Of Refractory Group Metal (i.e., Titanium (ti), Zirconium (zr), Hafnium (hf), Vanadium (v), Niobium (nb), Tantalum (ta), Chromium (cr), Molybdenum (mo), Tungsten (w), Or Alloy Thereof) Patents (Class 438/683)
  • Patent number: 10347581
    Abstract: A technique relates to fabricating a semiconductor device. A contact trench is formed in an inter-level dielectric layer. The contact trench creates an exposed portion of a semiconductor substrate through the inter-level dielectric layer. A gate stack is on the semiconductor substrate, and the inter-level dielectric layer is adjacent to the gate stack and the semiconductor substrate. A source/drain region is formed in the contact trench such that the source/drain region is on the exposed portion of the semiconductor substrate. Tin is introduced in the source/drain region to form an alloyed layer on top of the source/drain region, and the alloyed layer includes the tin and a source/drain material of the source/drain region. A trench layer is formed in the contact trench such that the trench layer is on top of the alloyed layer. A metallic liner layer is formed on the trench layer and the inter-level dielectric layer.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Oleg Gluschenkov, Jiseok Kim, Zuoguang Liu, Shogo Mochizuki, Hiroaki Niimi
  • Patent number: 10177030
    Abstract: Methods and structures for forming cobalt contact and/or cobalt interconnects includes depositing a stress control layer onto the cobalt layer prior to annealing after which the stress control layer can be removed. The stress control layer prevents formation of defects that can occur in the absence of the stress control layer.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: January 8, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hari P. Amanapu, Raghuveer R. Patlolla, Cornelius Brown Peethala, Chih-Chao Yang
  • Patent number: 10157953
    Abstract: Some embodiments of the present disclosure provide a back side illuminated (BSI) image sensor. The back side illuminated (BSI) image sensor includes a semiconductive substrate and an interlayer dielectric (ILD) layer at a front side of the semiconductive substrate. The ILD layer includes a dielectric layer over the semiconductive substrate and a contact partially buried inside the semiconductive substrate. The contact includes a silicide layer including a predetermined thickness proximately in a range from about 600 angstroms to about 1200 angstroms.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Chang Huang, Chi-Ming Lu, Jian-Ming Chen, Jung-Chih Tsao, Yao-Hsiang Liang
  • Patent number: 10079177
    Abstract: A method is provided for forming copper material over a substrate. The method includes forming a barrier layer over a substrate. Then, a depositing-soaking-treatment (DST) process is performed over the barrier layer. A copper layer is formed on the cobalt layer. The DST process includes depositing a cobalt layer on the barrier layer. Then, the cobalt layer is soaked with H2 gas at a first pressure. The cobalt layer is treated with a H2 plasma at a second pressure. The second pressure is lower than the first pressure.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: September 18, 2018
    Assignee: United Microelectronics Corp.
    Inventors: Ko-Wei Lin, Ying-Lien Chen, Chun-Ling Lin, Huei-Ru Tsai, Hung-Miao Lin, Sheng-Yi Su, Tzu-Hao Liu
  • Patent number: 9831240
    Abstract: A semiconductor device includes a gate on a substrate, a gate insulating layer along a sidewall and a bottom surface of the gate, and an L-shaped spacer structure on both sidewalls of the gate. A structure extends the distance between the gate and source/drain regions to either side of the gate.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: November 28, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Yeop Park, Leonelli Daniele, Shigenobu Maeda, Han-Su Oh, Woong-Gi Kim, Jong-Hyuk Lee, Ju-Seob Jeong
  • Patent number: 9633861
    Abstract: Embodiments of the present invention provide processes to selectively form a metal layer on a conductive surface, followed by flowing a silicon based compound over the metal layer to form a metal silicide layer. In one embodiment, a substrate having a conductive surface and a dielectric surface is provided. A metal layer is then deposited on the conductive surface. A metal silicide layer is formed as a result of flowing a silicon based compound over the metal layer. A dielectric is formed over the metal silicide layer.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: April 25, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Weifeng Ye, Mei-yee Shek, Mihaela Balseanu, Xiaojun Zhang, Xiaolan Ba, Yu Jin, Li-Qun Xia
  • Patent number: 9601430
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a dielectric layer positioned on the semiconductor substrate. The dielectric layer has a first recess. The semiconductor device structure includes a conductive structure filling the first recess. The conductive structure includes a first conductive layer and a second conductive layer. The first conductive layer is positioned over an inner wall and a bottom of the first recess. The first conductive layer has a second recess in the first recess. The second conductive layer fills the second recess. The first conductive layer and the second conductive layer include cobalt. The second conductive layer further includes at least one of sulfur, chlorine, boron, phosphorus, or nitrogen.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: March 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Rueijer Lin, Chen-Yuan Kao, Chun-Chieh Lin, Huang-Yi Huang
  • Patent number: 9484251
    Abstract: Methods of lightly implanting platinum, iridium, osmium, erbium, ytterbium, dysprosium, and gadolinium in semiconductor material in shallow depths by plasma-immersion ion implantation (PIII) and/or pulsed PIII are provided herein. Methods include depositing a liner layer prior to masking and implanting features to form n-type and p-type semiconductors and implanting materials through the liner layer. Methods are suitable for integration schemes involving fabrication of fin-type field effect transistors (FinFETs).
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: November 1, 2016
    Assignee: Lam Research Corporation
    Inventors: Paul Raymond Besser, William Worthington Crew, Jr., Sanjay Gopinath
  • Patent number: 9368467
    Abstract: A substrate structure is provided, including a substrate body and a plurality of circuits formed on the substrate body. At least one of the circuits has an electrical contact for connecting to an external element and the electrical contact is narrower in width than the circuit, thereby meeting the requirements of fine line/fine pitch and miniaturization, improving the product yield and reducing the fabrication cost.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: June 14, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chang-Fu Lin, Ho-Yi Tsai, Chin-Tsai Yao
  • Patent number: 9240323
    Abstract: A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: January 19, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chung-Hwan Shin, Sang-Bom Kang, Dae-Yong Kim, Jeong-Ik Kim, Chul-Sung Kim, Je-Hyung Ryu, Sang-Woo Lee, Hyo-Seok Choi
  • Patent number: 9029253
    Abstract: Nitrogen-containing phase-stabilized films, methods of forming phase-stabilized films, and structures and devices including the phase-stabilized films are disclosed. The phase-stabilized films include a matrix material and a phase stabilizer, which provides a morphologically stabilizing effect to a matrix material within the films. The phase-stabilized films may be used as, for example, gate electrodes and similar films in microelectronic devices.
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: May 12, 2015
    Assignee: ASM IP Holding B.V.
    Inventors: Robert Brennan Milligan, Fred Alokozai
  • Patent number: 9024388
    Abstract: One illustrative method disclosed herein includes forming replacement gate structures for an NMOS transistor and a PMOS transistor by forming gate insulation layers and a first metal layer for the devices from the same materials and selectively forming a metal-silicide material layer only on the first metal layer for the NMOS device but not on the PMOS device. One example of a novel integrated circuit product disclosed herein includes an NMOS device and a PMOS device wherein the gate insulation layers and the first metal layer of the gate structures of the devices are made of the same material, the gate structure of the NMOS device includes a metal silicide material positioned on the first metal layer of the NMOS device, and a second metal layer that is positioned on the metal silicide material for the NMOS device and on the first metal layer for the PMOS device.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: May 5, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Kisik Choi, Ruilong Xie
  • Patent number: 9006104
    Abstract: In one example, the method includes forming a metal layer on a silicon-containing structure, after forming the metal layer, performing an ion implantation process to implant silicon atoms into at least one of the metal layer and the silicon-containing structure and performing a first millisecond anneal process so as to form a first metal silicide region in the silicon-containing structure.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: April 14, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Vidmantas Sargunas
  • Patent number: 8981435
    Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.
    Type: Grant
    Filed: October 1, 2011
    Date of Patent: March 17, 2015
    Assignee: Intel Corporation
    Inventors: Sameer S. Pradhan, Subhash M. Joshi, Jin-Sung Chun
  • Patent number: 8946081
    Abstract: Embodiments of the invention include a method of cleaning a semiconductor substrate of a device structure and a method of forming a silicide layer on a semiconductor substrate of a device structure. Embodiments include steps of converting a top portion of the substrate into an oxide layer and removing the oxide layer to expose a contaminant-free surface of the substrate.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Ahmet Serkan Ozcan, Viraj Yashawant Sardesai, Cung Do Tran
  • Publication number: 20140363972
    Abstract: In one example, the method includes forming a metal layer on a silicon-containing structure, after forming the metal layer, performing an ion implantation process to implant silicon atoms into at least one of the metal layer and the silicon-containing structure and performing a first millisecond anneal process so as to form a first metal silicide region in the silicon-containing structure.
    Type: Application
    Filed: June 5, 2013
    Publication date: December 11, 2014
    Inventor: Vidmantas Sargunas
  • Patent number: 8900899
    Abstract: Novel processing methods for production of high-refractive index contrast and low loss optical waveguides are disclosed. In one embodiment, a “channel” waveguide is produced by first depositing a lower cladding material layer with a low refractive index on a base substrate, a refractory metal layer, and a top diffusion barrier layer. Then, a trench is formed with an open surface to the refractory metal layer. The open surface is subsequently oxidized to form an oxidized refractory metal region, and the top diffusion barrier layer and the non-oxidized refractory metal region are removed. Then, a low-refractive-index top cladding layer is deposited on this waveguide structure to encapsulate the oxidized refractory metal region. In another embodiment, a “ridge” waveguide is produced by using similar process steps with an added step of depositing a high-refractive-index material layer and an optional optically-transparent layer.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: December 2, 2014
    Inventor: Payam Rabiei
  • Patent number: 8865594
    Abstract: The invention provides a method of forming a film stack on a substrate, comprising performing a silicon containing gas soak process to form a silicon containing layer over the substrate, reacting with the silicon containing layer to form a tungsten silicide layer on the substrate, depositing a tungsten nitride layer on the substrate, subjecting the substrate to a nitridation treatment using active nitrogen species from a remote plasma, and depositing a conductive bulk layer directly on the tungsten nitride layer.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: October 21, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Sang-Hyeob Lee, Sang Ho Yu, Kai Wu
  • Patent number: 8835310
    Abstract: Electrodes, which contain molybdenum dioxide (MoO2) can be used in electronic components, such as memory or logic devices. The molybdenum-dioxide containing electrodes can also have little or no molybdenum element, together with a portion of molybdenum oxide, e.g., MoOx with x between 2 and 3. The molybdenum oxide can be present as molybdenum trioxide MoO3, or in Magneli phases, such as Mo4O11, MO8O23, or Mo9O26. The molybdenum-dioxide containing electrodes can be formed by annealing a multilayer including a layer of molybdenum and a layer of molybdenum oxide. The oxygen content of the multilayer can be configured to completely, or substantially completely, react with molybdenum to form molybdenum dioxide, together with leaving a small excess amount of molybdenum oxide MoOx with x>2.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: September 16, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Sergey Barabash, Dipankar Pramanik, Xuena Zhang
  • Patent number: 8828868
    Abstract: A method for forming a hard mask in semiconductor device fabrication comprises: forming first and second patterned material layers on a third material layer, the second patterned material layer only covering the top of predetermined regions of the first patterned material layer; changing a property of exposed top and side portions of the first patterned material layer using the second patterned material layer as a mask, forming property-changed roofs at the exposed top portions of the first patterned material layer and forming property-changed sidewalls with a predetermined width at the exposed side portions of the first patterned material layer; removing the second patterned material layer and portions of the first patterned material layer with exposed tops and an unchanged property located between the property-changed sidewalls, to form the hard mask.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: September 9, 2014
    Assignee: Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Zhongshan Hong
  • Patent number: 8809159
    Abstract: Provided are radiation enhanced resistive switching layers, resistive random access memory (ReRAM) cells including these layers, as well as methods of forming these layers and cells. Radiation creates defects in resistive switching materials that allow forming and breaking conductive paths in these materials thereby improving their resistive switching characteristics. For example, ionizing radiation may break chemical bonds in various materials used for such a layer, while non-ionizing radiation may form electronic traps. Radiation power, dozing, and other processing characteristics can be controlled to generate a distribution of defects within the resistive switching layer. For example, an uneven distribution of defects through the thickness of a layer may help with lowering switching voltages and/or currents. Radiation may be performed before or after thermal annealing, which may be used to control distribution of radiation created defects and other types of defects in resistive switching layers.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: August 19, 2014
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Yun Wang, Tony P. Chiang, Tim Minvielle, Takeshi Yamaguchi
  • Patent number: 8802552
    Abstract: A method for manufacturing a MOSFET includes the steps of: forming a gate oxide film on an active layer, forming a gate electrode on the gate oxide film, forming a source contact electrode in ohmic contact with the active layer, and forming an interlayer insulating film made of silicon dioxide so as to cover the gate electrode after the source contact electrode is formed. The step of forming a source contact electrode includes the steps of forming a metal layer including aluminum so as to be in contact with the active layer, and alloying the metal layer.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: August 12, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Taku Horii, Takeyoshi Masuda
  • Patent number: 8796103
    Abstract: Provided are methods of forming nonvolatile memory elements including resistance switching layers. A method involves diffusing oxygen from a precursor layer to one or more reactive electrodes by annealing. At least one electrode in a memory element is reactive, while another may be inert. The precursor layer is converted into a resistance switching layer as a result of this diffusion. The precursor layer may initially include a stoichiometric oxide that generally does not exhibit resistance switching characteristics until oxygen vacancies are created. Metals forming such oxides may be more electronegative than metals forming a reactive electrode. The reactive electrode may have substantially no oxygen at least prior to annealing. Annealing may be performed at 250-400° C. in the presence of hydrogen. These methods simplify process control and may be used to form nonvolatile memory elements including resistance switching layers less than 20 Angstroms thick.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: August 5, 2014
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Mihir Tendulkar, Tim Minvielle, Yun Wang, Takeshi Yamaguchi
  • Publication number: 20140206190
    Abstract: Embodiments of the present invention include methods of forming a silicide layer on a semiconductor substrate. In an exemplary embodiment, a metal layer may first be deposited above a semiconductor substrate using a chemical vapor deposition process with a metal amidinate precursor and then the semiconductor substrate may be annealed, causing the semiconductor substrate to react with the metal layer forming a metal-rich silicide layer on the semiconductor substrate. Embodiments may also include forming a low-oxygen capping layer above the metal layer prior to annealing the semiconductor substrate to protect the metal layer from oxidation. The low-oxygen capping layer may, for example, be made of titanium nitride containing less than 20 parts per million of oxygen. Embodiments may further include forming a silicide layer using the above process in a contact hole above a source/drain region of a field-effect transistor, and forming a metal contact above the silicide layer.
    Type: Application
    Filed: January 23, 2013
    Publication date: July 24, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: BAOZHEN LI, YUN Y. WANG, KEITH KWONG HON WONG, CHIH-CHAO YANG
  • Patent number: 8772159
    Abstract: A method of fabricating an electrical contact comprises the following steps. A substrate having at least a silicon region is provided. At least an insulation layer is formed on the substrate, wherein the insulation layer comprises at least a contact hole which exposes the silicon region. A metal layer is formed on sidewalls and bottom of the contact hole. An annealing process is performed to form a first metal silicide layer in the silicon region nearby the bottom of the contact hole. A conductive layer covering the metal layer and filling up the contact hole is then formed, wherein the first metal silicide layer is transformed into a second metal silicide layer when the conductive layer is formed.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: July 8, 2014
    Assignee: United Microelectronics Corp.
    Inventors: I-Ming Tseng, Tsung-Lung Tsai, Yi-Wei Chen
  • Patent number: 8698313
    Abstract: A nonvolatile semiconductor memory apparatus according to an embodiment includes: a semiconductor layer; a first insulating film formed on the semiconductor layer, the first insulating film being a single-layer film containing silicon oxide or silicon oxynitride; a charge trapping film formed on the first insulating film; a second insulating film formed on the charge trapping film; and a control gate electrode formed on the second insulating film. A metal oxide exists in an interface between the first insulating film and the charge trapping film, the metal oxide comprises material which is selected from the group of Al2O3, HfO2, ZrO2, TiO2, and MgO, the material is stoichiometric composition, and the charge trapping film includes material different from the material of the metal oxide.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: April 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Izumi Hirano, Shosuke Fujii, Yuichiro Mitani, Naoki Yasuda
  • Publication number: 20140057399
    Abstract: Techniques for forming a smooth silicide without the use of a cap layer are provided. In one aspect, a cap layer-free method for forming a silicide is provided. The method includes the following steps. A semiconductor material selected from: silicon and silicon germanium is provided. At least one silicide metal is deposited on the semiconductor material. The semiconductor material and the at least one silicide metal are annealed at a temperature of from about 400° C. to about 800° C. for a duration of less than or equal to about 10 milliseconds to form the silicide. A FET device and a method for fabricating a FET device are also provided.
    Type: Application
    Filed: August 24, 2012
    Publication date: February 27, 2014
    Applicant: International Business Machines Corporation
    Inventors: Joseph S. Newbury, Kenneth Parker Rodbell, Zhen Zhang, Yu Zhu
  • Patent number: 8642434
    Abstract: While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Yaocheng Liu, Dureseti Chidambarrao, Oleg Gluschenkov, Judson R. Holt, Renee T. Mo, Kern Rim
  • Patent number: 8642471
    Abstract: The present invention provides a method for manufacturing a semiconductor structure. The method can effectively reduce the contact resistance between source/drain regions and a contact layer by forming two contact layers of different thickness on the surfaces of the source/drain regions. Further, the present invention provides a semiconductor structure, which has reduced the contact resistance.
    Type: Grant
    Filed: February 27, 2011
    Date of Patent: February 4, 2014
    Assignee: The institute of Microelectronics, Chinese Academy of Science
    Inventors: Haizhou Yin, Jun Luo, Huilong Zhu, Zhijiong Luo
  • Patent number: 8642468
    Abstract: Embodiments of the invention generally provide methods for depositing metal-containing materials and compositions thereof. The methods include deposition processes that form metal, metal carbide, metal silicide, metal nitride, and metal carbide derivatives by a vapor deposition process, including thermal decomposition, CVD, pulsed-CVD, or ALD.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: February 4, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Seshadri Ganguli, Srinivas Gandikota, Yu Lei, Xinliang Lu, Sang Ho Yu, Hoon Kim, Paul F. Ma, Mei Chang, Maitreyee Mahajani, Patricia M. Liu
  • Publication number: 20140001576
    Abstract: Semiconductor devices, methods and apparatus for forming the same are provided. The semiconductor device includes a substrate having a source and drain region and a gate electrode stack on the substrate between the source and drain regions. The gate electrode stack includes a conductive film layer on a gate dielectric layer, a refractory metal silicon nitride film layer on the conductive film layer, and a tungsten film layer on the refractory metal silicon nitride film layer. In one embodiment, the method includes positioning a substrate within a processing chamber, wherein the substrate includes a source and drain region, a gate dielectric layer between the source and drain regions, and a conductive film layer on the gate dielectric layer. The method also includes depositing a refractory metal silicon nitride film layer on the conductive film layer and depositing a tungsten film layer on the refractory metal silicon nitride film layer.
    Type: Application
    Filed: June 19, 2013
    Publication date: January 2, 2014
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Srinivas GANDIKOTA, Zhendong LIU, Jianxin LEI, Rajkumar JAKKARAJU
  • Patent number: 8617992
    Abstract: Methods of forming contacts (and optionally, local interconnects) using an ink comprising a silicide-forming metal, electrical devices such as diodes and/or transistors including such contacts and (optional) local interconnects, and methods for forming such devices are disclosed. Electrical devices, such as diodes and transistors may be made using such printed contact and/or local interconnects. A metal ink may be printed for contacts as well as for local interconnects at the same time, or in the alternative, the printed metal can act as a seed for electroless deposition of other metals if different metals are desired for the contact and the interconnect lines. This approach advantageously reduces the number of processing steps and does not necessarily require any etching.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: December 31, 2013
    Assignee: Kovio, Inc.
    Inventors: Aditi Chandra, Arvind Kamath, James Montague Cleeves, Joerg Rockenberger, Mao Takashima, Erik Scher
  • Publication number: 20130334693
    Abstract: A method for forming a raised silicide contact, the method including depositing a layer of silicon using a gas cluster implant technique which accelerates clusters of silicon atoms causing them to penetrate a surface oxide on a top surface of the silicide; heating the silicide including the silicon layer to a temperature from about 300° C. to about 950° and holding the temperature for about 0.1 miliseconds to about 600 seconds in an inert atmosphere causing silicon from the layer of silicon to react with the remaining silicide partially formed in the silicon containing substrate; and forming a raised silicide from the layer of silicon, wherein the thickness of the raised silicide is greater than the thickness of the silicide and the raised silicide protrudes above a top surface of the silicon containing substrate.
    Type: Application
    Filed: June 18, 2012
    Publication date: December 19, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Emre Alptekin, Nathaniel Berliner, Christian Lavoie, Kam-Leung Lee, Ahmet Serkan Ozcan
  • Patent number: 8603882
    Abstract: A method for making a dual silicide or germanide semiconductor comprises steps of providing a semiconductor substrate, forming a gate, forming source/drain regions, forming a first silicide, reducing spacers thickness and forming a second silicide. Forming a gate comprises forming an insulating layer over the semiconductor substrate, and forming the gate over the insulating layer. Forming source/drain regions comprises forming lightly doped source/drain regions in the semiconductor substrate adjacent to the insulating layer, forming spacers adjacent to the gate and over part of the lightly doped source/drain regions, and forming heavily doped source/drain regions in the semiconductor substrate. The first silicide is formed on an exposed surface of lightly and heavily doped source/drain regions. The second silicide is formed on an exposed surface of lightly doped source/drain regions. A first germanide and second germanide may replace the first silicide and the second silicide.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: December 10, 2013
    Assignee: National Applied Research Laboratories
    Inventors: Szu-Hung Chen, Hung-Min Chen, Yu-Sheng Lai, Wen-Fa Wu, Fu-Liang Yang
  • Patent number: 8592305
    Abstract: Provided are methods of providing aluminum-doped TaSix films. Doping TaSix films allows for the tuning of the work function value to make the TaSix film better suited as an N-metal for NMOS applications. One such method relates to soaking a TaSix film with an aluminum-containing compound. Another method relates to depositing a TaSix film, soaking with an aluminum-containing compound, and repeating for a thicker film. A third method relates to depositing an aluminum-doped TaSix film using tantalum, aluminum and silicon precursors.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: November 26, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Xinliang Lu, Seshadri Ganguli, Shih Chung Chen, Atif Noori, Maitreyee Mahajani, Mei Chang
  • Patent number: 8580666
    Abstract: Methods for forming memory devices and integrated circuitry, for example, DRAM (dynamic random access memory) circuitry, structures and devices resulting from such methods, and systems that incorporate the devices are provided.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: November 12, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Terrence McDaniel, Sandra Tagg, Fred Fishburn
  • Patent number: 8580686
    Abstract: Formation of a semiconductor device with NiGe or NiSiGe and with reduced consumption of underlying Ge or SiGe is provided. Embodiments include co-sputtering nickel (Ni) and germanium (Ge), forming a first Ni/Ge layer on a Ge or silicon germanium (SiGe) active layer, depositing titanium (Ti) on the first Ni/Ge or Ni/Si/Ge layer, forming a Ti intermediate layer, co-sputtering Ni and Ge on the Ti intermediate layer, forming a second Ni/Ge layer, and performing a rapid thermal anneal (RTA) process.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: November 12, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Derya Deniz
  • Patent number: 8563355
    Abstract: A phase change memory (PCM) cell includes a transistor, a PCM structure, and a heater. The transistor has a first current electrode and a second current electrode in a structure, and a channel region having a first portion along a first sidewall of the structure and having a second portion along a second sidewall of the structure. The second sidewall is opposite the first sidewall. The transistor has a control electrode that has a first portion adjacent to the first sidewall and a second portion adjacent to the second sidewall. The PCM structure exhibits first and second resistive values when in first and second phase states, respectively. The heater is on the structure and produces heat when current flows through the heater for changing the phase state of the phase change structure.
    Type: Grant
    Filed: January 18, 2008
    Date of Patent: October 22, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo Mathew, Tushar P. Merchant, Ramachandran Muralidhar, Rajesh A. Rao
  • Patent number: 8536010
    Abstract: Methods for fabricating a semiconductor device are disclosed. A metal-rich silicide and/or a mono-silicide is formed on source/drain (S/D) regions. A millisecond anneal is provided to the metal-rich silicide and/or the mono-silicide to form a di-silicide with limited spikes at the interface between the silicide and substrate. The di-silicide has an additive which can lower the electron Schottky barrier height.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: September 17, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wen Nieh, Hung-Chang Hsu, Wen-Chi Tsai, Mei-Yun Wang, Chii-Ming Wu, Wei-Jung Lin, Chih-Wei Chang
  • Patent number: 8492261
    Abstract: A method for manufacturing a III-V CMOS device is disclosed. The device includes a first and second main contact and a control contact. In one aspect, the method includes providing the control contact by using damascene processing. The method thus allows obtaining a control contact with a length of between about 20 nm and 5 ?m and with good Schottky behavior. Using low-resistive materials such as Cu allows reducing the gate resistance thus improving the high-frequency performance of the III-V CMOS device.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: July 23, 2013
    Assignee: IMEC
    Inventors: Marleen Van Hove, Joff Derluyn
  • Patent number: 8476164
    Abstract: A method of manufacturing semiconductor device is provided. A substrate at least with a patterned silicon-containing layer on the substrate and spacers adjacent to the patterned silicon-containing layer is provided. A metal layer is formed on the substrate and covers the patterned silicon-containing layer and spacers. Then, a capping layer is formed on the metal layer. A first rapid thermal process is performed to at least make a portion of the metal layer react with the substrate around the spacers to form transitional silicides. The capping layer and the unreacted portions of the metal layer are removed. A first nitride film with a first tensile stress S1 is formed on the substrate. A second rapid thermal process is performed to transfer the transitional silicide to a silicide and transfer the first nitride film to a second nitride film with a second tensile stress S2, wherein S2>S1.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: July 2, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chin-Fu Lin, Chin-Cheng Chien, Chih-Chien Liu, Chia-Lin Hsu, Chun-Yuan Wu
  • Patent number: 8470700
    Abstract: A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: June 25, 2013
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Eng Huat Toh, Jae Gon Lee, Chung Foong Tan, Shiang Yang Ong, Elgin Quek
  • Patent number: 8435886
    Abstract: A method and apparatus are presented for reducing halide-based contamination within deposited titanium-based thin films. Halide adsorbing materials are utilized within the deposition chamber to remove halides, such as chlorine and chlorides, during the deposition process so that contamination of the titanium-based film is minimized. A method for regenerating the halide adsorbing material is also provided.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: May 7, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Cem Basceri, Donald L. Westmoreland
  • Patent number: 8435862
    Abstract: The method of manufacturing a semiconductor device comprises forming a metal film over silicon regions and insulating films; performing a first heat treatment under an oxygen atmosphere containing oxygen as a main ingredient, to form a first silicide film in the silicon region by reacting the metal film and the silicon region, and to simultaneously form a metal oxide by oxidizing the entire surface of the metal film from the surface side thereof; and selectively removing the metal oxide and the unreacted metal film using a chemical.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: May 7, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Tonegawa, Tomotake Morita, Norihiko Matsuzaka
  • Patent number: 8395266
    Abstract: A semiconductor memory device includes a titanium layer and a titanium nitride layer formed on a substrate, a thin layer formed on the titanium nitride layer, and a metal layer formed on the thin layer, wherein the thin layer increases a grain size of the metal layer.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: March 12, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kwan-Yong Lim, Min-Gyu Sung, Heung-Jae Cho
  • Patent number: 8377812
    Abstract: The present invention provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer. The method further includes providing a gate electrode on the gate oxide layer and disposing a dielectric layer on the gate electrode and the gate oxide layer. The method further includes etching a portion of the dielectric layer and a portion of the gate oxide layer to form sidewalls on the gate electrode. A metal layer is disposed on the gate electrode, the sidewalls and the source region. The method further includes forming a gate contact and a source contact by subjecting the metal layer to a temperature of at least about 800° C. The gate contact and the source contact comprise a metal silicide. The distance between the gate contact and the source contact is less than about 0.6 ?m.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: February 19, 2013
    Assignee: General Electric Company
    Inventors: Kevin Sean Matocha, Gregory Keith Dudoff, William Gregg Hawkins, Zachary Matthew Stum, Stephen Daley Arthur, Dale Marius Brown
  • Patent number: 8377556
    Abstract: Systems and methods for creating carbon nanotubes are disclosed that comprise a growing a nanotube on a tri-layer material. This tri-layer material may comprise a catalyst and at least one layer of Ti. This tri-layer material may be exposed to a technique that is used to grow a nanotube on a material such as a deposition technique.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: February 19, 2013
    Assignee: STMicroelectronics Asia Pacific Pte., Ltd.
    Inventors: Adeline Chan, Ivan Teo, Zhonglin Miao, Shanzhong Wang, Vincenzo Vinciguerra
  • Patent number: 8372750
    Abstract: According to one embodiment of the invention, a method for nickel silicidation includes providing a substrate having a source region, a gate region, and a drain region, forming a source in the source region and a drain in the drain region, annealing the source and the drain, implanting, after the annealing the source and the drain, a heavy ion in the source region and the drain region, depositing a nickel layer in each of the source and drain regions, and heating the substrate to form a nickel silicide region in each of the source and drain regions by heating the substrate.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: February 12, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Amitabh Jain, Peijun Chen, Jorge A. Kittl
  • Patent number: 8357611
    Abstract: A semiconductor device having good TFT characteristics is realized. By using a high purity target as a target, using a single gas, argon (Ar), as a sputtering gas, setting the substrate temperature equal to or less than 300° C., and setting the sputtering gas pressure from 1.0 Pa to 3.0 Pa, the film stress of a film is made from ?1×1010 dyn/cm2 to 1×1010 dyn/cm2. By thus using a conducting film in which the amount of sodium contained within the film is equal to or less than 0.3 ppm, preferably equal to or less than 0.1 ppm, and having a low electrical resistivity (equal to or less than 40 ??·cm), as a gate wiring material and a material for other wirings of a TFT, the operating performance and the reliability of a semiconductor device provided with the TFT can be increased.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: January 22, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Keiji Sato, Shunpei Yamazaki
  • Patent number: 8349732
    Abstract: A device and a method for forming a metal silicide is presented. A device, which includes a gate region, a source region, and a drain region, is formed on a substrate. A metal is disposed on the substrate, followed by a first anneal, forming a metal silicide on at least one of the gate region, the source region, and the drain region. The unreacted metal is removed from the substrate. The metal silicide is implanted with atoms. The implant is followed by a super anneal of the substrate.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: January 8, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry Chuang, Hung-Chih Tsai, Keh-Chiang Ku, Kong-Beng Thei, Mong Song Liang