Abstract: A method for forming a thin aluminum-nitride film (112). Solid hydrazine cyanurate is heated to produce in-situ hydrazine (N2H4). The in-situ hydrazine reacts with a previously deposited ailminum layer (108) to form aluminum-nitride (112).

Abstract: A method for forming aluminum bumps that has significantly reduced processing steps than the conventional method is disclosed. The method utilizes a chemical vapor deposition technique for the selective deposition of aluminum into an opening for forming the bump and then a wet etch process for removing a polymide layer that functioned both as a photoresist layer for providing an opening in a passivation layer and as a support for a via hole during the selective aluminum deposition process. The thickness of the passivation layer and the polyimide layer formed on top of the metal I/O pad is important since it determines the height of the aluminum bump formed.

Abstract: A method for manufacturing a semiconductor device that fills contact holes with conductive material such as aluminum or an aluminum alloy. A semiconductor device is manufactured by the process of forming an opening such as a contact hole in an interlayer dielectric film formed on a semiconductor substrate having a device element formed thereon. A first film and a second film made of conductive material such as aluminum or an alloy containing aluminum are formed on the interlayer dielectric film and the opening. The second film is then gradually cooled.

Abstract: A method of manufacturing a semiconductor device, according to the present invention comprises a step for forming an insulating film over a semiconductor wafer and thereafter subjecting the same to photolithography and etching to thereby define a contact hole, a step for forming an adhesive layer over the insulating film with the contact hole defined therein, a step for placing the interior of a processing chamber under an atmosphere uncontaining oxygen and subjecting the adhesive layer to heat treatment, a step for setting the temperature of the semiconductor wafer to less than or equal to a temperature equivalent to energy of such an extent as to cut the bonding between atoms which form the adhesive layer and thereafter taking the semiconductor wafer out of the processing chamber, and a step for forming an embedding film to be embedded in the contact hole.

Abstract: The present invention relates generally to an improved apparatus and process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron aperture width applications. In one aspect of the invention, a dielectric layer is formed over a conducting member. A thin nucleation layer is then deposited onto the dielectic layer prior to etching high aspect ratio apertures through the nucleation and dielectric layers to expose the underlying conducting member on the aperture floor. A CVD metal layer is then deposited onto the structure to achieve selective deposition within the apertures, while preferably also forming a blanket layer on the field. The present apparatus and process reduce the number of steps necessary to fabricate CVD metal interconnects and layers that are substantially void-free and planarized.

Abstract: A semiconductor device and manufacturing method thereof in which upon patterning of an Al strain metal wiring, an occurrence of side etch due to an emission of oxygen from an interlayer insulating film of an underlayer is prevented. A silicon nitride film or the like containing no oxygen is formed on the surface portion of an under BPSG film. A TiW film or the like serving as a barrier metal and an Al strain metal film are formed on the silicon nitride film. A side wall protecting film by carbon generated from an organic substance photoresist is preferably formed, thereby preventing the side etch of the Al strain metal film.

Abstract: A metallization structure and method for fabricating such a metallization structure are presented. The present method preferably includes forming a void within a metal layer. The void may have a void pressure level, which is preferably approximately equal to the pressure in a deposition chamber in which the metal layer is arranged when the void is formed. Subsequently, the void may be collapsed by increasing a pressure level outside of the void to a collapsing pressure level significantly above the void pressure level. Increasing a pressure level outside of the void preferably includes increasing a pressure level within the deposition chamber to a collapsing pressure sufficient to collapse the void. A metallization structure formed by such a process may be substantially void-free, even in narrow, high aspect ratio metallization cavities.

Abstract: A conductive structure includes a conductively doped semiconductive material and an overlying WxSiyNz comprising material, where each of “x”, “y” and “z” is greater than zero. Insulative material is formed over the WxSiyNz comprising material of the conductive structure. A contact opening is etched through the insulative material and through the WxSiyNz material effective to expose the conductively doped semiconductive material. The contact opening etching includes at least one dry etch, followed by at least one wet etch, followed by at least one dry etch. At least one wet etch occurs before etching the WxSiyNz comprising material. After the contact opening etching, conductive material is formed within the contact opening in electrical connection with the conductively doped semiconductive material. Other aspects are disclosed.

Abstract: After forming a barrier film on a silicon-containing film including silicon as a main component, a high-melting-point metal film is deposited on the barrier film, so as to form a laminated structure including the silicon-containing film, the barrier film and the high-melting-point metal film. The laminated structure is subjected to a heat treatment at a temperature of 750° C. or more. The barrier film is formed by forming a first metal film of a nitride of a metal on the silicon-containing film; forming, on the first metal film, a second metal film of the metal or the nitride of the metal with a smaller nitrogen content than the first metal film; and forming, on the second metal film, a third metal film of the nitride of the metal with a larger nitrogen content than the second metal film.

Abstract: A dual damascene process capable of reliably producing aluminum interconnects that exhibit improved electromigration characteristics over aluminum interconnects produced by conventional RIE techniques. In particular, the dual damascene process relies on a PVD-Ti/CVD-TiN barrier layer to produce aluminum lines that exhibit significantly reduced saturation resistance levels and/or suppressed electromigration, particularly in lines longer than 100 micrometers. The electromigration lifetime of the dual damascene aluminum line is strongly dependent on the materials and material fill process conditions. Significantly, deviations in materials and processing can result in electromigration lifetimes inferior to that achieved with aluminum RIE interconnects. In one example, current densities as high as 2.5 MA/cm2 are necessary to induce a statistically relevant number of fails due to electromigration.

Abstract: An improved method of forming a semiconductor device is described. In that method, a dielectric layer that comprises a carbon doped oxide is formed on a substrate. After a first etched region is formed in the dielectric layer, that region is filled with a sacrificial light absorbing material. A layer of photoresist is then deposited and patterned, followed by forming a second etched region by removing part of the sacrificial light absorbing material and a second part of the dielectric layer. Remaining portions of the photoresist are then removed by exposing the resulting device to a plasma generated from a forming gas. The device is then exposed to a solution for removing the remaining portions of the sacrificial light absorbing material.

Abstract: The present invention is a method of fabricating interconnects. A semiconductor substrate having a dielectric layer is provided. The dielectric layer has a via opening therein, which exposes the semiconductor substrate. Next, the surfaces of the via opening is covered with a conformal titanium layer formed by a sputtering process. The surface of the conformal titanium layer is covered with an Al—Si—Cu alloy layer formed by a sputtering process at a temperature of about 0° C. to 200° C. Then, the surface of the Al—Si—Cu alloy layer is covered with an Al—Cu alloy layer formed by a sputtering process at a temperature of about 380° C. to 450° C., which Al—Cu alloy layer fills the via opening. The Al—Cu alloy layer, the Al—Si—Cu alloy layer and the wetting layer on the dielectric layer are patterned by photolithography and etching process.

Abstract: A method with three embodiments of manufacturing metal lines and solder bumps using electroless deposition techniques. The first embodiment uses a PdSix seed layer 50 for electroless deposition. The PdSix layer 50 does not require activation. A metal line is formed on a barrier layer 20 and an adhesion layer 30. A Palladium silicide seed layer 50 is then formed and patterned. Ni, Pd or Cu is electroless deposited over the Palladium silicide layer 50 to form a metal line. The second embodiment selectively electrolessly deposits metal 140 over an Adhesion layer 130 composed of Poly Si, Al, or Ti. A photoresist pattern 132 is formed over the adhesion layer. A metal layer 140 of Cu or Ni is electrolessly deposited over the adhesion layer. The photoresist layer 132 is removed and the exposed portion of the adhesion layer 130 and the underlying barrier metal layer 120 are etched thereby forming a metal line.

Abstract: Deposited dielectric layers for a semiconductor device are typically formed in a chemical vapor deposition. Often a hydrogen by-product is formed. Especially in a plasma enhanced chemical vapor deposition process, the hydrogen by-product can form free radicals that are introduced into the dielectric layers. The hydrogen free radicals can affect the stability of the threshold and breakdown voltage of MOSFET transistors. Deuterium introduced into the CVD chamber competes to enter the dielectric layer with the hydrogen. The deuterium prevents some of the hydrogen free radicals from entering the dielectric layer and thus increases MOSFET reliability.

Abstract: To form a wiring electrode having excellent contact function, in covering a contact hole formed in an insulating film, a film of a wiring material comprising aluminum or including aluminum as a major component is firstly formed and on top of the film, a film having an element belonging to 12 through 15 groups as a major component is formed and by carrying out a heating treatment at 400° C. for 0.5 through 2 hr in an atmosphere including hydrogen, the wiring material is provided with fluidity and firm contact is realized.

Abstract: Disclosed is a semiconductor device including a semiconductor substrate, an interlayer insulating film formed on one main surface of the semiconductor substrate and having a concave portion, a liner film formed on the inner surface of the concave portion, a wiring layer formed inside the concave portion with the liner film interposed therebetween, and an agglomeration suppressing material contained in the wiring layer for suppressing agglomeration of the material constituting the wiring layer. The agglomeration suppressing material is selected from the group consisting of O, N, Nb, Ta, Ti, W and C.

Abstract: This invention relates to a process for forming a metal interconnect comprising the steps of forming a concave in an insulating film formed on a substrate, forming a copper-containing metal film over the whole surface such that the concave is filled with the metal and then polishing the copper-containing metal film by chemical mechanical polishing, characterized in that the polishing step is conducted using a chemical mechanical polishing slurry comprising a polishing material, an oxidizing agent and an adhesion inhibitor preventing adhesion of a polishing product to a polishing pad, while contacting the polishing pad to a polished surface with a pressure of at least 27 kPa. This invention allows us to prevent adhesion of a polishing product to a polishing pad and to form a uniform interconnect layer with an improved throughput, even when polishing a large amount of copper-containing metal during a polishing step.

Abstract: A novel method of using lasers for generating driving energy for activating P-type compound semiconductor films and reducing the resistivity thereof. The P-type compound semiconductor films are made from III-V nitrides or II-VI group compounds doped with P-type impurity. The present invention can be carried out in the ambience of atmosphere rather than in the ambience of nitrogen gas. In addition, adjusting the power and focusing distance of a laser source, and the power density can change the time required by the activating process.

Abstract: A method is provided for forming a metal wiring layer of a semiconductor device, which is performed in an airtight space, the pressure of which is maintained below atmospheric pressure, to form a metal deposition prevention layer. An interlayer dielectric layer pattern is formed on a semiconductor substrate so as to define a hole region. A metal film is formed on the top surface of the interlayer dielectric layer pattern under a vacuum state so as to expose the side walls of the hole region. The metal layer is oxidized in the airtight space, the pressure of which is maintained below atmospheric pressure in an oxygen atmosphere, thereby forming a metal deposition prevention layer. A metal liner is selectively formed at the side walls of the hole region. A metal layer is formed inside the hole region defined by the metal liner and on the metal deposition prevention layer. The metal liner is heat-treated and reflowed.

Abstract: A process used during the formation of a semiconductor device comprises the steps of placing a plurality of semiconductor wafers each having a surface into a chamber of a batch wafer processor such as a diffusion furnace. The wafers are heated to a temperature of between about 300° C. and about 550° C. With the wafers in the chamber, at least one of ammonia and hydrazine is introduced into the chamber, then a precursor comprising trimethylethylenediamine tris(dimethylamino)titanium and/or triethylaluminum is introduced into the chamber. In the chamber, a layer comprising aluminum nitride is simultaneously formed over the surface of each wafer. The inventive process allows for the formation of aluminum nitride or titanium aluminum nitride over the surface of a plurality of wafers simultaneously. A subsequent anneal of the aluminum nitride layer or the titanium aluminum nitride layer can be performed in situ.

Abstract: A method of forming interconnect structures in a semiconductor device, comprising the following steps. A semiconductor structure is provided. In the first embodiment, at least one metal line is formed over the semiconductor structure. A silicon-rich carbide barrier layer is formed over the metal line and semiconductor structure. Finally, a dielectric layer, that may be fluorinated, is formed over the silicon-rich carbide layer. In the second embodiment, at least one fluorinated dielectric layer, that may be fluorinated, is formed over the semiconductor structure. The dielectric layer is patterned to form an opening therein. A silicon-rich carbide barrier layer is formed within the opening. A metallization layer is deposited over the structure, filling the silicon-rich carbide barrier layer lined opening. Finally, the metallization layer may be planarized to form a planarized metal structure within the silicon-rich carbide barrier layer lined opening.

Abstract: Integrated circuits, the key components in thousands of electronic and computer products, include interconnected networks of electrical components. The components are typically wired, or interconnected, together with aluminum wires. In recent years, researchers have begun using copper instead of aluminum to form integrated-circuit wiring, because copper offers lower electrical resistance and better reliability at smaller dimensions. However, use of copper typically requires forming a diffusion barrier to prevent contamination of other parts of an integrated circuit and forming a seed layer to facilitate copper plating steps. Unfortunately, typical diffusion barrier materials add appreciable resistance to the copper wiring, and thus negate some of the advantages of using copper. Moreover, conventional methods of forming the diffusion barriers and seed layers require use of separate wafer-processing chambers, giving rise to transport delays and the introduction of defect-causing particles.

Abstract: The present invention relates generally to an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal is deposited onto the previously formed CVD metal layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD metal layer is substantially void-free.

Abstract: The invention relates to a process for filling a multiplicity of recesses (3) formed in an exposed surface of a workpiece (1), wherein the mouths of the recesses (3) are closed by the deposition of a layer (10) and the layer is subjected to elevated temperature and pressure to force material from the layer down into the recesses. In the particular embodiments described, the elevated temperature is achieved by supplying very short thermal pulses, for example, from a light source such as a laser or a halogen light and preferably this thermal pulse is applied after the elevated pressure has been achieved.

Abstract: A pad metal film used to fit a conductor for external connection composed of a bump-like or wire-like conductor can be formed by reduced numbers of processes. A semiconductor device is so configured that a trench for interconnect with its diameter of about 50 &mgr;m and its depth of about 2 &mgr;m is formed on a protective insulating film, formed on a semiconductor substrate, with a thickness of 3 to 4 &mgr;m, and in the trench for interconnect is imbedded an uppermost-layered copper wiring through a first barrier metal film composed of a titanium nitride with a thickness of about 50 nm. Furthermore, approximately in the center region of the upper-layered copper wiring is imbedded a copper pad film through a second barrier metal film with a thickness of about 70 nm.

Abstract: A method of forming a semiconductor device having aluminum lines therein, wherein the occurrence of lateral extrusions and voids are reduced. The method comprises the formation of a metal stack on a surface of the substrate, wherein the aluminum layer of the metal stack is deposited under controlled conditions; etching the metal lines in the metal stack; and exposing the substrate to a subsequent anneal.

Abstract: The present disclosure pertains to particular Ti/TiN/TiNx barrier/wetting layer structures which enable the warm aluminum filling of high aspect vias while providing an aluminum fill exhibiting a high degree of aluminum <111> crystal orientation. It has been discovered that an improved Ti/TiN/TiNx barrier layer deposited using IMP techniques can be obtained by increasing the thickness of the first layer of Ti to range from greater than about 100 Å to about 500 Å (the feature geometry controls the upper thickness limit); by decreasing the thickness of the TiN second layer to range from greater than about 100 Å to less than about 800 Å (preferably less than about 600 Å); and, by controlling the application of the TiNx third layer to provide a Ti content ranging from about 50 atomic percent titanium (stoichiometric) to about 100 atomic percent titanium.

Abstract: A corrosion resistant component of semiconductor processing equipment such as a plasma chamber includes a diamond containing surface and process for manufacture thereof.

Abstract: A method of isolating an exposed conductive surface. An aluminum layer (130) is selectively formed over the exposed conductive (106) surface (e.g., Cu) but not over the surrounding dielectric (110) surface using a thermal CVD process. The aluminum layer (130) is then oxidized to form a thin isolating aluminum-oxide (108) over only the conductive surface. The isolating aluminum-oxide provides a barrier for the Cu while taking up minimal space and reducing the effective dielectric constant.

Abstract: In accordance with the objectives of the invention a new method is provided to create aluminum pads that overlay an electrical contact point. A layer of passivation is deposited over the surface that contains one or more electrical contact points, the layer of passivation is patterned thereby creating openings in the layer of passivation that overlay and align with one or more of the contact points. Under the first embodiment of the invention, a layer of AlCu is deposited over the patterned layer of passivation thereby including the openings that have been created in the layer of passivation. The deposited layer of AlCu is patterned and etched thereby creating the required AlCu bond pad. In addition to creating the required AlCu bond pad, the etch of the layer of AlCu also creates a pattern of dummy AlCu pads that are not in contact with any underlying points of electrical contact but that are located on the surface of the layer of passivation.

Abstract: A method of enriching the surface of a substrate with a solute material that was originally dissolved in the substrate material, to yield a uniform dispersion of the solute material at the substrate surface. The method generally entails the use of a solvent material that is more reactive than the solute material to a chosen reactive agent. The surface of the substrate is reacted with the reactive agent to preferentially form a reaction compound of the solvent material at the surface of the substrate. As the compound layer develops, the solute material segregates or diffuses out of the compound layer and into the underlying substrate, such that the region of the substrate nearest the compound layer becomes enriched with the solute material. At least a portion of the compound layer is then removed without removing the underlying enriched region of the substrate.

Abstract: Disclosed is a process for depositing an aluminum oxide thin film necessary for semiconductor devices. The process includes the steps of: subjecting a gaseous organoaluminum compound as an aluminum source in contact with a target substrate and depositing aluminum using plasma, which steps are sequentially repeated to form an aluminum thin film, and further the step of oxidizing the aluminum thin film using oxygen plasma. This deposition cycle is repeated to obtain an aluminum oxide thin film.

Abstract: A method of forming an organic low k layer, for use as an interlevel dielectric layer in semiconductor integrated circuits, has been developed. An organic low k layer, such as a poly arylene ether layer, with a dielectric constant between about 2.6 to 2.8, is applied on an underlying metal interconnect pattern. The moisture contained in the as applied, organic low k layer, or the moisture absorbed by the organic low k layer, due to exposure to the environment, is then reduced via a high density plasma treatment, performed in a nitrogen ambient. The reduction in moisture can be accomplished, even when the organic low k layer had been exposed to the environment for a period of time as great as three months. The dielectric constant, of the organic low k layer, remains unchanged, as a result of the high density plasma treatment.

Abstract: A dual damascene manufacturing process, which is applicable on a dual damascene structure, is described. The etching stop layer at a bottom of the trench line is removed followed by a thermal treatment to smooth out the surface at the bottom of the trench line and in the via to form a larger and smoother opening at the top part of the via. The via and the trench line are then filled with a barrier layer and a metal layer.

Abstract: In a method for manufacturing a semiconductor device in which wiring layers are formed by a damascene method, certain embodiment relate to a manufacturing methods and semiconductor devices, in which a bonding pad section having a multiple-layered structure can be formed by a simple method without increasing the number of process steps.

Abstract: The present invention is a semiconductor metallization process for providing complete via fill on a substrate and a planar metal surface, wherein the vias are free of voids and the metal surface is free of grooves. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A PVD metal layer, such as PVD Al or PVD Cu, is then deposited onto the refractory layer at a pressure below about 1 milliTorr to provide a conformal PVD metal layer. Then the vias or contacts are filled with metal, such as by reflowing additional metal deposited by physical vapor deposition on the conformal PVD metal layer. The process is preferably carried out in an integrated processing system that includes a long throw PVD chamber, wherein a target and a substrate are separated by a long throw distance of at least 100 mm, and a hot metal PVD chamber that also serves as a reflow chamber.

Abstract: An improved semiconductor device structure comprises insertion of a semiconductor wafer into a high-pressure heated chamber and the deposition of a low-melting point aluminum material into a contact hole or via and over an insulating layer overlying a substrate of the wafer. The wafer is heated up to the melting point of the aluminum material and the chamber is pressurized to force the aluminum material into the contact holes or vias and eliminate voids present therein. A second layer of material, comprising a different metal or alloy, which is used as a dopant source, is deposited over an outer surface of the deposited aluminum material layer and allowed to diffuse into the aluminum material layer in order to form a homogenous aluminum alloy within the contact hole or via. A semiconductor device structure made according to the method is also disclosed.

Abstract: An improved semiconductor device structure comprises insertion of a semiconductor wafer into a high-pressure heated chamber and the deposition of a low-melting-point aluminum material into a contact hole or via and over an insulating layer overlying a substrate of the wafer. The wafer is heated up to the melting point of the aluminum material and the chamber is pressurized to force the aluminum material into the contact holes or vias and eliminate voids present therein. A second layer of material, comprising a different metal or alloy, which is used as a dopant source, is deposited over an outer surface of the deposited aluminum material layer and allowed to diffuse into the aluminum material layer in order to form a homogenous aluminum alloy within the contact hole or via. A semiconductor device structure made according to the method is also disclosed.

Abstract: An improved method for making an integrated circuit. That method includes forming a first dielectric layer on a substrate, etching a trench into that layer, then filling the trench with a conductive material. The conductive material is then electropolished to form a recessed conductive layer within the first dielectric layer.

Abstract: Chemical mechanical polishing (CMP) is known to cause dishing when the surface being planarized includes a wide trench partially filled with metal. This problem has been overcome by first filling the trench with a material whose polishing rate under CMP is similar to that of the metal in the trench. Spin-coating is used for this so that only the trench gets filled. After CMP, any residue of this material is removed, leaving behind a surface that has been planarized to the intended extent without the introduction of significant dishing and with minimum erosion of the metal.

Abstract: A method for manufacturing an interconnect structure of a semiconductor device includes forming a bottom interconnect layer underlying a dielectric layer and overlying a silicon substrate; forming a through-hole in the dielectric layer to expose the bottom interconnect later; depositing a first barrier metal layer overlying the dielectric layer and on an inner wall of the through-hole; depositing a metal layer on the first barrier metal layer for filling the through-hole; etching the metal layer and the first barrier metal layer until the dielectric film is exposed to thereby form a via plug of the metal layer and the barrier metal layer; depositing a second barrier metal layer on the dielectric film and the via plug; and depositing an interconnect layer of which a main component is aluminum on the second barrier metal layer.

Abstract: A method of forming a dual damascene structure comprises the steps of providing a substrate having a first conductive layer formed thereon, and then sequentially forming a first dielectric layer, an anti-reflection layer and a second dielectric layer over the substrate. Next, the first dielectric layer, the anti-reflection layer and the second dielectric layer are patterned to form a first opening that exposes the conductive layer. Thereafter, the second dielectric layer is patterned to form a trench (or second opening) in a position above the first conductive layer. The trench and the first opening together form an opening of the dual damascene structure. Finally, a second conductive material is deposited into the opening and the trench to form conductive lines and the dual damascene structures.

Abstract: In a related interconnection structure that is formed by filling a metal, there have been problems, since defective connection occurs due to generation of voids and other features caused by poor filling of the metal, which entails reduction in reliability, and contact resistance is large due to a barrier metal layer at a contact portion. A novel interconnection structure is provided which comprises: a recess (for example, a contact hole, a trench, or a trench and a contact hole formed at a bottom of the trench), which is connected onto a conductive material mass formed in an insulating film, and which is formed in the insulating film; a barrier metal layer formed on side walls of the recess; and metal material masses filled in the interior of the recess, wherein the metal material masses are formed with a metal repeatedly filled into the recess over a plurality of times, and a metal material mass and a conductive material mass are directly connected to each other.

Abstract: Improved processes for fabricating wire bond pads on pure copper damascene are disclosed by this invention. The invention relates to various methods of fabrication used for semiconductor integrated circuit devices, and more specifically to the formation of Al—Cu alloy top pad metal layers are described, which improve adhesion among the wire bond, top Al—Cu and the underlying copper pad metallurgy. This invention describes processes wherein a special Al—Cu bond layer or region is placed on top of the underlying copper pad metal. This Al—Cu bond pad on pure copper (with barrier layer in-between) provides for improved wire bond adhesion to the bond pad and prevents peeling during wire bond adhesion tests.

Abstract: A process for preventing the formation of a copper precipitate in a copper-containing metallization on a die, wherein the process includes the steps of: identifying each manufacturing step after metallization which exposes the die to a temperature of greater than 100° C.; and after performing such post-metallization step, cooling the die down to a temperature of at least 100° C. at a cooling rate in a range of 0.6° C. per second to 1.0° C. per second, and more specifically in a range of 0.59° C. per second to 1.00° C. per second. The step of cooling the die can be achieved by utilizing any of numerous means including an air conditioning system with a thermocouple for monitoring the cooling rate, a substantially closed manufacturing environment housing having a ventilation port with an electrically operable fan system mounted proximate the ventilation port, a cooling rack having artificial ventilation, and/or a chiller plate.

Abstract: A method of metallization for a semiconductor channel, trench, or via with a high aspect ratio lined with a barrier metal layer. The channel, trench, or via is situated in a semiconductor substrate and the barrier metal layer has deposited thereon two metal layers, the first of which has a lower melting point by at least 10° C. than that of the second. A low temperature, high pressure process is used to alloy together the two uppermost metal layers and bond them to a barrier metal, and thereby substantially fill up the channel, trench, or via without leaving a void therein and without breaching the barrier layer in a pitting phenomenon.

Abstract: The present invention provides methods of producing an anti-reflective layer on a semiconductor wafer/device and wafers/devices including that anti-reflective layer. The anti-reflective layer is produced by annealing layers of titanium and aluminum on a wafer/device to provide a roughened surface that significantly reduces reflectivity to improve the accuracy and definition provided by optical lithography processes.

Abstract: A semiconductor device includes first and second conductive layers which are electrically connected to each other through a contact plug. A first insulating film is formed on the first conductive layer and has a first opening which reaches the surface of the first conductive layer. A second insulating film is formed on the first insulating film and has a second opening at the same position as the first opening. The contact plug is filled in the first and second openings and has the surface which is substantially flush with the surface of the second insulating film and also contains a metal having a high melting point. The second conductive layer is formed on the second insulating film and on the contact plug.

Abstract: In the first option of the present invention, a semiconductor structure is provided and an overlying titanium nitride barrier layer is deposited thereon at about 100° C. At least Al and Cu is sputtered over the titanium nitride barrier layer from about 270 to 300° C. to form an Al—Cu alloy containing metal layer. The sputtered Al—Cu alloy containing metal layer is promptly cooled at a cooling rate greater than about 100° C./minute to a temperature below 200° C. to form a Al—Cu alloy containing metal layer having minimal CuAl2 grain growth. The semiconductor structure is removed from the cooling chamber and the semiconductor structure is processed further below 200° C. to form semiconductor device precursors. In the second option of the present invention, a semiconductor structure having an overlying barrier layer is provided.

Abstract: A method for forming a damascene interconnection. After forming an insulating layer on a semiconductor substrate, the insulating layer is patterned and etched to form an opening. A barrier layer is formed on an entire surface of a resulting structure where the opening is formed. A seed layer is formed on at least on a sidewall of the opening on which the barrier layer is formed, and on a top surface of the insulating layer, using an ionized physical vapor deposition (PVD) apparatus having a target to which a power for making plasma is applied, and a chuck to which a radio frequency (RF) bias for accelerating ions is applied. When the seed layer is formed using an ionized PVD process, the power and bias are controlled to resputter an initial seed layer formed on a bottom of the opening. The resputtered seed layer is redeposited on the sidewall of the opening, forming a seed layer with a good step coverage characteristic on the sidewall.