Abstract: The present invention is an electrical interconnection on a substrate and a method for forming an electrical interconnection on a substrate. The electrical interconnection in the present invention comprises a first metal layer, a first diffusion barrier layer on the first metal layer, a second metal layer on the first diffusion barrier layer, an organometallic layer on the second metal layer, and an electrical interconnect layer on the organometallic layer. The first diffusion barrier layer prevents diffusion of the first metal layer and the second metal layer therethrough. The organometallic layer is preferably formed by contacting the second metal layer with an organic material to form a organometallic layer. The organometallic layer chemically and physically protects the second metal layer, particularly by preventing the oxidation thereof.

Abstract: Metallization process sequences are provided for forming reliable interconnects including lines, vias and contacts. An initial barrier layer, such as Ta or TaN, is first formed on a patterned substrate followed by seed layer formed using high density plasma PVD techniques. The structure is then filled using either 1) electroplating, 2) PVD reflow, 3) CVD followed by PVD reflow, or 4) CVD.

Abstract: A first wiring layer is formed on an insulating film. The first wiring layer is formed by sequentially laminating a barrier layer, an Al alloy layer, and an antireflection layer. The antireflection layer is formed by sequentially laminating a Ti layer, a TiN layer, and a TiON layer. After an interlayer insulating film is formed on the first wiring layer, a contact hole is formed through the interlayer insulating film and a tight adhesion layer is formed on an inner surface of the contact hole. The tight adhesion layer is formed by sequentially laminating a Ti layer, a TiN layer, a TiON layer, and a TiN layer. A W plug is embedded in the contact hole through CVD using WF6. Thereafter, an Al alloy layer and an antireflection layer are sequentially deposited and patterned to form a second wiring layer.

Abstract: A method of preventing or at least reducing the likelihood of bridging between adjacent micro-scale polycrystalline structures, and particularly to reducing electrical shorting between adjacent metallization lines of a microcircuit. The method generally entails forming a multilayer structure that comprises a polycrystalline layer and at least one constraining layer, and then patterning the multilayer structure to yield a first line and a second line that is narrower in width than the first line. The first line has a patterned edge that is spaced apart from a patterned edge of the second line, so that the first and second lines are electrically insulated from each other. One or more features associated with the first line are then formed that prevent bridging between the first and second lines if excessive lateral grain growth subsequently occurs along the patterned edge of the first line.

Abstract: A semiconductor device includes first and second conductive layers which are electrically connected to each other through a contact plug. A first insulating film is formed on the first conductive layer and has a first opening which reaches the surface of the first conductive layer. A second insulating film is formed on the first insulating film and has a second opening at the same position as the first opening. The contact plug is filled in the first and second openings and has the surface which is substantially flush with the surface of the second insulating film and also contains a metal having a high melting point. The second conductive layer is formed on the second insulating film and on the contact plug.

Abstract: A process used during the formation of a semiconductor device comprises the steps of placing a plurality of semiconductor wafers each having a surface into a chamber of a batch wafer processor such as a diffusion furnace. The wafers are heated to a temperature of between about 300° C. and about 550° C. With the wafers in the chamber, at least one of ammonia and hydrazine is introduced into the chamber, then a precursor comprising trimethylethylenediamine tris(dimethylamino)titanium and/or triethylaluminum is introduced into the chamber. In the chamber, a layer comprising aluminum nitride is simultaneously formed over the surface of each wafer. The inventive process allows for the formation of aluminum nitride or titanium aluminum nitride over the surface of a plurality of wafers simultaneously. A subsequent anneal of the aluminum nitride layer or the titanium aluminum nitride layer can be performed in situ.

Abstract: A method of isolating an exposed conductive surface. An aluminum layer (130) is selectively formed over the exposed conductive (106) surface (e.g., Cu) but not over the surrounding dielectric (110) surface using a thermal CVD process. The aluminum layer (130) is then oxidized to form a thin isolating aluminum-oxide (108) over only the conductive surface. The isolating aluminum-oxide provides a barrier for the Cu while taking up minimal space and reducing the effective dielectric constant.

Abstract: There is provided a semiconductor device having a wiring structure which reduces possibility of a short circuit, and method of making the device. Besides, there is provided a semiconductor device having high reliability. Further, there is provided a semiconductor device having high yield. A wiring line is formed at one main surface side of a semiconductor substrate, and has a laminate structure of an adjacent conductor layer and a main wiring layer. The main wiring layer contains an added element to prevent migration. The adjacent conductor layer is formed of a material for preventing a main constituent element and the added element of the main wiring layer from diffusing into the substrate beneath the adjacent conductor layer, and the concentration of the added element at a location close to an interface between the adjacent conductor layer and the main wiring layer is low compared to the concentration of the added element in the main wiring layer spaced from the adjacent conductor layer.

Abstract: In the fabrication of integrated circuits containing multilevel structures of FSG (F-doped SiO2) dielectric layers and aluminum-copper-TiN layers, superior adhesion between the FSG and aluminum-copper-TiN is achieved by subjecting the aluminum-copper-TiN layer to a plasma containing N2 and H2 or N2 and NH3 prior to deposition of the FSG layer. It is believed that the plasma treatment converts unreacted Ti within the TiN layer to TiN and, also, stuffs grain boundaries within the TiN layer with N2. The result is a void-free TiN layer which is impervious to F atoms residing in the FSG layer.

Abstract: The present invention is a film forming method of forming a film of a treatment solution on the front face of a substrate in a treatment chamber including the steps of: supplying the treatment solution to the substrate mounted on a holding member in the treatment chamber in states of gas being supplied into the treatment chamber and of an atmosphere in the treatment chamber being exhausted; and measuring the temperature of the front face of the substrate before the supply of the treatment solution. The measurement of the temperature of the front face of the substrate before the supply of the treatment solution enables the check of the temperature of the front face of the substrate and the temperature distribution. Then, the measured result is compared with a previously obtained ideal temperature distribution for the formation of a film with a uniform thickness, thereby predicting the film thickness of the film which will be formed in the following processing.

Abstract: Grooves and holes of high aspect ratio are filled completely and uniformly. After forming connection holes (3) and wiring grooves (4) in a silicon oxide film (2) which is formed on a silicon substrate (1), a TiN film (5) is formed over the entire surface of the semiconductor substrate and a Ti film (6) is formed on the region except for the connection holes (3) and the wiring grooves (4). Then, in a state where the connection holes (3) and the wiring groove (4) are dipped in a plating solution, a plating treatment is carried out under a deposition overvoltage higher than the deposition overvoltage of TiN to copper and lower than the deposition overvoltage of Ti to copper.

Abstract: In one aspect, the invention includes a processing method, comprising: a) providing a substrate having a high aspect ratio opening therein; b) forming a metal-comprising layer over the opening; c) providing a first pressure against the metal-comprising layer; and d) ramping the pressure that is against the metal-comprising layer to a second pressure at a rate of from about 1 atmosphere per second about 100 atmospheres per second.

Abstract: A method for making a semiconductor device is described. That method includes forming a dielectric layer on a substrate, then etching a trench into the dielectric layer. After filling the trench with copper, a portion of the copper is removed to form a recessed copper plug within the dielectric layer. A capping layer that comprises aluminum is then formed on the recessed copper plug.

Abstract: This invention provides a conductive aluminum film and method of forming the same, wherein a non-conductive impurity is incorporated into the aluminum film. In one embodiment, the introduction of nitrogen creates an aluminum nitride subphase which pins down hillocks in the aluminum film to maintain a substantially smooth surface. The film remains substantially hillock-free even after subsequent thermal processing. The aluminum nitride subphase causes only a nominal increase in resistivity (resistivities remain below about 12 &mgr;&OHgr;-cm), thereby making the film suitable as an electrically conductive layer for integrated circuit or display devices.

Abstract: The present invention is a contact/via comprising and its method of fabrication. The contact/via of the present invention includes a conductive film. An opening having a top and bottom is formed on the conductive film. The opening has a first sidewall and a second sidewall wherein the first sidewall is opposite the second sidewall. The first sidewall has a stair step configuration such that the first sidewall is closer to the second sidewall at the bottom of the opening than at the top of the opening. A conductive film is then formed on the first sidewall in the opening and on the bottom of the opening on the conductive film.

Abstract: A disclosed embodiment comprises patterning a conductor in a dielectric in a semiconductor die. The dielectric can be, for example, silicon oxide or a low-k dielectric while the conductor can comprise aluminum, copper, or a copper-aluminum alloy. Thereafter, a blanket of high permeability layer is deposited over the dielectric. The high permeability layer can comprise high permeability materials such as nickel, iron, nickel-iron alloy, or a magnetic oxide. The blanket deposition of the high permeability layer can be accomplished by, for example, a sputtering technique. After depositing the high permeability layer, a portion of the atoms or molecules in the high permeability layer is driven into the underlying dielectric to increase the permeability of the dielectric. As an example, an ion implanter using heavy ions such as silicon ions or germanium ions can be used to drive some of the atoms or molecules in the high permeability layer into the underlying dielectric.

Abstract: A chemical vapor deposition process for the in-situ preparation of conformal copper-doped aluminum coatings on a substrate comprises the steps of generating a first flow of a first reactant vapor directed to the substrate in the reactor, the first reactant vapor including a copper source precursor; heating the substrate to a temperature sufficient to decompose the first reactant vapor and form an ultrathin copper seed layer; generating a second flow of a second reactant vapor directed to the substrate in the reactor, the second reactant vapor including an aluminum source precursor; and heating the substrate to a temperature higher than 185° C. to decompose the second reactant vapor and form a copper-doped aluminum film.

Abstract: A terminal interconnection 45a including an aluminum alloy film 4a and a nitrogen-containing aluminum film 5a layered together is formed on a glass substrate 2. Nitrogen-containing aluminum film 5a in a contact portion 12a within a contact hole 11a exposing the surface of terminal interconnection 45a has a predetermined thickness d1 determined based on a specific resistance of the nitrogen-containing aluminum film. The thickness of the nitrogen-containing aluminum film outside the contact portion is larger than that of the nitrogen-containing aluminum film within the contact portion. Thereby, a semiconductor device or a liquid crystal display device having a reduced contact resistance and an appropriate resistance against chemical liquid is achieved.

Abstract: A method for manufacturing an integrated circuit improves the reliability of thermosonic bonds formed to attach a gold bond wire to an aluminum interconnect pad by reducing corrosion of the aluminum pad regions. In the method, a gold or silver plating is applied to the aluminum bond pads to prevent corrosion of the aluminum pad surface. Prior to applying the plating, corrosive contaminants are removed from the aluminum pad regions using an argon sputter etch. Annealing is used to remove damage from the argon sputtering, and further serves to alloy the resultant aluminum to gold or aluminum to silver interface. The aluminum pad layer is made very thin, or less than approximately 8000 Å to limit Kirkendall voiding when gold wires are bonded to the pad using a thermosonic bonding process.

Abstract: A method of manufacturing a semiconductor device is capable of preventing a local delamination at the interface between an aluminum film and an anti-reflective layer formed thereon. After aluminum is deposited on a substrate, the aluminum film is slowly cooled. Then, the substrate is left as is for more than 3 minutes before a venting process takes place in which thermal energy is generated. Then, an anti-reflective layer is formed on the aluminum film. Thermal stress in the aluminum film is relieved by the slow cooling of the aluminum film and the delay before the venting process. Accordingly, when a thermal process is carried out after the anti-reflective layer is formed on the aluminum film, little shear stress is generated at the interface between the aluminum film and the anti-reflective layer.

Abstract: Peeling between a bonding pad and an insulating film which underlies the bonding pad is to be prevented. A laminate film constituted mainly by W which is higher in mechanical strength than a wiring layer using an Al alloy film as a main conductive layer and than a bonding pad, is formed within an aperture formed in silicon oxide films and is interposed between the wiring line and the bonding pad.

Abstract: A recess having a height-to-width aspect ratio from about 6:1 to about 10:1 in a semiconductor structure is taught with a method of forming the same. In a first embodiment, a refractory metal layer is formed in the recess, which can be a trench, a contact hole, or a combination thereof. A refractory metal nitride layer is then formed on the refractory metal layer. A heat treatment is used to form a metal silicide contact at the bottom of the contact hole upon a semiconductor material. In a first alternative method, an ammonia high-temperature treatment is conducted to remove undesirable impurities within the refractory metal nitride layer lining the contact hole and to replace the impurities with more nitrogen. In a second alternative method, a second refractory metal nitride layer is formed by PVD upon the first refractory metal nitride layer. In either alternative, a metallization layer is deposited within the recess.

Abstract: Embodiments include a manufacturing method for a semiconductor device which can suppress a concave from being generated in an upper area of a wiring layer at a position above plug. The method may include the steps of (a) forming an impurity diffusion layer 34; (b) forming, on the impurity diffusion layer 34, an interlayer insulating layer 40 having at least one. through hole 42; (c) forming a plug 50 in the through hole 42; (d) forming an underlying layer 62 on the plug 50 and the interlayer insulating layer 40, and (e) forming an aluminum layer 64 on the underlying layer 62, the aluminum layer 64 being formed at a substrate temperature not lower than 250° C. and under a reduced pressure.

Abstract: An aluminum hardmask (106, 214) is used for etching a dielectric layer (102, 210). A fluorine-based etch is used that does not etch the aluminum hardmask (106, 210) The aluminum hardmask (106, 214) is then removed by CMP.

Abstract: Disclosed is a semiconductor device which comprises a semiconductor element having a plurality of electrodes, a plurality of external electrodes disposed around the periphery of the semiconductor element, a fine wire electrically connected between at least one of surfaces of each of the plural external electrodes and at least one of the plural electrodes of the semiconductor element, and an encapsulating resin which encapsulates the semiconductor element, the plural external electrodes, and the fine wires and whose external shape is a rectangular parallelepiped, wherein a bottom surface of the semiconductor element and a bottom surface of each of the plural external electrode are exposed from a bottom surface of the encapsulating resin and a top surface of the semiconductor element and a top surface of each of the plural external electrode are located substantially coplanar with each other.

Abstract: An insulating film for embedding conductive portions therein is formed so as to represent convex configurations corresponding to each top of convex conductive portions. The insulating film is covered with an etching stopper film having an etching rate which is smaller than that of the insulating film. Convex portions of the etching stopper film corresponding to each top of the conductive portions are removed partially, thereby forming a contact hole that reaches each top of the conductive portions through the removal portions of the silicon nitride film by an etching treatment. A plug conductive portion connected to each top of the conductive portions is formed in the contact hole.

Abstract: First, a lower layer wiring is formed on a semiconductor substrate. Then, an interlayer insulating film is formed on the lower layer wiring. Next, a first Ti film is formed on the interlayer insulating film. Thereafter, a TiN film is formed on the first Ti film. Then, a via hole is formed in the TiN film, the first Ti film and the interlayer insulating film such as to reach the lower layer wiring. Then, a second Ti film and an Al or Al alloy film are sequentially formed in the via hole and on the TiN film. Next, a thermal treatment is carried out, thereby allowing Ti in the second Ti film and Al in the Al or Al alloy film to react with each other in a bottom of the via hole.

Abstract: A metal wiring suitable for a substrate of large size is provided. The present invention is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle &agr; in accordance with the bias power density, the ICP power density, the temperature of lower electrode, the pressure, the total flow rate of etching gas, or the ratio of oxygen or chlorine in etching gas. The thus formed metal wiring has less fluctuation in width or length and can satisfactorily deal with an increase in size of substrate.

Abstract: There are included a semiconductor substrate provided with a desirable element region, an electrode pad formed to come in contact with a surface of the semiconductor substrate or a wiring layer provided on the surface of the semiconductor substrate, a bump formed on a surface of the electrode pad through an intermediate layer, and a resin insulating film formed in at least a peripheral portion of the bump to cover an interface of the bump and the intermediate layer which is exposed to a side surface of the bump.

Abstract: A gate-insulating layer, intrinsic amorphous-silicon semiconductor layer, and ohmic contact layer are continuously formed so as to cover a gate electrode on a substrate to remove a natural oxide film from the surface of the ohmic contact layer by performing radio-frequency sputter etching before forming source and drain electrodes. After the natural oxide film is removed, a metallic layer mainly containing Al is formed on the gate-insulating layer and ohmic contact layer.

Abstract: A method of manufacturing a semiconductor device is capable of preventing a local delamination at the interface between an aluminum film and an anti-reflective layer formed thereon. After aluminum is deposited on a substrate, the aluminum film is slowly cooled. Then, the substrate is left as is for more than 3 minutes before a venting process takes place in which thermal energy is generated. Then, an anti-reflective layer is formed on the aluminum film. Thermal stress in the aluminum film is relieved by the slow cooling of the aluminum film and the delay before the venting process. Accordingly, when a thermal process is carried out after the anti-reflective layer is formed on the aluminum film, little shear stress is generated at the interface between the aluminum film and the anti-reflective layer.

Abstract: This invention produces a film which is resistant to hillocking without compromising the electrical conductivity of the interconnects, the circuit architecture or any other function affecting the operation of the integrated circuit. The invention works on the principle that hillocking is caused by the squeezing or extrusion of certain grains (crystals) in the film due to a compressive residual stress state that arises from annealing (heating) treatments applied to the film following the deposition of the film. These grains are in a “weak” crystallographic orientation relative to the great majority of the grains. The coordinated orientation of this great majority of grains is known as the texture and aluminum films are deposited with a strong (111) texture, where (111) refers to specific crystallographic planes and <111>. Refers to the direction normal to the (111) plane.

Abstract: An aluminum layer formed over an integrated circuit structure is patterned to form a plurality of aluminum metal lines. The patterned aluminum metal lines are then anodized in an acid anodizing bath to form anodized aluminum oxide on the exposed sidewall surfaces of the patterned aluminum. The anodization may be carried out until the anodized aluminum films on horizontally adjacent aluminum metal lines contact one another, or may be stopped prior to this point, leaving a gap between the anodized aluminum oxide films on adjacent aluminum metal lines. This gap may then be either filled with other low k dielectric material or by standard (non-low k) dielectric material. A capping layer of non-porous dielectric material is then formed over the porous anodized aluminum oxide.

Abstract: In order to form an aluminum system wiring that does not peel off on an insulating film containing fluorine and to improve the reliability thereof, a semiconductor device according to the present invention includes an insulating film (14) containing fluorine formed on a substrate (11), a titanium aluminum alloy film (17a) formed on the insulating film (14) containing fluorine, and a metallic film (17b) comprising aluminum or an aluminum alloy formed on the titanium aluminum alloy film (17a).

Abstract: Disclosed is a method of post treatment for a metal line of semiconductor device, wherein an aluminum oxide layer is employed as a protecting layer of metal line, thereby improving reliability thereof. The disclosed comprises the steps of: forming aluminum having a predetermined thickness on the entire surface of substrate having the metal line by performing a deposition process; performing a plasma treatment on a predetermined processing condition, thereby changing the aluminum into a lower barrier layer of aluminum oxide layer; and forming an inter metal dielectric layer on the entire surface of the lower barrier layer by performing a deposition process.

Abstract: An integrated circuit designed to control grain growth induced roughening in a conductive stack is disclosed herein. The conductive stack includes an interconnect metallization layer formed at a low diffusivity temperature of less than 200° C. The interconnect metallization layer includes aluminum doped with copper. The conductive stack further includes subsequent depositions and/or processing involving interconnect metallization layer to be carried out at the low diffusivity temperatures.

Abstract: To form a wiring electrode having excellent contact function, in covering a contact hole formed in an insulting film, a film of a wiring material comprising aluminum or including aluminum as a major component is firstly formed and on top of the film, a film having an element belonging to 12 through 15 groups as a major component is formed and by carrying out a heating treatment at 400° C. for 0.5 through 2 hr in an atmosphere including hydrogen, the wiring material is provided with fluidity and firm contact is realized.

Abstract: In a method for manufacturing a semiconductor device in which wiring layers are formed by a damascene method, certain embodiments relate to a manufacturing method and a semiconductor device, in which a bonding pad section having a multiple-layered structure can be formed by a simple method without increasing the number of process steps. One embodiment includes a method for manufacturing a semiconductor device in which at least an uppermost wiring layer is formed by a damascene method.

Abstract: The invention is a method of depositing an aluminum nitride comprising layer over a semiconductor substrate, a method of forming DRAM circuitry, DRAM circuitry, a method of forming a field emission device, and a field emission device. In one aspect, a method of depositing an aluminum nitride comprising layer over a semiconductor substrate includes positioning a semiconductor substrate within a chemical vapor deposition reactor. Ammonia and at least one of triethylaluminum and trimethylaluminum are fed to the reactor while the substrate is at a temperature of about 500° C. or less and at a reactor pressure from about 100 mTorr to about 725 Torr effective to deposit a layer comprising aluminum nitride over the substrate at such temperature and reactor pressure. In one aspect, such layer is utilized as a cell dielectric layer in DRAM circuitry. In one aspect, such layer is deposited over emitters of a field emission display.

Abstract: A method for making 0.25-micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the contraction being absorbed by the aluminum. Because the alloy is reacted prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation. in the interconnect lines is reduced. The likelihood of undesirable void formation is still further reduced during the subsequent ILD gapfill deposition process by using relatively low bias power to reduce vapor deposition temperature. and by using relatively low source gas deposition flow rates to reduce flow-induced compressive stress on the interconnect lines during ILD formation.

Abstract: Various methods of inspecting a workpiece for residue are provided. In one aspect, a method of fabricating a conductor layer on a substrate is provided that includes forming an aluminum-copper film on the substrate in a first processing chamber and forming an anti-reflective coating on the aluminum-copper film in a second processing chamber. The substrate is moved from the second processing chamber into a cooling chamber to quench the substrate. A first time interval during which the substrate is in the first processing chamber and second time interval during which the substrate is present in the second processing chamber are measured. The substrate is annealed to restore a uniform equilibrium distribution of copper in the aluminum if the first time interval exceeds about 600 seconds or the second time interval exceeds about 300 seconds. The method substantially reduces the risk of metal comb bridging device failures following etch definition of conductor lines.

Abstract: A titanium nitride film is selectively etched relative to a tungsten film by using as an etchant a solution containing hydrochloric acid and a hydrogen peroxide solution, the molar ratio of the hydrogen peroxide in the hydrogen peroxide solution to hydrogen chloride in the hydrochloric acid being 1/100 or less.

Abstract: A recess having a height-to-width aspect ratio from about 6:1 to about 10:1 in a semiconductor structure is taught with a method of forming the same. In a first embodiment, a refractory metal layer is formed in the recess, which can be a trench, a contact hole, or a combination thereof. A refractory metal nitride layer is then formed on the refractory metal layer. A heat treatment, preferably RTP, is used to form a metal silicide contact at the bottom of the contact hole upon semiconductor material. In a first alternative method, an ammonia high-temperature treatment is conducted to remove undesirable impurities within the refractory metal nitride layer lining the contact hole and to replace the impurities with more nitrogen. In a second alternative method, a second refractory metal nitride layer is formed by PVD upon the first refractory metal nitride layer. In either alternative, metallization layer is deposited with the recess.

Abstract: In a semiconductor device, each electrode pad portion is structured by a metal portion, such as a W film, buried in a recess of an oxide film and vertically extended and a pad film, such as an Al alloy film, partially contacted with the metal portion. An underlying film, such as a TiN film, underlies the pad film and the metal portion and is deposited on a conductive film, such as a Ti film, which is contacted with the oxide film and the recess of the oxide film. With this structure, peeling off can be avoided in the pad film, the underlying film, and the conductive film when a wiring line is bonded to the pad film.

Abstract: A method of forming interconnect structures in a semiconductor device, comprising the following steps. A semiconductor structure is provided. In the first embodiment, at least one metal line is formed over the semiconductor structure. A silicon-rich carbide barrier layer is formed over the metal line and semiconductor structure. Finally, a dielectric layer, that may be fluorinated, is formed over the silicon-rich carbide layer. In the second embodiment, at least one fluorinated dielectric layer, that may be fluorinated, is formed over the semiconductor structure. The dielectric layer is patterned to form an opening therein. A silicon-rich carbide barrier layer is formed within the opening. A metallization layer is deposited over the structure, filling the silicon-rich carbide barrier layer lined opening. Finally, the metallization layer may be planarized to form a planarized metal structure within the silicon-rich carbide barrier layer lined opening.

Abstract: A dielectric interlayer is formed over a semiconductor substrate comprising at least one active region. The exposed upper surface of the dielectric interlayer is treated with nitrogen to form a nitrided barrier layer thereon. At least one hydrogen-containing dielectric layer is formed over the dielectric interlayer having the nitrided barrier layer thereon. The nitrided barrier layer serves as a barrier to diffusion of hydrogen from the at least one hydrogen-containing dielectric layer into the dielectric interlayer, thereby preventing a decrease in hot carrier injection reliability.

Abstract: In a semiconductor device including a first conductive layer, the first conductive layer is treated with a nitrogen/hydrogen plasma before an additional layer is deposited thereover. The treatment stuffs the surface with nitrogen, thereby preventing oxygen from being adsorbed onto the surface of the first conductive layer. In one embodiment, a second conductive layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates an oxide formed between the two layers as a result of subsequent thermal treatments. In another embodiment, a dielectric layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates the ability of the first conductive layer to incorporate oxygen from the dielectric.

Abstract: The specification describes techniques for wire bonding gold wires to copper metallization in semiconductor integrated circuits. A barrier layer is formed on the copper, and an aluminum bonding pad is formed on the barrier layer. Gold wire is then thermocompression bonded to the aluminum pad.

Abstract: This invention relates to a method of fabricating metal wiring, whereby sputtered metal is rapidly cooled down by a post-metal quenching process, to prevent deleterious CuAl2 precipitation. The main embodiments are the formation of a TiN reactively sputtered bottom barrier layer, followed by a sputtered Al—Cu alloy wiring layer immediately followed by an in situ post-metal quench (key step), then followed by a reactively sputtered second TiN top barrier layer. The “in situ” post-metal quench is especially effective by employing wafer backside cooling using low temperature helium gas or argon gas, cooling the substrate from a high temperature range of 450 to 150 °C., to a low temperature range near room temperature, in a short time interval of between 30 to 180 seconds. The CuAl2 precipitates if allowed to form, block the etch removal of the underlying TiN layer causing electrical shorts between closely spaced lines.

Abstract: The object of the invention is to solve failure in embedding conductive material by electroplating caused because organic insulating material is deformed by the compressive stress of a barrier metal layer such as tantalum nitride used for grooved interconnection, a groove-used for grooved interconnection is deformed and a seed layer is not fully formed in the groove and to enhance reliability upon interconnection. To achieve the object, a semiconductor device according to the invention is based upon a semiconductor device having a groove formed through a second insulating film over a substrate, a barrier metal layer formed at least on the inner wall of the groove and grooved interconnection embedded inside the groove via the barrier metal layer and is characterized in that a concave portion is continuously or intermittently formed along a groove through a second insulating film within a predetermined interval from grooved interconnection.