Aluminum Or Aluminum Alloy Conductor Patents (Class 438/688)
  • Publication number: 20040253807
    Abstract: An improved barrier layer stack and method for forming the same for preserving an aluminum alloy interconnect resistivity, the method comprising providing a semiconductor process wafer comprising an exposed conductive region; forming a first barrier layer comprising a barrier layer stack over the exposed conductive region comprising one of a TiN or Ti layer in contact with the conductive region; forming at least one additional barrier layer comprising the barrier layer stack to form an alternating sequence of TiN and Ti layers; forming an uppermost barrier layer of TiN comprising the barrier layer stack; forming an overlying aluminum alloy region in contact with the uppermost barrier layer; and, subjecting the semiconductor process wafer to at least one process comprising a temperature of greater than temperatures greater than about 350 ° C.
    Type: Application
    Filed: June 13, 2003
    Publication date: December 16, 2004
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kong-Beng Thei, Chung-Lung Cheng, His-Chien Lin, Li-Don Chen, Tung-Lung Lai, Chi-Lung Lin
  • Publication number: 20040253817
    Abstract: A liquid application material that is capable of forming an oxidized insulator as a result of baking is applied onto a support substrate to produce an object of processing. Then, a mold having projection structures with intervals of nanometers is pressed against the applied liquid material to produce corresponding recess structures. Thereafter, the applied liquid material is baked in oxygen-containing gas or oxidized in ozone or oxygen plasma to make it electrically highly resistive. Subsequently, a layer to be anodized is formed on said oxidized insulator. Then, the layer to be anodized is actually anodized in an acidic solution to form fine holes that are aligned with the respective recess structures in the anodized layer. Accordingly, fine recess structures can be manufactured with ease.
    Type: Application
    Filed: June 9, 2004
    Publication date: December 16, 2004
    Inventors: Aya Imada, Tohru Den
  • Patent number: 6831010
    Abstract: This invention relates to a method of depositing a layer on an exposed surface of an insulating layer of material. The method includes treating the exposed surface with hydrogen or a gaseous source of hydrogen in the presence of a plasma, prior to or during deposition of a metallic layer.
    Type: Grant
    Filed: April 12, 2000
    Date of Patent: December 14, 2004
    Assignee: Trikon Technologies Limited
    Inventors: Knut Beekman, Paul Rich, Claire Louise Wiggins
  • Patent number: 6828233
    Abstract: A high integrity, reliable liner is disclosed for a via in which a titanium aluminide layer is preformed as a lining within a via hole prior to deposition of other conductive materials within the via hole. The conductive materials deposited on the preformed titanium aluminide can be either a secondary barrier layer portion of the liner, such as a titanium compound layer, which in turn has a metal plug deposited thereon, or, alternatively, a metal plug directly deposited on the titanium aluminide layer. An important advantage achieved by the present invention is that a via is formed with a substantial elimination of void formation. The enhanced vias are useful in a wide variety of semiconductor devices, including SRAMS and DRAMs.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: December 7, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Shane P. Leiphart
  • Patent number: 6821875
    Abstract: In a method for forming a contact on semiconductor surface, a crystalline silicon surface is first oxidized, following which an aluminium layer is deposited onto the oxide layer. A layer of amorphous silicon is then deposited onto the aluminium layer. The structure is then heated to a temperature below the aluminium/silicon eutectic temperature to locally reduce the oxide layer in regions where the quality/density of the oxide layer is lower. Simultaneously, the amorphous silicon penetrates into the aluminium layer, in which it has a high mobility. With continued heating, the aluminium penetrates completely through the oxide layer in localized regions, exposing the crystalline silicon surface. The exposed silicon surface provides a sight for nucleating epitaxial growth, which occurs rapidly as silicon within the aluminium continuously feeds the solid phase epitaxial growth process.
    Type: Grant
    Filed: November 5, 2002
    Date of Patent: November 23, 2004
    Assignee: Unisearch Limited
    Inventors: Stuart Ross Wenham, Linda Mary Koschier
  • Publication number: 20040229458
    Abstract: A thick metal layer is formed on a semiconductor integrated circuit in multiple different deposition chambers. A first portion of the metal layer is formed in a first deposition chamber, the first thickness being approximately half the target thickness. The substrate is then removed from the first chamber and transported to a second chamber. The deposition of the same metal layer continues in a second chamber, having the same grain structure and orientation. The second portion of the metal layer is grown to achieve the final thickness. By using two different deposition chambers to form the single metal layer, layers in excess of 25,000 angstroms in thickness can be obtained.
    Type: Application
    Filed: May 13, 2003
    Publication date: November 18, 2004
    Applicant: STMicroelectronics Inc.
    Inventor: Ardeshir J. Sidhwa
  • Patent number: 6815326
    Abstract: An object of the present invention is to provide a technique for forming an ohmic connection between a semiconductor and a metal efficiently in a short period of time. The present invention provides a method of forming at least one electrode on a surface of a semiconductor, wherein a metal or alloy for the electrode is rubbed against a predetermined region of the semiconductor surface so as to be adhered by frictional force and frictional heat to the predetermined region of the semiconductor as an electrode and part of the adhered metal or a metal of the alloy is diffused into an inside of the semiconductor by the frictional heat thereby to be formed into an ohmic electrode substantially simultaneously when the metal or alloy is adhered by the frictional force and frictional heat to the predetermined region of the semiconductor.
    Type: Grant
    Filed: March 19, 2003
    Date of Patent: November 9, 2004
    Assignee: Fuji Machine Mfg. Co., Ltd.
    Inventors: Kouichi Asai, Kazutoshi Sakai, Kazuya Suzuki, Hirofumi Koike, Shunji Yoshikane, Kenji Tanaka
  • Patent number: 6815351
    Abstract: A semiconductor configuration with an ohmic contact-connection includes a p-conducting semiconductor region made of silicon carbide. A p-type contact region serves for the contact-connection. The p-type contact region is composed of a material containing at least nickel and aluminum. A substantially uniform material composition is present in the entire p-type contact region. A method for contact-connecting p-conducting silicon carbide with a material containing at least nickel and aluminum is also provided. The two components nickel and aluminum are applied simultaneously on the p-conducting semiconductor region.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: November 9, 2004
    Assignee: SiCED Electronics Development GmbH & Co. KG
    Inventors: Peter Friedrichs, Dethard Peters, Reinhold Schörner
  • Patent number: 6815342
    Abstract: Low resistance interconnect lines and methods for fabricating them are described herein. IC fabrication processes are used to create interconnect lines of Al and Cu layers. The Cu layer is thinner than in the known art, but in combination with the Al layer, the aggregate Cu/Al resistance is lowered to a point where it is comparable to that of a very thick Cu layer, without the additional cost and yield problems caused by using a thicker Cu deposition. Fuses for memory repair can also be fabricated using the methods taught by the present invention with only small variations in the process.
    Type: Grant
    Filed: November 27, 2001
    Date of Patent: November 9, 2004
    Assignee: LSI Logic Corporation
    Inventors: Chuan-cheng Cheng, Sethuraman Lakshminarayanan, Peter J. Wright, Hong Ying
  • Patent number: 6815337
    Abstract: A process for reducing the risk of removing metal from an underlying metal structure during a dry etch procedure used to define a borderless, overlying metal line structure, has been developed. After formation of a damascene type, underlying metal structure, deposition of an metal layer and of an overlying silicon oxide layer, is performed. A photoresist shape is used as an etch mask to allow formation of a partially etched metal line structure to be accomplished in the silicon oxide layer, and in a top portion of the metal layer. Insulator spacers are then formed on the sides of the partially etched metal line structure, resulting in a wider, partially etched metal line structure. The hard mask now presented by the defined silicon oxide component of the partially etched metal line structure, is then used as an etch mask allowing a final metal line structure, wider than the partially etched metal line structure, to be obtained.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: November 9, 2004
    Assignee: Episil Technologies, Inc.
    Inventor: Hsi Mao Hsiao
  • Patent number: 6806529
    Abstract: In an electrically programmable non-volatile memory cell, the first terminal of a high density capacitive structure is electrically connected to a conductive structure to form a floating gate/first electrode, while the second terminal of the capacitive structure is used as a control gate, providing a cell with a high overall capacitive coupling ratio, a relatively small area, and a high voltage tolerance.
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: October 19, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Yuri Mirgorodski, Andy Strachan
  • Patent number: 6803327
    Abstract: The present invention teaches the deposition of a pattern of interconnecting lines and bond pads. Passivation layers are deposited over this metal pattern. A layer of photosensitive polyimide is deposited over the passivation layers. This layer of photosensitive polyimide is patterned, exposed and developed to expose the underlying bonding pads. The remaining polyimide is cured and cross-linked and remains in place to serve as a buffer during further device packaging. Key to the present invention is that the remaining photosensitive polyimide is not removed after the bond pad has been exposed.
    Type: Grant
    Filed: April 5, 1999
    Date of Patent: October 12, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Shih-Shiung Cheu, Yea-Dean Sheu, Chih-Heng Shen
  • Patent number: 6803266
    Abstract: A process for passivating the semiconductor-dielectric interface of a MOS structure to reduce the interface state density to a very low level. A particular example is a MOSFET having a tungsten electrode that in the past has prevented passivation of the underlying semiconductor-dielectric interface to an extent sufficient to reduce the interface state density to less than 5×1010/cm2−eV. Though substantially impervious to molecular hydrogen, thin tungsten layers are shown to be pervious to atomic hydrogen, enabling atomic hydrogen to be diffused through a tungsten electrode into an underlying semiconductor-dielectric interface.
    Type: Grant
    Filed: March 20, 2003
    Date of Patent: October 12, 2004
    Assignee: International Business Machines Corporation
    Inventors: Paul M. Solomon, Douglas A. Buchanan, Eduard A. Cartier, Kathryn W. Guarini, Fenton R. McFeely, Huiling Shang, John J. Yourkas
  • Publication number: 20040192038
    Abstract: There is provided a method for forming wiring or an electrode by coating a substrate with a composition comprising (A) a complex of an amine compound and a hydrogenated aluminum compound and (B) a titanium compound or a composition comprising the complex and (C) metal particles and subjecting the obtained coating film to heating and/or a light treatment. By the method, a film can be formed that uses a conductive film forming composition with which wiring and an electrode that can be suitably used for electronic devices can be formed easily and inexpensively.
    Type: Application
    Filed: March 25, 2004
    Publication date: September 30, 2004
    Applicants: JSR Corporation, SHARP CORPORATION, International Center for Materials Research
    Inventors: Yasuaki Yokoyama, Isamu Yonekura, Takashi Satoh, Tamaki Wakasaki, Yasumasa Takeuchi, Masayuki Endo
  • Patent number: 6797611
    Abstract: A method of fabricating contact holes on a semiconductor chip with a plurality of gates and a first mask layer includes filling a dielectric layer into the inter-gate space of two gates, polishing the dielectric layer until the surface of the dielectric layer is coplanar with the gates, depositing a second mask layer, etching the second mask layer to form a bit line opening in an array area and simultaneously forming a gate opening and a substrate opening in a periphery area, removing a portion of the dielectric layer through the bit line opening and the substrate opening to form a bit line contact hole and a substrate contact hole, filling a metal layer into the bit line contact hole and the substrate contact hole, and etching the first mask layer through the gate opening to form a gate contact hole.
    Type: Grant
    Filed: August 3, 2003
    Date of Patent: September 28, 2004
    Assignee: Nanya Technology Corp.
    Inventors: Kuo-Chien Wu, Yinan Chen
  • Publication number: 20040185660
    Abstract: A method for manufacturing a semiconductor device having a semiconductor substrate with a contact hole filled by an aluminum-containing thin film. This manufacturing method includes a step of forming a silicon-containing thin film in a region having a predetermined area including the inner surface of the contact hole on the surface of the semiconductor substrate, an step of forming an aluminum-containing thin film on the surface of the semiconductor substrate on which the silicon-containing thin film is formed, and a step of heating the semiconductor substrate on which the aluminum-containing thin film is formed to such a temperature as to cause silicon to diffuse with respect to aluminum.
    Type: Application
    Filed: January 29, 2004
    Publication date: September 23, 2004
    Inventor: Masaru Takaishi
  • Patent number: 6794282
    Abstract: A method of forming a semiconductor device includes providing a semiconductor device including a conductor formed thereon. A dielectric layer is formed over the conductor and a recess is formed in the dielectric layer by removing a portion of the dielectric layer to expose at least a portion of the conductor. A first layer of aluminum is deposited over the top surface of the dielectric, along the sidewalls of the dielectric layer and over the exposed portion of the conductor without altering the temperature of the semiconductor device. A second layer of aluminum is deposited over the first layer of aluminum at a temperature greater than about 300° C. A third layer of aluminum is deposited over the second layer of aluminum so as to completely fill the recess in the dielectric layer. The third layer of aluminum is slow deposited at a temperature greater than about 300° C.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: September 21, 2004
    Assignee: Infineon Technologies AG
    Inventors: Thomas Goebel, Werner Robl, Rajeev Malik, Mihel Seitz
  • Patent number: 6790767
    Abstract: A method for formation of a copper diffusion barrier film using aluminum is disclosed. In the method, thin aluminum (Al) film is deposited on a dielectric, and a surface of the deposited aluminum film is plasma treated with NH3, thereby transforming the surface of the plasma treated aluminum film into a nitride film basically composed of aluminum nitride (AlxNy), and an aluminum film is deposited on the surface of the transformed aluminum nitride film, and copper is deposited on the surface of the deposited aluminum film. Therefore, because the diffusion of copper is suppressed, the problem that leakages between metal lines increase as pitches between the metals decrease due to high integration of parts of semiconductor can be settled.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: September 14, 2004
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Jae Suk Lee
  • Patent number: 6790764
    Abstract: In one aspect, the invention includes a processing method, comprising: a) providing a substrate having a high aspect ratio opening therein; b) forming a metal-comprising layer over the opening; c) providing a first pressure against the metal-comprising layer; and d) ramping the pressure that is against the metal-comprising layer to a second pressure at a rate of from about 1 atmosphere per second about 100 atmospheres per second.
    Type: Grant
    Filed: February 5, 2003
    Date of Patent: September 14, 2004
    Assignee: Micron Technology, Inc.
    Inventor: John H. Givens
  • Patent number: 6790773
    Abstract: A process and structure are provided that allows electroplating to fill sub-micron, high aspect ratio features using a non-conformal conductive layer between the dielectric layer and the platability layer. The conductive layer is a relatively thick layer overlying the planar surface of the wafer and the bottom of the features to be filled. Little or no material of the conductive layer is formed on the feature sidewalls. The thick conductive layer on the field provides adequate conductivity for uniform electroplating, while the absence of significant conductive material on the sidewalls decreases the aspect ratio of the feature and makes void-free filling easier to accomplish with electroplating. Further, the absence of significant material on the sidewalls allows a thicker barrier layer to be formed for higher reliability.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: September 14, 2004
    Assignee: Novellus Systems, Inc.
    Inventors: John S. Drewery, Ronald A. Powell
  • Patent number: 6790757
    Abstract: The present invention uses wire bonding technology to bond interconnect materials that oxidize easily by using a wire with stable oxidation qualities. A passivation layer is formed on the semiconductor substrate to encapsulate the bonding pad made from the interconnect material such that the wire bonds with the passivation layer itself, not with the interconnect material. The passivation layer is selected to be a material that is metallurgically stable when bonded to the interconnect material. Since the wire is stable compared with the interconnect material, i.e., it does not readily corrode, a reliable mechanical and electrical connection is provided between the semiconductor device (interconnect material) and the wire, with the passivation layer disposed therebetween.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: September 14, 2004
    Assignee: Agere Systems Inc.
    Inventors: Sailesh Chittipeddi, Sailesh Mansinh Merchant
  • Patent number: 6790774
    Abstract: A wiring film, which can be formed into wiring for ULSI semiconductor circuits, is formed by first forming holes in an insulating film on a substrate; then depositing a metallic material of copper, copper alloy, silver or silver alloy into the holes under an atmosphere including hydrogen; and finally annealing the deposited metallic material. The metallic material can be deposited by a sputtering process in which the atmosphere includes an inert gas in addition to the hydrogen. Hydrogen doped in the metallic material during the sputtering process promotes diffusion of atoms in the metallic material. The diffusion eliminates voids in the deposited metallic material.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: September 14, 2004
    Assignee: Kobe Steel, Ltd.
    Inventors: Takao Fujikawa, Makoto Kadoguchi, Kohei Suzuki, Takuya Masui
  • Patent number: 6787468
    Abstract: A method of fabricating a semiconductor device having a recess region in an insulation layer on a silicon substrate, comprising the steps of depositing a barrier metal over the entire surface of the insulation layer including the substrate surface in the recess region, depositing selectively an anti-nucleation layer on the barrier metal except in the recess region, depositing a CVD-Al layer on the barrier metal in the recess region, depositing a metal or a metal alloy inhibiting aluminum migration on the anti-nucleation layer and the barrier metal except in the recess region, and depositing a PVD-Al layer and re-flowing the PVD-Al layer, for improving the quality of aluminum grooves. The present method inhibits PVD-Al migration and grain growth, which results in preventing abnormal patterning in the semiconductor device.
    Type: Grant
    Filed: January 4, 2002
    Date of Patent: September 7, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Hee Kim, Jong-Myeong Lee, Myoung-Bum Lee, Gil-Heyun Choi
  • Patent number: 6784105
    Abstract: A method of fabricating a semiconductor device having a dielectric structure on which an interconnect structure is optionally patterned using lithographic and etching techniques, within a single deposition chamber, is provided. The dielectric structure may optionally be covered by diffusion barrier materials prior to a sputter etching process. This sputter etching process is used to remove the native oxide on an underneath metal conductor surface and includes a directional gaseous bombardment with simultaneous deposition of metal neutral. Diffusion barrier materials may also be deposited into the pattern.
    Type: Grant
    Filed: April 9, 2003
    Date of Patent: August 31, 2004
    Assignees: Infineon Technologies North America Corp., International Business Machines Corporation, United Microelectronics Co.
    Inventors: Chih-Chao Yang, Yun Wang, Larry Clevenger, Andrew Simon, Stephen Greco, Kaushik Chanda, Terry Spooner, Andy Cowley, Sunfei Fang
  • Patent number: 6777318
    Abstract: A method of forming at least one aluminum/copper clad interconnect comprising the following steps. A substrate is provided having an overlying patterned dielectric layer. The patterned dielectric layer having at least one lower opening. The at least one lower opening is lined with a first barrier layer. At least one planarized copper portion is formed within the at least one first barrier layer lined lower opening. A patterned layer is formed over the at least one planarized copper portion and the patterned dielectric layer. The patterned layer has at least one upper opening exposing at least a portion of the at least one planarized copper portion. The at least one upper opening is lined with a second barrier layer. At least one aluminum portion is formed within the at least one second barrier layer lined opening to form the at least one aluminum/copper clad interconnect.
    Type: Grant
    Filed: August 16, 2002
    Date of Patent: August 17, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Shin-Puu Jeng, Shang-Yun Hou
  • Publication number: 20040157435
    Abstract: Methods for forming metal lines in semiconductor devices are disclosed. One example method may include forming a lower adhesive layer on a semiconductor substrate; forming a metal layer including aluminum on the lower adhesive layer; forming an anti-reflection layer on the metal layer; forming a photomask on the anti-reflection layer; performing an initial etching, a main etching and an over-etching for the anti-reflection layer, the metal layer and the lower adhesive layer, respectively, in a region which is not protected by the photomask, using C3F8 as a main etching gas; and removing the photomask residual on the anti-reflection layer.
    Type: Application
    Filed: December 30, 2003
    Publication date: August 12, 2004
    Inventor: Tae-Hee Park
  • Publication number: 20040140490
    Abstract: A hillock-free gate layer and method of manufacturing the same is disclosed. One or more pure aluminum layers are formed under high pressure and low sputtering power. An aluminum layer containing nitrogen is then formed on the pure aluminum layers to prevent the formation of hillocks and to reduce manufacturing costs.
    Type: Application
    Filed: October 1, 2003
    Publication date: July 22, 2004
    Inventor: Cheng-Chi Wang
  • Patent number: 6764953
    Abstract: The electronic device (1) has a layer (11) of a material comprising a first and a second element. This material has an amorphous and a crystalline state. A transition from the amorphous to the crystalline state can be effected by heating of the material to above a crystallization temperature, for example with a laser. As a result, the layer (11) has a first electrically conducting areas (21), comprising the material in the crystalline state, which are insulated from each other by the first electrically insulating area (23), comprising the material in the amorphous state. The layer (11) may be present as an interconnect layer, but also as a covering layer. Preferably, the material is aluminum-germanium. In the method of patterning a layer (11), electrically conductive areas of the layer can be strengthened by electroplating.
    Type: Grant
    Filed: November 18, 2002
    Date of Patent: July 20, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Jan Johannes Van Den Broek, Coen Theodorus Hubertus Fransiscus Liedenbaum, Andreas Hubertus Montree, Arjen Boogaard, Willem Reindert De Wild, Johannes Nicolaas Huiberts
  • Patent number: 6762123
    Abstract: A method of producing a protective inhibitor layer of moisture-generated corrosion for aluminum (Al) alloy metallization layers, particularly in semiconductor electronic devices, includes chemically treating the metallization layer in at least two steps using a mixture of concentrated nitric acid and trace phosphoric acid to produce a thin protective phosphate layer. Alternatively, the method may include dipping the electronic device at least once in a mixture of a polar organic solvent and phosphoric acid (H3PO4) or phosphate derivatives thereof in a low percentage amount (e.g., with a phosphate reactant such as orthophosphoric acid or even R—HxPOy, where R is an alkaline type of ion group or an alkyl radical). The thin film may be formed on top of a thin layer of native aluminum oxide hydrate Al2O3.xH2O.
    Type: Grant
    Filed: January 16, 2003
    Date of Patent: July 13, 2004
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giuseppe Curro, Antonio Scandurra
  • Patent number: 6762501
    Abstract: Isolated metal structures (110), (140) are formed adjacent to terminated metal lines (100), (130) that are connect by a via (120). The isolated structures (110), (140) act to suppress the stress created in the terminated metal lines (100), (130) during thermal cycling.
    Type: Grant
    Filed: April 14, 2003
    Date of Patent: July 13, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Young-Joon Park, Andrew Tae Kim
  • Patent number: 6759317
    Abstract: An interconnection is formed on a semiconductor substrate having a semiconductor element formed thereon. Next, a passivation film is formed on the semiconductor substrate including the interconnection. Further, a polyimide film, which is served as a buffer coating film, is formed on the passivation film. Further, the polyimide film is patterned. Next, the passivation film is subject to etching while the patterned polyimide film is taken as a mask. Next, a hardened layer, which is formed on the surface of the polyimide film as a result of etching, is removed through ashing process. Next, the semiconductor substrate after ashing process is cured so as to transform the polyimide film into imide.
    Type: Grant
    Filed: July 24, 2001
    Date of Patent: July 6, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Hiroshi Tobimatsu, Yuuki Kamiura, Seiji Okura, Mahito Sawada
  • Patent number: 6759324
    Abstract: Structures and processes are disclosed for reducing electrical contact resistance between two metal layers. Specifically, a resistive aluminum oxide layer forms spontaneously on metal lines including aluminum, within a V-shaped contact via which is opened in an insulating layer through a mask. The mask includes an opening with a width of less than about 0.75 &mgr;m. After removing the mask, the via is treated with an RF etch. The resultant contact has a width at the bottom of less than 0.9 &mgr;m. A titanium layer of 300 Å to 400 Å is deposited into the via, with about 60 Å to 300 Å reaching the via bottom and reacted with the underlying aluminum. The reaction produces a titanium-aluminum complex (TiAlx) with a thickness of about 150 Å to 900 Å. Advantageously, this composite layer provides a low resistivity contact between the aluminum-containing layer and a subsequently deposited metal layer.
    Type: Grant
    Filed: November 13, 2000
    Date of Patent: July 6, 2004
    Inventors: Howard E. Rhodes, Sanh Tang
  • Patent number: 6756302
    Abstract: The invention concerns a method of forming a layer of metal on a substrate and fill the via with high throughput. A layer of metal can be formed on a substrate using sequentially a cold deposition step, a slow hot deposition step and a rapid hot deposition step. The cold deposition step need only be performed for a time sufficient to deposit a seed layer of metal over the entire surface on which the metal layer is to be formed. In the slow hot deposition step, further metal is deposited at a power allowing for surface diffusion of the deposited metal, which is then followed by a rapid hot deposition of metal under bulk diffusion conditions.
    Type: Grant
    Filed: October 17, 2000
    Date of Patent: June 29, 2004
    Assignee: Cypress Semiconductor Corporation
    Inventors: Ende Shan, Gorley Lau, Sam Geha
  • Patent number: 6753271
    Abstract: The invention includes an atomic layer deposition method of forming a layer of a deposited composition on a substrate. The method includes positioning a semiconductor substrate within an atomic layer deposition chamber. On the substrate, an intermediate composition monolayer is formed, followed by a desired deposited composition from reaction with the intermediate composition, collectively from flowing multiple different composition deposition precursors to the substrate within the deposition chamber. A material adheres to a chamber internal component surface from such sequentially forming. After such sequentially forming, a reactive gas flows to the chamber which is different in composition from the multiple different deposition precursors and which is effective to react with such adhering material. After the reactive gas flowing, such sequentially forming is repeated. Further implementations are contemplated.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: June 22, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Demetrius Sarigiannis, Garo J. Derderian, Cem Basceri, Gurtej S. Sandhu, F. Daniel Gealy, Chris M. Carlson
  • Patent number: 6746950
    Abstract: A low temperature aluminum planarization process. Vias, including high aspect ratio vias, are filled using a liner layer, a seed layer, and a fill layer. The device associated with the via is exposed to a reactive gas prior to applying the fill layer to the device.
    Type: Grant
    Filed: November 14, 2001
    Date of Patent: June 8, 2004
    Assignee: Vitesse Semiconductor Corporation
    Inventor: Ende Shan
  • Patent number: 6747355
    Abstract: A connection via hole is formed in an inter layer insulation film that covers a copper pad. Copper is formed within the connection via hole to form a connection copper via metal. An aluminum pad having a barrier metal thereunder for preventing reaction between copper and aluminum is formed on the connection copper via metal, thereby electrically connecting the copper pad and the aluminum pad to each other through the connection copper via metal. A step formed by the connection via hole that is formed in the inter layer insulation film is made substantially equal to zero with the aid of the connection copper via metal and at the same time, a film thickness of aluminum constituting the aluminum pad is reduced, thereby reducing manufacturing cost of the semiconductor device.
    Type: Grant
    Filed: July 17, 2002
    Date of Patent: June 8, 2004
    Assignee: NEC Electronics Corporation
    Inventors: Takahisa Abiru, Keisuke Hatano
  • Patent number: 6747359
    Abstract: A two-step via cleaning process which removes metal polymer and oxide polymer residues from a via with substantially no damage to the via or underlying structures on a semiconductor substrate. The via is formed through a dielectric layer and a barrier layer which are disposed over a metal-containing trace, pad, or other such circuitry, wherein the metal-containing trace, pad, or other circuitry is disposed on a semiconductor substrate. When such a via is formed, the sidewalls of the via are coated with a residue layer. The residue layer generally has a distinct oxide polymer component and a distinct metal polymer component. The two-step cleaning process comprises first subjecting the residue layer to a nitric acid dip which removes the metal polymer component to expose the oxide polymer component. The oxide polymer component is then subjected to a phosphoric acid dip which removes the oxide polymer component.
    Type: Grant
    Filed: August 25, 2000
    Date of Patent: June 8, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Li Li
  • Publication number: 20040102001
    Abstract: In a process for preparing contact layer (CL) contacts for DRAM products filled with aluminum by physical vapor deposition (PVD), the improvements of increasing the process window of wafers per hour per deposition chamber and filling the contact hole without a void to obtain high aspect ratio CL contacts, comprising:
    Type: Application
    Filed: November 27, 2002
    Publication date: May 27, 2004
    Applicant: Infineon Technologies North America Corp.
    Inventors: Thomas Goebel, Werner Robl, Rajeev Malik, Mihel Seitz
  • Patent number: 6734100
    Abstract: A conventional method of forming a ruthenium thin film has a problem that conditions for improving a surface morphology are contrary to those for improving a step coverage, with respect to an oxygen fraction, a pressure, a temperature, etc. Accordingly, it is difficult to obtain a thin film having the improved properties in both the surface morphology and the step coverage. This invention provides three methods for improving both the surface morphology and the step coverage. As one method of forming the ruthenium thin film, a ruthenium seed layer is first formed using a PECVD process and then a ruthenium thin film is deposited using a thermal CVD process. As another method, a first ruthenium thin film is deposited using a thermal CVD process and then a second ruthenium thin film is formed on the first ruthenium thin film using a PECVD process.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: May 11, 2004
    Assignee: Jusung Engineering Co., Ltd.
    Inventors: Kyung Woong Park, Jung Hwan Choi, Young Ki Han
  • Patent number: 6730591
    Abstract: A method of forming interconnect structures in a semiconductor device, comprising the following steps. A semiconductor structure is provided. In the first embodiment, at least one metal line is formed over the semiconductor structure. A silicon-rich carbide barrier layer is formed over the metal line and semiconductor structure. Finally, a dielectric layer, that may be fluorinated, is formed over the silicon-rich carbide layer. In the second embodiment, at least one fluorinated dielectric layer, that may be fluorinated, is formed over the semiconductor structure. The dielectric layer is patterned to form an opening therein. A silicon-rich carbide barrier layer is formed within the opening. A metallization layer is deposited over the structure, filling the silicon-rich carbide barrier layer lined opening. Finally, the metallization layer may be planarized to form a planarized metal structure within the silicon-rich carbide barrier layer lined opening.
    Type: Grant
    Filed: July 1, 2002
    Date of Patent: May 4, 2004
    Assignees: Chartered Semiconductor Manufactoring Ltd., Institute of Microelectronics
    Inventors: Licheng Han, Xu Yi, Simon Chooi, Mei Sheng Zhou, Joseph Zhifeng Xie
  • Publication number: 20040082167
    Abstract: A recess is formed in a microelectronic substrate, and then a metal-containing layer is formed that conforms to an inner surface of the recess and to a surface of the substrate adjacent the recess. A carbon concentration in a portion of the metal-containing layer on the surface of the substrate adjacent the recess is decreased in comparison to a portion of the metal-containing layer within the recess, e.g., using a plasma treatment that has a greater effect on the surface outside of the recess. Aluminum is then deposited on the metal-containing layer to form an aluminum layer that conforms to the inner surface of the recess and to the surface of the substrate adjacent the recess. Preferably, the carbon concentration in the portion of the metal-containing layer within the recess is sufficiently great to cause aluminum to deposited at a greater rate on the portion of the metal-containing layer within the recess.
    Type: Application
    Filed: July 16, 2003
    Publication date: April 29, 2004
    Inventors: Jung-Hun Seo, Gil-Heyun Choi, Ju-Young Yun, Byung-Hee Kim, Seung-Gil Yang
  • Patent number: 6727178
    Abstract: An etchant for patterning thin metal films by wet etching and in particular, an etchant for use in producing semiconductor devices, such as semiconductor elements and liquid-crystal display elements, is for application to a multilayer film having a first layer made of aluminum or an aluminum alloy having formed thereon a second layer made of aluminum or an aluminum alloy each containing at least one element selected from nitrogen, oxygen, silicon, and carbon, and has a phosphoric acid content of from 35 to 65% by weight and a nitric acid content of from 0.5 to 15% by weight; and an etching is performed using the etchant.
    Type: Grant
    Filed: April 21, 2003
    Date of Patent: April 27, 2004
    Assignees: Mitsubishi Chemical Corporation, Advanced Display Inc.
    Inventors: Noriyuki Saitou, Takuji Yoshida, Kazunori Inoue, Makoto Ishikawa, Yoshio Kamiharaguchi
  • Patent number: 6723642
    Abstract: A method for forming a nitrogen-containing oxide thin film by using plasma enhanced atomic layer deposition is provided. In the method, the nitrogen-containing oxide thin film is deposited by supplying a metal source compound and oxygen gas into a reactor in a cyclic fashion with sequential alternating pulses of the metal source compound and the oxygen gas, wherein the oxygen gas is activated into plasma in synchronization of the pulsing thereof, and a nitrogen source gas is further sequentially pulsed into the reactor and activated into plasma over the substrate in synchronization with the pulsing thereof. According to the method, a dense nitrogen-containing oxide thin film can be deposited at a high rate, and a trace of nitrogen atoms can be incorporated in situ into the nitrogen-containing oxide thin film, thereby increasing the breakdown voltage of the film.
    Type: Grant
    Filed: February 27, 2003
    Date of Patent: April 20, 2004
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jung-wook Lim, Sun-jin Yun
  • Patent number: 6720261
    Abstract: A system and method for eliminating interconnect extrusions in vias that are formed during ionized metal plasma processing. By eliminating interconnect extrusions in vias, reliability failures and yield loss are decreased. The extrusions of interconnect metallization occur while wafers are subject to elevated temperatures that cause the internal stresses in the interconnect metallization to transit from a substantially tensile mode to a substantially compressive mode. By controlling the interconnect temperature to be below the temperature at which the interconnect transits from a tensile to a compressive mode, interconnect extrusions in vias are eliminated. The interconnect temperature is controlled by using an actively cooled pedestal in combination with a low temperature IMP deposition process. In addition, the IMP processing time may also be decreased to limit heating of the interconnect.
    Type: Grant
    Filed: June 2, 2000
    Date of Patent: April 13, 2004
    Assignee: Agere Systems Inc.
    Inventors: Steven Mark Anderson, Siddhartha Bhowmik, Joseph William Buckfeller, Sailesh Mansinh Merchant, Frank Minardi
  • Patent number: 6720253
    Abstract: A semiconductor device is constituted by embedding an Al wiring layer in a second object formed on a interlayer-insulating film on one principal plane of a semiconductor substrate and connecting with an Al wiring formed on the substrate and at least, an Nb liner film and NbAl alloy film are formed between the second object and the Al wiring layer.
    Type: Grant
    Filed: September 4, 2001
    Date of Patent: April 13, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junichi Wada, Yasushi Oikawa, Tomio Katata
  • Patent number: 6716743
    Abstract: A method of forming wiring of a uniform film thickness using a damascene process is proposed. Tantalum nitride, copper, another copper, and another tantalum nitride, for example, all constituting conductive films of different polishing rates, are overlayed on the top layer of an insulating film in which one wiring groove and another wiring groove are formed. The film thickness of the tantalum nitride, the copper, the other copper, and the other tantalum nitride is set and formed so that the height of the surface of the tantalum nitride formed on a silicon oxide film excluding the one wiring groove matches the height of the surface of the other tantalum nitride formed on the top layer of the one wiring groove. Subsequently, polishing takes over to complete the forming process.
    Type: Grant
    Filed: May 29, 2002
    Date of Patent: April 6, 2004
    Assignee: Sony Corporation
    Inventor: Naoki Nagashima
  • Patent number: 6713384
    Abstract: A method of making a contact plug and a metallization line structure is disclosed in which a substrate is provided with at least one contact hole within an insulation layer situated on a semiconductor substrate of a semiconductor wafer. A first metal layer is deposited upon the semiconductor wafer within the contact hole. A planarizing step isolates the first metal layer within the insulation layer in the form of a contact plug within the contact hole. A second metal layer is then deposited upon the semiconductor wafer over and upon the contact plug. Metallization lines are patterned and etched from the second metal layer. The contact hole may also be lined with a refractory metal nitride layer, with a refractory metal silicide interface being formed at the bottom of the contact hole as an interface between the contact plug and a silicon layer on the semiconductor substrate.
    Type: Grant
    Filed: January 16, 1998
    Date of Patent: March 30, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Richard L. Elliott, Guy F. Hudson
  • Publication number: 20040058529
    Abstract: This invention relates to a method of depositing a layer on an exposed surface of an insulating layer of material. The method includes treating the exposed surface with hydrogen or a gaseous source of hydrogen in the presence of a plasma, prior to or during deposition of a metallic layer.
    Type: Application
    Filed: September 4, 2003
    Publication date: March 25, 2004
    Inventors: Knut Beekman, Paul Rich, Claire Louise Wiggins
  • Patent number: 6709874
    Abstract: A semiconductor device (100) having a copper damascene BEOL structure. A metal cap layer (120) is formed over conductive lines (118) to prevent oxidation of the conductive lines (118) during subsequent processing steps. The metal cap layer (120) comprises a material other than the conductive line (118) material that is resistant to oxidation. The structure (100) is particularly beneficial for MRAM devices.
    Type: Grant
    Filed: March 2, 2001
    Date of Patent: March 23, 2004
    Assignee: Infineon Technologies AG
    Inventor: Xian J. Ning
  • Publication number: 20040048460
    Abstract: A semiconductor device having a contact structure that can exhibit superlative step coverage without causing voids or wiring discontinuities, using aluminum or aluminum alloys as a conductive substance for via-holes. A method of fabricating the semiconductor device comprises, for at least one layer of wiring regions above the first wiring region on a semiconductor substrate, the following steps (a) to (f): (a) a step of forming a via-hole in a second interlayer dielectric formed above the first wiring region on a semiconductor substrate; (b) a degassing step for removing gaseous components included within the interlayer dielectric by a heat treatment under reduced pressure and at the substrate temperature of 300° C. to 550° C.; (c) a step of forming a wetting layer on the surface of the interlayer dielectric and the via-hole; (d) a step of cooling the substrate to a temperature of no more than 100° C.
    Type: Application
    Filed: July 7, 2003
    Publication date: March 11, 2004
    Applicant: Seiko Epson Corporation
    Inventors: Michio Asahina, Junichi Takeuchi, Naohiro Moriya, Kazuki Matsumoto