Abstract: A method for processing semiconductor wafers is disclosed. A solution is applied to a semiconductor wafer to prevent dendrites and electrolytic reactions at the surface of metal interconnects. The solution can be applied during a CMP process or during a post CMP cleaning process. The solution may include a surfactant and a corrosion inhibitor. In one embodiment, the concentration of the surfactant in the solution is less than approximately one percent by weight and the concentration of the corrosion inhibitor in the solution is less than approximately one percent by weight. The solution may also include a solvent and a cosolvent. In an alternate embodiment, the solution includes a solvent and a cosolvent without the surfactant and corrosion inhibitor. In one embodiment, the CMP process and post CMP cleaning process can be performed in the presence of light having a wavelength of less than approximately one micron.

Abstract: Described is a polishing technique adapted for multilevel metallization of an electronic circuit device, which comprises polishing a metal film with a polishing liquid containing an oxidizing substance, a phosphoric acid and a protection-layer forming agent. The present invention makes it possible to polishing a metal film at a high removal rate while suppressing occurrence of scratches, delamination, dishing or erosion.

Abstract: The object of the present invention is to provide a process for chemical mechanical polishing of semiconductor substrate that is particularly useful for chemical mechanical polishing a wafer having a wiring pattern and an insulating layer having a low dielectric constant is formed between wiring patterns, interlayers in the case of a multi-layer wiring and the like in the process of producing a semiconductor device, and an aqueous dispersion for chemical mechanical polishing which is used in this process.

Abstract: In accordance with the objectives of the invention a new method is provided to tune the Edge Bead Remove hump and to further prevent a pointed or tip shaped Edge Bead Remove edge, thus preventing peeling of the low-k dielectric film after the process of Chemical Mechanical Polishing of the low-k film.

Abstract: According to the present invention, a metal and a barrier material, such as copper and a tantalum-based barrier material, are effectively removed from the wafer edge and especially from the bevel by using an etchant that comprises a diluted mixture of hydrofluoric acid and nitric acid. The method is compatible with currently available etch modules for removing metal from the wafer edge, wherein, depending on the hardware specifics, copper, barrier material and dielectric material may be removed in a single etch step, or a first etch step may be performed substantially without any nitric acid so as to avoid the formation of nitric oxides. In this way, the formation of instable layer stacks may be substantially avoided, thereby reducing the risk of material delamination from the substrate edge.

Abstract: Aqueous dispersion containing a silicon-aluminum mixed oxide powder, the powder containing 0.1 to 99.9 wt. % Al2O3 and Si—O—Al-bonds. The dispersion can be produced using dispersing and/or grinding devices which a achieve an energy input of at least 200 KJ/m3. The dispersion can be used for the chemical-mechanical polishing of semiconductor substrates.

Abstract: The invention provides a method of polishing a substrate comprising (i) contacting a substrate comprising a noble metal layer with a chemical-mechanical polishing system comprising (a) a polishing component, (b) an oxidizing agent, and (c) a liquid carrier, and (ii) abrading at least a portion of the noble metal layer to polish the substrate. The polishing component is selected from the group consisting of an abrasive, a polishing pad, or a combination thereof, and the oxidizing agent is selected from the group consisting of bromates, bromites, hypobromites, chlorates, chlorites, hypochlorites, perchlorates, iodates, hypoiodites, periodates, peroxyacetic acid, organo-halo-oxy compounds, salts thereof, and combinations thereof. The chemical-mechanical polishing system has a pH of about 9 or less, and the oxidizing agent does not produce a substantial amount of elemental halogen.

Abstract: Cassettes for holding thin semiconductor wafers for safe handling are provided, along with an improved methodology for reducing the thickness of semiconductor wafers. Embodiments include a cassette for holding thin semiconductor wafers, having a plurality of sets of center and edge supports, the sets being spaced from each other a distance greater than a sag amount of the wafers. The thin wafers are supported in a predetermined reference plane, so that tools such as robots or automatic handlers can be programmed to pick them up without damaging them. In another embodiment, a double into single pitch wafer cassette is provided having a wafer entrance section with spacing twice as large between sets of edge supports as a conventional cassette, to accommodate the sag/warp of the thin wafers, and a “flattening section” which guides and flattens the wafers between opposing edge supports as they are pushed into the cassette, such that the wafers are held substantially planar.

Abstract: A planarizing pad for planarizing a microelectronic substrate, and a method and apparatus for forming the planarizing pad. In one embodiment, planarizing pad material is mixed with compressed gas to form a plurality of discrete elements that are distributed on a film support material. The film support material is supported by a liquid and is drawn from the liquid with a backing layer. At least a portion of the discrete elements are spaced apart from each other on the film support material to form a textured surface for engaging a microelectronic substrate and removing material from the microelectronic substrate. The discrete elements can be uniformly or randomly distributed on the film support material.

Abstract: A method for forming a split-gate flash memory structure includes etching a first gate layer to form one or more floating gates and forming an isolation layer over the floating gates. An insulation layer is deposited over the isolation layer and planarized.

Abstract: Fabricating a semiconductor structure includes providing a semiconductor substrate, forming a silicide layer over the substrate, and removing a portion of the silicide layer by chemical mechanical polishing. The fabrication of the structure can also include forming a dielectric layer after forming the silicide layer, and removing a portion of the dielectric layer by chemical mechanical polishing before removing the portion of the silicide layer.

Abstract: A method for forming a pre-metallization layer on an underlying micro-structure, and a corresponding micro-structure formed by the method. The micro-structure may be a semiconductor circuit and/or a Micro-Electro-Mechanical Systems (MEMS) device. A first layer of undoped silicate glass is deposited on a micro-structure. Then, a layer of phospho silicate glass is deposited on the first layer of undoped silicate glass. This combination is then densified by applying a temperature to the combination that is sufficient to densify the layer of phospho-silicate glass, while being below the glass flow temperature. After densification, a second layer of undoped silicate glass is deposited on the densified layer of phospho silicate glass. Finally, the upper surface of the second layer of undoped silicate glass is polished using a chemical mechanical polishing process. The result is a dielectric layer of high density and low stress, and that reduces soft errors and defects.

Abstract: A polishing method and a polishing apparatus by which excess portions of a metallic film 18 can be removed easily and efficiently in planarizing the metallic film 18 by polishing and which is high in accuracy of polishing, are provided. Also, a method of manufacturing a semiconductor device by use of the polishing method and the polishing apparatus is provided. A substrate 17 provided with the metallic film 18 and a counter electrode 15 are disposed oppositely to each other in an electrolytic solution E, an electric current is passed to the metallic film 18 through the electrolytic solution E, and the surface of the metallic film 18 is polished with a hard pad 14.

Abstract: A method is provided for imprinting a pattern having nanoscale features from a mold into the patternable layer on a substrate. The method comprises: providing the mold; forming the patternable layer on the substrate; and imprinting the mold into the patternable layer, wherein the patternable layer comprises a metal or alloy having a transition temperature from its solid form to its liquid form that is within a range of at least 10° above room temperature.

Abstract: A method for Chemical-Mechanical Polishing utilizes a two step process. The first step utilizes a slurry with abrasive particles which become embedded into a conditioned polishing pad having small cavities in the surface. During the second step the slurry flow is discontinued and the final polishing is performed using the embedded small abrasive particles. Using this method dishing has been reduced considerably, and has enabled the fabrication of a Damascene metal gate NMOSFET fabricated with Atomic Layer Deposition (ALD).

Abstract: A polishing technique wherein scratches, peeling, dishing and erosion are suppressed, a complex cleaning process and slurry supply/processing equipment are not required, and the cost of consumable items such as slurries and polishing pads is reduced A metal film formed on an insulating film comprising a groove is polished with a polishing solution containing an oxidizer and a substance which renders oxides water-soluble, but not containing a polishing abrasive.

Abstract: A method of forming a semiconductor device includes implanting a precipitate into a gate conductor of an at least partially formed semiconductor device. The gate conductor including a plurality of semiconductor grains. The boundaries of adjacent grains forming a dopant migration path. A plurality of precipitate regions are formed within the gate conductor. At least some of the precipitate regions located at a junction of at least two grains. The gate conductor of the at least partially formed semiconductor device is doped with a dopant. The dopant diffuses inwardly along the dopant migration path.

Abstract: The present invention provides a Group III nitride crystal substrate whose surface has concavities and convexities reduced in size. The surfaces with concavities and convexities, such as hillocks, pits and facets, of Group III nitride crystals are brought into contact with a melt and thereby the surfaces are subjected to meltback etching or mechanochemical polishing. The melt includes at least one of alkali metal and alkaline-earth metal. Thus a Group III nitride crystal substrate that has reduced strain and a reduced number of defects, which are caused through the processing, and is excellent in surface flatness is manufactured. Furthermore, by the use of the Group III nitride crystal substrate of the present invention, for instance, semiconductor devices of high performance can be obtained.

Abstract: A method and apparatus for making and using slurries for planarizing microelectronic-device substrate assemblies in mechanical and/or chemical-mechanical planarization processes. In one aspect of the invention, a bi-modal slurry is fabricated by removing a first type of selected abrasive particles from a first abrasive particle solution to form a treated flow of the first solution. The treated flow of the first solution is then combined with a flow of a second solution having a plurality of second abrasive particles. The abrasive particles of the first type are accordingly removed from the first solution separately from the second solution such that the second abrasive particles in the second solution do not affect the removal of the abrasive particles of the first type from the first solution. In another aspect of the invention, a second type of selected abrasive particles are removed from the second solution prior to mixing with the first solution.

Abstract: The present invention relates to a process for forming a near-planar or planar layer of a conducting material, such as copper, on a surface of a workpiece using an ECMPR technique. The process preferably uses at least two separate plating solution chemistries to form a near-planar or planar copper layer on a semiconductor substrate that has features or cavities on its surface.

Abstract: A thermal cleaning of a substrate that has been subjected to wet cleaning is carried out under a high vacuum atmosphere to remove an oxide film remaining on the substrate. Thereafter, a thermal cleaning is carried out under a hydrogen atmosphere to remove contamination such as carbon or the like. At this time, the oxide film has already been removed and therefore contamination is effectively removed by a relatively low temperature and short duration thermal cleaning. Thus, problems such as the degradation of the profile of the impurity concentration in the impurity diffusion layer which has been formed over the substrate are prevented.

Abstract: The present invention provides a chemical-mechanical polishing slurry for use in removing a barrier layer during the fabrication of a damascene structure. The slurry according to the invention includes an agent that suppresses the rate at which an underlying silicon-containing dielectric layer is removed. In the presently most preferred embodiment of the invention, the agent that suppresses the rate at which an underlying silicon-containing dielectric layer is removed is L-lysine and/or L-arginine. The present invention also provides a method of suppressing the removal rate of an underlying silicon-containing dielectric layer during the chemical-mechanical polishing of a barrier layer in a damascene structure. The method according to the invention includes polishing the barrier layer with a slurry comprising an agent that suppresses the rate at which said underlying silicon-containing dielectric layer is removed.

Abstract: A liquid application material that is capable of forming an oxidized insulator as a result of baking is applied onto a support substrate to produce an object of processing. Then, a mold having projection structures with intervals of nanometers is pressed against the applied liquid material to produce corresponding recess structures. Thereafter, the applied liquid material is baked in oxygen-containing gas or oxidized in ozone or oxygen plasma to make it electrically highly resistive. Subsequently, a layer to be anodized is formed on said oxidized insulator. Then, the layer to be anodized is actually anodized in an acidic solution to form fine holes that are aligned with the respective recess structures in the anodized layer. Accordingly, fine recess structures can be manufactured with ease.

Abstract: Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted into the exposed gate structure.

Abstract: Conditioning apparatuses and methods for conditioning polishing pads used for mechanical and/or chemical-mechanical planarization of micro-device workpieces are disclosed herein. In one embodiment, a method for conditioning a polishing pad used for polishing a micro-device workpiece includes monitoring surface condition in a first region of the polishing pad and adjusting at least one of a rotational velocity of the polishing pad, a downforce on the polishing pad, and a sweep velocity of the end effector in response to the monitored surface condition to provide a desired texture in the first region. In another embodiment, an apparatus for conditioning the polishing pad includes an end effector, a monitoring device, and a controller operatively coupled to the end effector and the monitoring device. The controller has a computer-readable medium containing instructions to perform a conditioning method, such as the above-mentioned method.

Abstract: Method and system for fabricating an electrical interconnect capable of supporting very high current densities (106–1010 Amps/cm2), using an array of one or more carbon nanotubes (CNTs). The CNT array is grown in a selected spaced apart pattern, preferably with multi-wall CNTs, and a selected insulating material, such as SiOw or SiuNv, is deposited using CVD to encapsulate each CNT in the array. An exposed surface of the insulating material is planarized to provide one or more exposed electrical contacts for one or more CNTs.

Abstract: CMP of integrated circuits containing DRAM arrays with trench capacitors fill the trenches with oxide, resulting in a an array of oxide structures that is dense compared with the concentration in the surrounding support structures and therefore has a higher loading. A conformal layer is deposited over the wafer, increasing the loading in the array, but filling in spaces between active areas. A blanket etch removes material in both the array and the supports. A block etch balances the amount of material in the array and the supports. A supplementary oxide deposition in the array fills spaces between the structures to a nearly uniform density.

Abstract: An algorithm uses offline metrology to control a process by passing information from an outer control loop to an inner control loop, extended Kalman filter estimator. The inner control loop operates online, and the outer control loop operates asynchronously with respect to the inner control loop. The online control loop is updated for each subsequent process. The offline metrology is optionally updated for each subsequent process.

Abstract: The copper interconnect formed by the use of a damascene technique is improved in dielectric breakdown strength (reliability). During post-CMP cleaning, alkali cleaning, a deoxidizing process due to hydrogen annealing or the like, and acid cleaning are carried out in this order. After the post-CMP cleaning and before forming an insulation film for a cap film, hydrogen plasma and ammonia plasma processes are carried out on the semiconductor substrate. In this way, a copper-based buried interconnect is formed in an interlayer insulation film structured of an insulation material having a low dielectric constant.

Abstract: A method of manufacturing a semiconductor device comprises: forming a first pattern in a first region over a semiconductor substrate; forming a second pattern in a second region separated from the first region over the semiconductor substrate; depositing an interlayer insulation film to cover the first and second patterns; forming a photoresist film on the interlayer insulation film; treating the photoresist film in stepper exposure and development to form a photoresist pattern of a photomask having its device pattern matched with the first pattern and its alignment marks matched with the second pattern; selectively etching off the interlayer insulation film over the first and second patterns, with the photoresist pattern; and after removing the photoresist pattern, flattening the interlayer insulation film to expose the surfaces of the first and second patterns, respectively.

Abstract: A leadless plastic chip carrier is fabricated by selectively etching a leadframe strip to reduce a thickness of the strip at a portion thereof. Selectively masking the surface of the leadframe strip using a mask, follows selectively etching, to provide exposed areas of the surface at the portion and contact pad areas on leadframe the strip. At least one layer of metal is deposited on the exposed areas to define a die attach pad on the portion of the leadframe strip with reduced thickness and to define contact pads on the surface of the strip. At least one semiconductor die is mounted to the die attach pad, followed by wire bonding the at least one semiconductor die to ones of the contact pads. The at least one semiconductor die, the wire bonds, and the contact pads are covered with an overmold material and the leadframe strip is etched to thereby remove the leadframe strip. The leadless plastic chip carrier is singulated from the leadframe strip.

Abstract: Compound-semiconductor-wafer manufacturing whereby particle adherence, and obverse-surface oxidization and alteration are slight and the use of organic solvents is reduced. An adsorption pad is bonded to a polishing plate, and a wafer being adsorbed onto the adsorption pad without using wax is polished and thereafter stored within purified water without drying. Since storage is within purified water, particle adherence, and obverse-surface oxidization and alteration turn out to be slight, yielding a high-quality wafer. In the cleaning procedure following the aquatic storage, organic solvent washing is omitted. This allows the use/waste volume of noxious organic solvent to be reduced.

Abstract: A method for the production of airgaps in a semiconductor device and device produced therefrom. The formation of airgaps is accomplished, in part, by chemically and/or mechanically changing the properties of a first dielectric layer locally, such that at least part of said first dielectric layer is converted locally and becomes etchable by a first etching substance. The local conversion of the dielectric material may be achieved during anisotropic etching of the material in oxygen containing plasma or ex-situ by performing an oxidizing step (e.g., a UV/ozone treatment or supercritical carbon dioxide with addition of an oxidizer). Formation of airgaps is achieved after creation of conductive lines and, alternatively, a barrier layer by a first etching substance. The airgaps are formed in a dual damascene structure, near the vias and/or the trenches of the damascene structure.

Abstract: A method for forming a void free ultra thick dual damascene copper feature providing a semiconductor process wafer comprising via openings formed in a first undoped silicate glass (USG) layer the first USG layer having an overlying a second USG layer formed having a thickness of greater than about 1 micron and an overlying silicon oxynitride BARC layer; forming a trench opening having a width of greater than about 1 micron to encompass one of the via openings; forming a barrier layer to line the dual damascene opening; forming a copper seed layer having a thickness of from about 1000 Angstroms to about 2000 Angstroms; carrying out a multi-step electrochemical deposition (ECD); and, carrying out a two step copper annealing process.

Abstract: A technique to form a structure with a rough topography in a planarized semiconductor process. The rough topography is formed by creating cored contacts. Subsequent process layers may be further stacked on top of the cored contacts in order to augment the nonplanar characteristics of the cored contacts. This rough topography structure may be used to align integrated circuits and wafers. An integrated circuit may be laser aligned using this alignment structure.

Abstract: There is disclosed a method of manufacturing a semiconductor device, wherein an Si3N4 film is formed as a mask member on the surface of a silicon substrate, then etched to form an STI trench. A solution of perhydrogenated silazane polymer is coated on the surface of the silicon substrate having an STI trench formed thereon to deposit a coated film (PSZ film) thereon. The PSZ film deposited on the mask member is removed, leaving part of the PSZ film inside the trench, wherein the thickness of the PSZ film is controlled to make the height thereof from the bottom of the STI trench become 600 nm or less. Thereafter, the PSZ film is heat-treated in a water vapor-containing atmosphere to convert the PSZ film into a silicon oxide film through a chemical reaction of the PSZ film. Subsequently, the silicon oxide film is heat-treated to densify the silicon oxide film.

Abstract: The invention is directed to a method of polishing a silicon-containing dielectric layer involving the use of a chemical-mechanical polishing system comprising (a) an inorganic abrasive, (b) a polishing additive, and (c) a liquid carrier, wherein the polishing composition has a pH of about 4 to about 6. The polishing additive comprises a functional group having a pKa of about 4 to about 9 and is selected from the group consisting of arylamines, aminoalcohols, aliphatic amines, heterocyclic amines, hydroxamic acids, aminocarboxylic acids, cyclic monocarboxylic acids, unsaturated monocarboxylic acids, substituted phenols, sulfonamides, thiols, salts thereof, and combinations thereof. The invention is further directed to the chemical-mechanical polishing system, wherein the inorganic abrasive is ceria.

Abstract: The present invention relates to a method of forming damascene pattern in a semiconductor device, and the method includes forming an insulating layer on a bottom wiring, forming via holes exposing a part of the bottom wiring by removing the insulating layer selectively, filling insides of the via holes to a prescribed thickness, forming an anti-reflection layer on the via holes and the insulating layer, forming a mask pattern for trench etching on the insulating layer on which the anti-reflection layer is formed, and forming a damascene pattern using the mask pattern for trench etching. CD uniformity is improved by minimizing change of the critical dimension of the damascene pattern, thereby increasing reliability of the semiconductor device.

Abstract: A method of manufacturing a semiconductor device includes the steps of forming a sunken section in an insulating film formed on a substrate and forming a barrier metal film on the insulating film inclusive of the sunken section. The method also includes forming a copper-based film over the entire surface so as to fill up the sunken section and forming a copper-based metal interconnection. The interconnection is formed by polishing this substrate surface by the chemical mechanical polishing method, using a polishing slurry containing a silica polishing material, an oxidizing agent, an amino acid, a triazole-based compound and water. A content ratio of the amino acid to the triazole-based compound (amino acid/triazole-based compound (weight ratio)) is 5 to 8.

Abstract: A method of post chemical mechanical polishing (CMP) cleaning to remove a CMP residue from a surface of an object is disclosed. The object is placed within a pressure chamber. The pressure chamber is pressurized. A supercritical carbon dioxide process is performed to remove a residual CMP residue from the surface of the object. The pressure chamber is vented.

Abstract: Disclosed is a CMP slurry comprising a first colloidal particle having a primary particle diameter ranging from 5 nm to 30 nm and an average particle diameter of d1, the first colloidal particle being incorporated in an amount of w1 by weight and a second colloidal particle having a primary particle diameter larger than that of the first colloidal particle and an average particle diameter of d2, the second colloidal particle being formed of the same material as that of the first colloidal particle and incorporated in an amount of w2 by weight, wherein d1, d2, w1 and w2 are selected to concurrently meet following conditions (A) and (B) excluding situations where d1, d2, w1 and w2 concurrently meet following conditions (C) and (D): 3?d2/d1?8??(A) 0.7?w1/(w1+w2)?0.97??(B) 3?d2/d1?5??(C) 0.7?w1/(w1+w2)?0.9.

Abstract: A buried film and a barrier film are polished together using a slurry in which the polishing rate on a substrate material (in particular, silicon oxide), that on a buried-film material (in particular, tungsten) and that on a barrier-film material (in particular, titanium oxide) are substantially equal to one another. This can materialize a buried structure free from any step or steps, at a high polishing rate.

Abstract: A polishing slurry for an aluminum-based metal includes an oxidizing agent having a standard electrode potential of 1.7 V or more, amino acid or amino acid compound, and bi- or higher than bi-valent aromatic carboxylic acid having a carbocycle or a heterocycle.

Abstract: A method for manufacturing a semiconductor device comprises: forming an N region and P region on a substrate, forming wiring so as to connect one or both of these N and P regions; and performing a processing step on a semiconductor substrate on which the upper surface of said wiring is exposed using a liquid, wherein said processing step is performed in a state in which the wavelength of light radiated onto said semiconductor substrate is 500 nm to less than 1 ?m, so that problems such as wiring connection defects for which there is the risk of occurring in the cleaning step are prevented by performing the cleaning step during, before or after a step that includes chemical mechanical polishing (CMP) for forming the above wiring.

Abstract: Disclosed is a method of manufacturing a semiconductor device. A gate electrode, which was formed through existing mask and etch processes, is formed by forming an oxide film protrusion on a field oxide film and forming the gate electrode between the oxide film protrusions. It is thus possible to minimize the critical dimension of the device, easily adjust the size of the device and form a uniform gate electrode over the wafer.

Abstract: A method and polishing system for planarizing a substrate having one or more materials formed thereon. The method generally includes positioning the substrate in proximity with a polishing pad, dispensing a polishing fluid to the polishing pad, the polishing fluid being subjected to carbonation prior to being dispensed to the polishing pad, and polishing the substrate. The polishing system generally includes a polishing platen having a polishing pad disposed thereon and in proximity to the substrate, a controller configured to cause the polishing pad to contact the substrate, and a polishing fluid delivery system to deliver a polishing fluid to the polishing pad, the polishing fluid delivery system including a carbonation system.

Abstract: A method of planarization allows for the use of chemical mechanical polishing (CMP) in starting structures having films not generally suitable for CMP processes. Two material layers are formed over a starting structure, and the upper layer is planarized in a CMP process. A nonselective etch is then used to transfer the planar topography to the lower level.

Abstract: A semiconductor chip formed on a substrate is provided. An oxygen-doped silicon carbide etch stop layer is formed over the substrate. An organosilicate glass layer is formed over the oxygen-doped silicon carbide etch stop layer. A feature is selectively etched in the organosilicate glass layer using an etch with an organosilicate glass to oxygen-doped silicon carbide selectivity greater than 5:1.

Abstract: According to one aspect of the invention, an improved process for preparing a surface of substrate is provided wherein the surface of the substrate is prepared for a chemical mechanical polishing (CMP) process, the CMP process is performed on the surface of the substrate, and the surface of the substrate is finished to clear the substrate surface of any active ingredients from the CMP process. Also, an improved substrate produced by the method is provided. According to one aspect of the invention, particular polishing materials and procedures may be used that allow for increased quality of AlN substrate surfaces.

Abstract: The present invention is a semiconductor wafer that enhances polish-stop endpointing in chemical-mechanical planarization processes. The semiconductor wafer has a substrate with a device feature formed on the substrate, a stratum of low friction material positioned over the substrate, and an upper layer deposited on the low friction material stratum. The low friction stratum has a polish-stop surface positioned at a level substantially proximate to a desired endpoint of the chemical-mechanical planarization process. The upper layer, which is made from either a conductive material or an insulative material, has a higher polishing rate than that of the low friction stratum. In operation, the low friction stratum resists chemical-mechanical planarization with either hard or soft polishing pads to stop the planarization process at the desired endpoint.