Abstract: A substrate processing apparatus includes a rotary table configured to move each of multiple substrate chucks to, in sequence, a carry-in position where a carry-in of a substrate is performed, a processing position where thinning of the substrate is performed, and a carry-out position where a carry-out of the substrate is performed; a tilt angle adjusting device configured to adjust a tilt angle of the substrate chuck with respect to the rotary table at the processing position; and a tilt angle controller configured to control the tilt angle adjusting device based on a measurement result of a plate thickness measuring device. The plate thickness measuring device measures a plate thickness of the substrate at the carry-out position.

Abstract: A method and apparatus for insitu adjustment of wafer slip detection during work piece polishing are disclosure. In one aspect, a chemical mechanical planarization (CMP) system, includes: a carrier configured to retain a substrate, a platen supporting a polishing pad, and a slip sensor configured to generate a signal indicative of a characteristic of a surface of the polishing pad. The system further includes a processor configured to: receive the signal from the slip sensor, calibrate a steady-state value of the signal when the CMP system is in a steady-state condition, compare the signal received from the slip sensor to the calibrated steady-state value during CMP polishing, and detect wafer slip in response to the signal received from the slip sensor during the CMP polishing differing from the calibrated steady-state value by more than a threshold value.

Abstract: A polishing composition, includes an abrasive; a pH adjuster; a barrier film removal rate enhancer; a low-k removal rate inhibitor; an azole-containing corrosion inhibitor; and a ruthenium removal rate enhancer. A method of polishing a substrate includes the steps of: applying the polishing composition described herein to a surface of a substrate, wherein the surface comprises ruthenium or a hard mask material; and bringing a pad into contact with the surface of the substrate and moving the pad in relation to the substrate.

Abstract: A method for manufacturing a semiconductor structure includes: forming multiple trenches spaced apart from each other and extending in a first direction in a substrate, and forming a first insulating layer on sidewalls and bottoms of the trenches; forming a first conductive layer on a surface of the first insulating layer; removing part of the first conductive layer to an initial depth by a first etching process; removing remaining part of the first conductive layer to a target depth by a second etching process.

Abstract: A polishing liquid includes abrasive grains containing at least one selected from the group consisting of cerium oxide and silicon oxide; a nitrogen-containing compound; and water. The nitrogen-containing compound contains nicotinamide. A polishing liquid set includes constituent components of a polishing liquid stored while being divided into a first liquid and a second liquid. A polishing method includes a step of polishing a surface to be polished by using a polishing liquid.

Abstract: A slurry composition, a polishing method and an integrated circuit are provided. The slurry composition includes a slurry and at least one cationic surfactant having at least one nitrogen atom in the molecule. The slurry includes at least one liquid carrier, at least one abrasive and at least one pH adjusting agent, and has a pH of less than 7.0. The polishing method includes using the slurry composition with the cationic surfactant to polish a conductive layer. The integrated circuit comprises a block layer comprising the cationic surfactant between a sidewall of the conductive plug and an interlayer dielectric layer.

Abstract: The presently claimed invention relates to a chemical-mechanical polishing (CMP) composition and chemical-mechanical polishing (CMP) methods. The presently claimed invention particularly relates to a composition and process for chemical-mechanical polishing of substrates containing copper and ruthenium, specifically, semiconductor substrates containing copper and ruthenium.

Abstract: Various back end of line (BEOL) layer formation techniques described herein enable reduced contact resistance, reduced surface roughness, and/or increased semiconductor device performance for BEOL layers such as interconnects and/or metallization layers.

Abstract: A semiconductor device has a semiconductor die. A first dielectric layer is formed over the semiconductor die. A second dielectric layer is formed over the first dielectric layer. A trench is formed in the second dielectric layer. A via opening is formed to expose a contact pad of the semiconductor die within the trench. A seed layer is formed over the second dielectric layer. The seed layer extends into the trench and via opening. A conductive material is deposited into the via opening and trench. The conductive material is overburdened from the trench. The seed layer around the conductive material is etched in a first etching step. The conductive material is etched in a second etching step.

Abstract: A slurry blending tool may include a blending tank to receive and blend one or more materials into a slurry, and at least one inlet pipe connected to the blending tank and to provide the one or more materials to the blending tank. The at least one inlet pipe may vertically enter the blending tank and may not contact the blending tank. The slurry blending tool may include a blending pump partially provided within the blending tank and to blend the one or more materials into the slurry. The slurry blending tool may include an outlet pipe connected to the blending pump and to remove the slurry from the blending tank.

Abstract: A method of fabricating a semiconductor device is described. A semiconductor substrate having at least one electrical component is provided. A patterned wiring layer is formed above the semiconductor substrate. The patterned wiring layer includes a plurality of wiring portions, where adjacent of the wiring portions are separated from each other. A first insulating passivation layer is formed over the wiring portions in a region between adjacent wiring portions. The first insulating passivation layer has a horizontal surface in the region between adjacent wiring portions. A second insulating passivation layer is formed on the first insulating passivation layer, wherein the first insulating passivation layer has a side surface which makes an angle with the horizontal surface of greater than 103°.

Abstract: A microelectronic device including a substrate having a semiconductor material containing an embedded thermoelectric cooler with thermally anisotropic mesas between the cold terminal and the hot terminal of the embedded thermoelectric cooler adjacent to a heat source; the adjacent embedded thermoelectric cooler providing a temperature reduction for the heat source resulting in increased safe operating area (SOA) for the microelectronic device. The thermally anisotropic mesas are formed in parallel with deep trenches used as isolation in the microelectronic device.

Abstract: This disclosure relates to polishing compositions that include (1) at least one abrasive; (2) at least one organic acid or a salt thereof; (3) at least one first amine compound, the at least one first amine compound including an alkylamine having a 6-24 carbon alkyl chain; (4) at least one second amine compound containing at least two nitrogen atoms, the second amine compound being different from the first amine compound; and (5) an aqueous solvent.

Abstract: In an embodiment, a chemical mechanical planarization (CMP) system includes: a monolithic platen within a platen housing, wherein the monolithic platen is formed of a single piece of material, wherein the monolithic platen includes: a first portion within a first opening, and a second portion within a second opening, wherein the first portion has a different diameter than the second portion; and a polishing fluid delivery module above the monolithic platen, wherein the polishing fluid delivery module is configured to deliver slurry to the monolithic platen during performance of CMP.

Abstract: A slurry composition, a polishing method and an integrated circuit are provided. The slurry composition includes a slurry and at least one rheology modifier. The slurry includes at least one liquid carrier, at least one abrasives and at least one oxidizer. The rheology modifier is dispensed in the slurry. The polishing method includes using the slurry composition with the rheology modifier to polish a conductive layer.

Abstract: Provided is a powder coating device including a powder fluidization tank including a bottom member having a plurality of spacers interposed between a first plate member and a second plate member, a fixing member to which the powder fluidization tank is fixed, a coupling support member coupling and supporting the first plate member to the fixing member, and a vibration mechanism coupled to the first plate member, wherein the coupling support member includes an elastic member.

Abstract: An aqueous alkaline chemical mechanical polishing composition includes a quaternary ammonium compound having a phenyl group which enables enhanced reduction of defects on silicon oxide substrates and enables good silicon oxide removal rates during chemical mechanical polishing.

Abstract: A semiconductor structure includes a substrate including a first surface; a dielectric layer disposed over the first surface of the substrate; a first conductive line surrounded by the dielectric layer and extended over the first surface of the substrate; a second conductive line disposed adjacent to the first conductive line, surrounded by the dielectric layer and extended parallel to the first conductive line; a conductive via disposed over the first conductive line and extended through the dielectric layer; and a cross section of the conductive via substantially parallel to the first surface of the substrate, wherein the cross section of the conductive via is at least partially protruded from the first conductive line towards the second conductive line. Further, a method of manufacturing the semiconductor structure is also disclosed.

Abstract: There is provided a method for manufacturing a structure, including: applying a first etching to a surface of a member, at least the surface being composed of Group III nitride; and applying a second etching to the surface to which the first etching has been applied, wherein in applying the first etching, a flat portion and a protruding portion are formed, the flat portion being newly appeared on the surface by etching, and the protruding portion being raised with respect to the flat portion, which is caused by being less likely to be etched than the flat portion, and in applying the second etching, the protruding portion is lowered by etching the protruding portion.

Abstract: The invention provides a chemical-mechanical polishing composition comprising (a) an abrasive comprising ceria particles, (b) a cationic polymer selected from a cationic homopolymer, a cationic copolymer comprising at least one cationic monomer and at least one nonionic monomer, and a combination thereof, (c) a quaternary ammonium salt or a quaternary phosphonium salt, and (d) water, wherein the polishing composition has a pH of about 5 to about 8. The invention also provides a method of chemically-mechanically polishing a substrate, especially a substrate comprising silicon oxide, silicon nitride and/or polysilicon by contacting the substrate with the inventive chemical-mechanical polishing composition.

Abstract: An electronic substrate may be fabricated having at least two glass layers separated by an etch stop layer, wherein a bridge is embedded within one of the glass layers. The depth of a cavity formed for embedding the bridge is control by the thickness of the glass layer rather than by controlling the etching process used to form the cavity, which allows for greater precision in the fabrication of the electronic substrate. In an embodiment of the present description, an integrated circuit package may be formed with the electronic substrate, wherein at least two integrated circuit devices may be attached to the electronic substrate, such that the bridge provides device-to-device interconnection between the at least two integrated circuit devices. In a further embodiment, the integrated circuit package may be electrically attached to an electronic board.

Abstract: A method of planarizing a device having a surface topography with at least one material at a surface of the device is described. The method comprises the steps of depositing a stop layer over at least a portion of the at least one material which substantially retains the surface topography of the device. A sacrificial layer is deposited over at least a portion of the stop layer. A planarization process is performed on the device. The planarization process includes the steps of performing a chemical mechanical polish (CMP) on the top surface of the sacrificial layer. A physical removal step is conducted on the remainder portion of the sacrificial layer to form a planarized surface. A second CMP step and a second physical removal step are conducted, to form a planarized device.

Abstract: The present disclosure describes an apparatus and a method to detect a polishing pad profile during a polish process and adjust the polishing process based on the detected profile. The apparatus can include a polishing pad configured to polishing a substrate, a substrate carrier configured to hold the substrate against the polishing pad, and a detection module configured to detect a profile of the polishing pad. The detection module can include a probe configured to measure a thickness of one or more areas on the polishing pad, and a beam configured to support the probe, where the probe can be further configured to move along the beam.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first metal layer over a substrate, forming a dielectric layer over the first metal layer. The method includes forming a trench in the dielectric layer, and performing a surface treatment process on a sidewall surface of the trench to form a hydrophobic layer. The hydrophobic layer is formed on a sidewall surface of the dielectric layer. The method further includes depositing a metal material in the trench and over the hydrophobic layer to form a via structure.

Abstract: An object of the invention is to provide a cleaning liquid for semiconductor substrates having undergone a chemical mechanical polishing process, the cleaning liquid being excellent in corrosion prevention properties and defect suppression performance with respect to a metal film. Another object of the invention is to provide a method of cleaning semiconductor substrates having undergone a chemical mechanical polishing process. A cleaning liquid of the invention is used for semiconductor substrates having undergone a chemical mechanical polishing process and includes: an amine oxide compound that is a compound having an amine oxide group, or its salt; and at least one hydroxylamine compound selected from the group consisting of a hydroxylamine, a hydroxylamine derivative, and their salts, and the amine oxide compound content is 0.00001 to 0.15 mass % based on the total mass of the cleaning liquid.

Abstract: Shallow Trench Isolation (STI) chemical mechanical planarization (CMP) polishing compositions, methods and systems of use therefore are provided. The CMP polishing composition comprises abrasives of ceria coated inorganic oxide particles, such as ceria-coated silica; and dual chemical additives for providing the tunable oxide film removal rates and tunable SiN film removal rates; low oxide trench dishing, and high oxide: SiN selectivity. Dual chemical additives comprise at least one silicone-containing compound comprising at least one of (1) ethylene oxide and propylene oxide (EO-PO) group, and at least one of substituted ethylene diamine group on the same molecule; and (2) at least one non-ionic organic molecule having at least two, preferably at least four hydroxyl functional groups.

Abstract: Methods for forming a topographically selective silicon oxide film by a cyclical plasma-enhanced deposition process are provided. The methods may include: forming a topographically selective silicon oxide film by a plasma enhanced atomic layer deposition (PEALD) process or a cyclical plasma-enhanced chemical vapor deposition (cyclical PECVD) process. The methods may also include: forming a silicon oxide film either selectivity over the horizontal surfaces of a non-planar substrate or selectively over the vertical surfaces of a non-planar substrate.

Abstract: A ruthenium film forming method includes: causing chlorine to be adsorbed to an upper portion of a recess at a higher density than to a lower portion of the recess by supplying a chlorine-containing gas to a substrate including an insulating film and having the recess; and forming a ruthenium film in the recess by supplying a Ru-containing precursor to the recess to which the chlorine is adsorbed.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a gate structure over the substrate. The semiconductor device structure also includes a spacer element covering a first sidewall of the gate structure. The semiconductor device structure further includes a source/drain portion in the substrate, and the spacer element is between the source/drain portion and the gate structure. In addition, the semiconductor device structure includes an etch stop layer covering the source/drain portion. The etch stop layer includes a first nitride layer covering the source/drain portion and having a second sidewall, and the second sidewall is in direct contact with the spacer element. The etch stop layer also includes a first silicon layer covering the first nitride layer and having a third sidewall, and the third sidewall is in direct contact with the spacer element.

Abstract: A substrate processing apparatus includes a chamber, a holding unit, a hydrophobizing agent nozzle, a first organic solvent nozzle, a second organic solvent nozzle, and an exhaust port. The chamber has a gastight space that is capable of accommodating the plurality of substrates. The holding unit lifts or lowers the plurality of substrates between a storage area where a liquid is stored in the gastight space and a drying area that is located above the storage area in the gastight space. The hydrophobizing agent nozzle supplies a vapor of a hydrophobizing agent to the drying area. The first organic solvent nozzle supplies an organic solvent from the drying area to the storage area. The second organic solvent nozzle supplies a vapor of an organic solvent to the drying area. The exhaust port discharges a gas in the gastight space.

Abstract: A polishing slurry composition is provided. The polishing slurry composition includes polishing particles, a first polishing inhibitor containing a hydrophobic amino acid, and a second polishing inhibitor containing a cyclic polymer, and the first polishing inhibitor and the second polishing inhibitor are different.

Abstract: A method of forming a memory device having magnetic tracks individually comprising a plurality of magnetic domains having domain walls, includes forming an elevationally outer substrate material of uniform chemical composition. The uniform composition material is partially etched into to form alternating regions of elevational depressions and elevational protrusions in the uniform composition material. A plurality of magnetic tracks is formed over and which angle relative to the alternating regions. Interfaces of immediately adjacent of the regions individually form a domain wall pinning site in individual of the magnetic tracks. Other methods, including memory devices independent of method, are disclosed.

Abstract: A manufacturing method for a semiconductor structure includes: patterning and etching a semiconductor substrate to form a concave region; forming a first protective layer on a surface of the semiconductor substrate, the surface of the semiconductor substrate being a surface of a non-etched region except the concave region; forming an isolation structure in the concave region; and removing the first protective layer on the surface of the semiconductor substrate.

Abstract: A curable composition on a substrate is cured in a state where a member is in contact with the curable composition. Thereafter, the member having adhered to the curable composition is separated from the substrate, whereby the curable composition and a particle are removed from the substrate.

Abstract: A binding capacity evaluation apparatus includes a first solution tank into which a first solution is input, the first solution including a hydrophobic substance and a hydrophilic substance; a second solution tank into which a second solution is input, the second solution including water as a major component; a light irradiation device irradiating light on a third solution including a mixture of the first and second solutions; a light-receiving device receiving light passing through the third solution; and a light transmittance measuring device measuring light transmittance by using an intensity of the light received by the light-receiving device. The apparatus uses the light transmittance to detect when the hydrophobic substance becomes supersaturated in the second solution.

Abstract: Provided is a polishing composition for semiconductor wiring providing an excellent polishing rate and preventing occurrence of dishing. The polishing composition for semiconductor wiring according to the present invention contains a compound represented by Formula (1) below: R1O—(C3H6O2)n—H??(1) where R1 represents a hydrogen atom, a hydrocarbon group that has from 1 to 24 carbon atoms and may include a hydroxyl group, or a group represented by R2CO, where the R2 represents a hydrocarbon group having from 1 to 24 carbon atoms; and n represents an average degree of polymerization of glycerol units shown in the parentheses and is from 2 to 60.

Abstract: Embodiments herein include carrier loading stations and methods related thereto which may be used to beneficially remove nano-scale and/or micron-scale particles adhered to a bevel edge of a substrate before polishing of the substrate. By removing such contaminates, e.g., loosely adhered particles of dielectric material, from the bevel edge, contamination of the polishing interface can be avoided thus preventing and/or substantially reducing scratch related defectivity associated therewith.

Abstract: A CMP slurry composition for polishing a tungsten pattern wafer and a method of polishing a tungsten pattern wafer, the CMP slurry composition including a solvent, the solvent being a polar solvent or a non-polar solvent; an abrasive agent; and a biocide, wherein the abrasive agent includes silica modified with a silane containing two nitrogen atoms or silica modified with a silane containing three nitrogen atoms, the biocide includes a compound of Formula 3:

Abstract: An interconnect structure is formed on a substrate in a semiconductor device. The interconnect structure includes a dielectric layer and a metal layer. The dielectric layer includes a region and a plurality of protrusions. The metal layer is disposed on the region and between the protrusions, wherein tops of the protrusions are exposed with respect to the metal layer. In a top view of the semiconductor device, the protrusions are distributed in the region. Any straight path crossing through a central region of the region is always intersected with a portion of the protrusions.

Abstract: A polishing slurry is disclosed which includes about 0.01 wt % to about 10 wt % of polishing particles, about 0.005 wt % to about 0.1 wt % of a dispersing agent, about 0.001 wt % to about 1 wt % of an oxide-polishing promoter including a pyridine compound, about 0.05 wt % to about 0.1 wt % of a nitride-polishing inhibitor including an amino acid or an anionic organic acid, and water. A method for manufacturing a display device including an active pattern disposed on a base substrate, a gate metal pattern including a gate electrode overlapping the active pattern, a planarized insulation layer disposed on the gate metal pattern, and a source metal pattern disposed on the planarized insulation layer is also disclosed.

Abstract: An imaging device includes a photoelectric conversion layer, a counter electrode provided above the photoelectric conversion layer, a pixel electrode that faces the counter electrode with the photoelectric conversion layer disposed between the counter electrode and the pixel electrode, and a contact plug covered with the pixel electrode and connected to the pixel electrode. The pixel electrode includes a first layer and a second layer provided on the first layer in contact with the first layer. A surface of the first layer that is in contact with the second layer has a protrusion that protrudes upward.

Abstract: The present disclosure relates to a method and apparatus for cleaning a substrate. The method includes rotating a substrate disposed on a substrate support and spraying a front side of the substrate using steam through a front side nozzle assembly. A back side of the substrate is sprayed using steam through a back side dispenser assembly. A heated chemical is dispensed over the front side of the substrate.

Abstract: The present application provides a detection method of metal impurity in wafer. The method comprises conducting a medium temperature thermal treatment for a first predicted time period to the wafer, cooling the wafer and conducting a low temperature thermal treatment for a second predicted time period, cooling the wafer to ambient temperature; providing a liquid of vapor phase decomposition on the wafer to collect metal impurities; atomizing the liquid containing the collected metal impurities, conducting an inductively coupled plasma mass spectrometry analysis and obtaining concentrations of the metal impurities. The present application applies the combination of various thermal treatment without an interrupt of cooling to ambient temperature to contemplate diffusions of various metal impurities to the wafer surface. Accordingly, the detection of metal impurities can be conducted with reduced time cost and enhanced efficiency.

Abstract: A semiconductor wafer dicing process is disclosed for dicing a wafer into individual dies, each die comprising one integrated circuit. The process comprises: disposing a coating upon the wafer; removing at least a portion of the coating to expose regions of the wafer, along which the wafer is to be diced, to form a workpiece; disposing the workpiece upon a platen within a processing chamber; plasma treating the workpiece with a set of plasma treatment conditions to etch a portion of the exposed regions of the wafer to form a wafer groove which extends laterally beneath the coating to form an undercut; and plasma etching the workpiece with a set of plasma etch conditions, which are different to the plasma treatment conditions, to etch through the wafer and dice the wafer along the wafer groove.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a wafer structure. The wafer structure has a normal region and a trimmed region adjacent to the normal region. A top surface of the trimmed region is lower than a top surface of the normal region. The semiconductor structure includes a dielectric layer and a conductive layer disposed on the wafer structure in the normal region and the trimmed region. The semiconductor structure includes a protective layer disposed on a portion of the dielectric layer in the trimmed region and a portion of the conductive layer in the trimmed region. The semiconductor structure includes another dielectric layer disposed on a portion of the dielectric layer in the normal region and a portion of the conductive layer in the normal region and on the protective layer.

Abstract: A method includes bonding a front side surface of a first wafer to a second wafer; performing a multi-trimming process on the first and second wafers from a back side surface of the first wafer, the multi-trimming process comprising: performing a first trimming step from the back side surface of the first wafer to cut through a periphery of the first wafer; performing a second trimming step on the second wafer to partially cut a periphery of the second wafer to form a first step-like structure; and performing a third trimming step on the second wafer to partially cut the periphery of the second wafer to form a second step-like structure connecting down from the first step-like structure; after performing the multi-trimming process, forming a coating material at least over the periphery of the second wafer.

Abstract: A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view.

Abstract: A method for manufacturing a semiconductor device is provided, including: preparing a first chip forming portion having a first semiconductor substrate, first metal pads provided at the substrate and a first circuit electrically connected to at least a part of the pads, and a second chip forming portion having a second semiconductor substrate, second metal pads provided at substrate and a second circuit electrically connected to at least a part of the pads; bonding the first and the second chip forming portions while joining the first and the second pads to form a bonding substrate having a non-bonded region between the first and the second chip forming portions at an outer peripheral portion thereof; and filling an insulating film into the non-bonded region, at least a part of the insulating film containing at least one selected from the group consisting of silicon nitride and nitrogen-containing silicon carbide.

Abstract: A method for manufacturing a structure, including photoelectrochemically etching an etching object, the photoelectrochemical etching of the etching object including: injecting an alkaline or acidic etching solution containing an oxidizing agent that receives electrons, into a rotatably held container in which an etching object at least whose surface is composed of group III nitride is held, and immersing the surface in the etching solution; irradiating the surface of the etching object held in the container with light in a stationary state of the etching object and the etching solution; and rotating the container to scatter the etching solution toward an outer peripheral side, thereby discharging the etching solution from the container, after the surface is irradiated with the light.

Abstract: A multilayer interconnect structure is formed by, providing a substrate having thereon a first dielectric for supporting a multi-layer interconnection having lower conductor MN, upper conductor MN+1, dielectric interlayer (DIL) and interconnecting via conductor VN+1/N. The lower conductor MN has a first upper surface located in a recess below a second upper surface of the first dielectric. The DIL is formed above the first and second surfaces. A cavity is etched through the DIL from a desired location of the upper conductor MN+1, exposing the first surface. The cavity is filled with a further electrical conductor to form the upper conductor MN+1 and the connecting via conductor VN+1/N making electrical contact with the first upper surface. A critical dimension between others of lower conductors MN and the via conductor VN+1/N is lengthened. Leakage current and electro-migration therebetween are reduced.