Simultaneous (e.g., Chemical-mechanical Polishing, Etc.) Patents (Class 438/692)
  • Patent number: 12014951
    Abstract: A method of manufacturing a semi-damascene structure of a semiconductor device includes: forming a 1st intermetal dielectric layer; forming a 1st hardmask layer and at least one 1st photoresist pattern on the 1st intermetal dielectric layer; patterning at least one via hole penetrating through the 1st hardmask layer and the 1st intermetal dielectric using the 1st photoresist pattern; removing the 1st photoresist pattern among the 1st photoresist pattern and the 1st hardmask layer; forming a metal structure in the via hole such that the metal structure fills in the vial hole and extends on the 1st hardmask layer; patterning the metal structure to form at least one 1st trench penetrating at least the metal structure at a portion where the metal structure extends on the 1st hardmask layer; and filling the 1st trench with a 2nd inter-metal layer.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: June 18, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hoonseok Seo, Euibok Lee, Taeyong Bae
  • Patent number: 12009393
    Abstract: A tunnel field effect transistor includes a constant current formation layer, a source region and a drain region provided on the constant current formation layer, a channel layer provided between the source region and the drain region, a gate electrode provided on the channel layer, and a gate insulating film provided between the gate electrode and the channel layer, wherein the source region and the drain region have different conductivity types, and the constant current formation layer forms a constant current between the drain region and the constant current formation layer.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: June 11, 2024
    Assignee: UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)
    Inventors: Kyung Rok Kim, Ji Won Chang, Jae Won Jeong, Youngeun Choi, Wooseok Kim
  • Patent number: 12009222
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The method includes forming a stop layer over the first layer. The method includes forming a second layer over the stop layer. The second layer is in direct contact with the stop layer. The method includes partially removing the second layer. The method includes performing an etching process to partially remove the stop layer and an upper portion of the first layer, wherein protrusion structures are formed over a lower portion of the first layer after the etching process, and the protrusion structures include the stop layer and the upper portion of the first layer remaining after the etching process. The method includes removing the protrusion structures.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Chen Wei, Chun-Chieh Chan, Chun-Jui Chu, Jen-Chieh Lai, Shih-Ho Lin
  • Patent number: 11999876
    Abstract: The compositions of the present disclosure polish surfaces or substrates that at least partially include ruthenium. The composition includes a synergistic combination of ammonia and oxygenated halogen compound. The composition may further include abrasive and acid(s). A polishing composition for use on ruthenium materials may include ammonia, present in an amount of 0.01 wt % to 10 wt %, based on the total weight of the composition; hydrogen periodate, present in an amount of 0.01 wt % to 10 wt %, based on the total weight of the composition; silica, present in an amount of 0.01 wt % to 12 wt %, based on the total weight of the composition; and organic sulfonic acid, present in an amount of 0.01 wt % to 10 wt %, based on the total weight of the composition, wherein the pH of the composition is between 6 and 8.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: June 4, 2024
    Assignee: FUJIFILM ELECTRONIC MATERIALS U.S.A., INC.
    Inventors: David (Tawei) Lin, Bin Hu, Liqing (Richard) Wen, Yannan Liang, Ting-Kai Huang
  • Patent number: 12002684
    Abstract: A method for CMP includes following operations. A metal stack is received. The metal layer stack includes at least a first metal layer and a second metal layer, and a top surface of the first metal layer and a top surface of the second metal layer are exposed. A protecting layer is formed over the second metal layer. A portion of the first metal layer is etched. The protecting layer protects the second metal layer during the etching of the portion of the first metal layer. A top surface of the etched first metal layer is lower than a top surface of the protecting layer. The protecting layer is removed from the second metal layer.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ji Cui, Fu-Ming Huang, Ting-Kui Chang, Tang-Kuei Chang, Chun-Chieh Lin, Wei-Wei Liang, Liang-Guang Chen, Kei-Wei Chen, Hung Yen, Ting-Hsun Chang, Chi-Hsiang Shen, Li-Chieh Wu, Chi-Jen Liu
  • Patent number: 11996330
    Abstract: There is provided a method for manufacturing a SiC device wafer comprising the steps: a) slicing and polishing a SiC boule to thicker substrates compared to the usual thickness in the prior art, b) creating a device wafer on the substrate, c) removing the device wafer from the remaining substrate, d) adding SiC to the remaining substrate so that the original thickness of the substrate is essentially restored, and repeating steps b)-d). The removal of the device wafer can be made for instance by laser slicing. Advantages include that the SiC material loss is significantly decreased and the boule material used for device wafers is considerably increased, the substrates become more stable especially during high temperature processes, the warp and bow is reduced, the risk of breakage is decreased.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: May 28, 2024
    Assignee: II-VI ADVANCED MATERIALS, LLC
    Inventors: Adolf Schöner, Sergey Reshanov
  • Patent number: 11990410
    Abstract: A technique relates to an integrated circuit (IC). The IC includes a conductive line formed on a conductive via, the conductive line being formed though a dielectric material. The IC includes an etch stop layer having one or more extended portions intervening between one or more edge portions of the conductive line and the conductive via, the one or more edge portions being at a periphery of the conductive line and the conductive via, the etch stop layer including a higher dielectric breakdown than the dielectric material. The one or more extended portions of the etch stop layer cause the conductive line to be formed with a bottom part having a reduced dimension than an upper part of the conductive line.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: May 21, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent Anderson, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Christopher J. Penny, Kisik Choi, Robert Robison
  • Patent number: 11986926
    Abstract: An apparatus for chemical mechanical polishing includes a rotatable platen having a surface to support a polishing pad, a carrier head to hold a substrate in contact with the polishing pad, and a polishing liquid distribution system. The polishing liquid distribution system includes a dispenser positioned to deliver a polishing liquid to a portion of a polishing surface of the polishing pad, and a curved barrier positioned after the dispenser to spread fresh polishing liquid from the dispenser.
    Type: Grant
    Filed: August 26, 2022
    Date of Patent: May 21, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Yen-Chu Yang, Stephen Jew, Jianshe Tang, Haosheng Wu, Shou-Sung Chang, Paul D. Butterfield, Alexander John Fisher, Bum Jick Kim
  • Patent number: 11986920
    Abstract: According to one embodiment, a polishing method includes supplying a polishing agent to be between a polishing pad and to-be-polished surface, then polishing the to-be-polished surface with the polishing agent while rotating at least one of the to-be-polished surface and the polishing pad. The polishing agent includes abrasive grains and an organic polymer. The organic polymer makes a reversible phase transition between a gel state and a sol state depending on temperature.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: May 21, 2024
    Assignee: Kioxia Corporation
    Inventors: Mikiya Sakashita, Yumiko Kataoka, Yukiteru Matsui
  • Patent number: 11990339
    Abstract: A semiconductor device and method of manufacture are provided. After a patterning of a middle layer, the middle layer is removed. In order to reduce or prevent damage to other underlying layers exposed by the patterning of the middle layer and intervening layers, an inhibitor is included within an etching process in order to inhibit the amount of material removed from the underlying layers.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jian-Jou Lian, Yao-Wen Hsu, Neng-Jye Yang, Li-Min Chen, Chia-Wei Wu, Kuan-Lin Chen, Kuo Bin Huang
  • Patent number: 11980993
    Abstract: A method of grinding a workpiece includes a first grinding step of adjusting the relative tilt of a chuck table and a grinding wheel to a first state and bringing grindstones into abrasive contact with the workpiece to grind the workpiece, and a second grinding step of adjusting the relative tilt of the chuck table and the grinding wheel to a second state that is different from the first state and bringing the grindstones into abrasive contact with the workpiece to grind the workpiece. In the second grinding step, the workpiece is ground under a condition for causing the workpiece to have a smaller surface roughness than that in the first grinding step.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: May 14, 2024
    Assignee: DISCO CORPORATION
    Inventor: Yoshikazu Suzuki
  • Patent number: 11981833
    Abstract: Provided is a polishing composition for semiconductor wiring providing an excellent polishing rate and preventing occurrence of dishing. The polishing composition for semiconductor wiring according to the present invention contains a compound represented by Formula (1) below: R1O—(C3H6O2)n—H??(1) where R1 represents a hydrogen atom, a hydrocarbon group that has from 1 to 24 carbon atoms and may include a hydroxyl group, or a group represented by R2CO, where the R2 represents a hydrocarbon group having from 1 to 24 carbon atoms; and n represents an average degree of polymerization of glycerol units shown in the parentheses and is from 2 to 60.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: May 14, 2024
    Assignee: DAICEL CORPORATION
    Inventor: Yuichi Sakanishi
  • Patent number: 11969917
    Abstract: A silicon carbide wafer manufacturing method includes: a bending measuring step of measuring a first edge having the greatest degree of a bending at one surface of a silicon carbide ingot having one surface; a cutting start step of starting a cutting at a second edge having a distance of r×a along an edge of the one surface from the first edge in a direction parallel to or with a predetermined off angle with respect to the one surface through the wire saw, a cutting speed being decreased to a first cutting speed in the cutting start step; a cutting proceeding step in which the first cutting speed is substantially constant within a variation of about ±5% of the first cutting speed; and a finish step in which the cutting speed is increased from the first cutting speed and the cutting of the silicon carbide ingot is completed.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: April 30, 2024
    Assignee: SENIC Inc.
    Inventors: Jung-Gyu Kim, Kap-Ryeol Ku, Jung Doo Seo, Jung Woo Choi, Jong Hwi Park
  • Patent number: 11951587
    Abstract: The present disclosure is directed to techniques of zone-based target control in chemical mechanical polishing of wafers. Multiple zones are identified on a surface of a wafer. The CMP target is achieved on each zone in a sequence of CMP processes. Each CMP process in the sequence achieves the CMP target for only one zone, using a CMP process selective to other zones.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Liang Chung, Che-Hao Tu, Kei-Wei Chen, Chih-Wen Liu
  • Patent number: 11931853
    Abstract: Generating a recipe for controlling a polishing system includes receiving a target removal profile that includes a target thickness to remove for a plurality of locations on a substrate that are angularly distributed around the substrate, and storing a first function defining a polishing rate for a zone from a plurality of pressurizable zones of a carrier head that are angularly distributed around a the carrier head. The first function defines polishing rates as a function of pressures. For each particular zone of the plurality of zones a recipe defining a pressure for the particular zone over time is calculated by calculating an expected thickness profile after polishing using the first function, and minimizing a cost function that incorporates a first term representing a difference between the expected thickness profile and a target thickness profile.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: March 19, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Eric Lau, Charles C. Garretson, Huanbo Zhang, Zhize Zhu, Benjamin Cherian, Brian J. Brown, Thomas H. Osterheld
  • Patent number: 11929257
    Abstract: Described herein are etching solutions and method of using the etching solutions suitable for etching aluminum nitride (AlN) from a semiconductor substrate during the manufacture of a semiconductor device comprising AlN and silicon material without harming the silicon material. The etching solution comprises a cationic surfactant, water, a base, and a water-miscible organic solvent.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: March 12, 2024
    Assignee: Versum Materials US, LLC
    Inventors: Chung Yi Chang, Wen Dar Liu, Yi-Chia Lee
  • Patent number: 11930639
    Abstract: A three-dimensional semiconductor memory device may include horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other, memory structures provided on the horizontal patterns, respectively, each of the memory structures including a three-dimensional arrangement of memory cells. Penetrating insulating patterns and separation structures may isolate the horizontal patterns from one another. Through vias may extend through the penetrating insulating patterns to connect logic circuits of the peripheral circuit structure to the memory structure.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: March 12, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Woosung Yang, Dong-Sik Lee, Sung-Min Hwang, Joon-Sung Lim
  • Patent number: 11923233
    Abstract: Apparatus and methods for providing backside pressure control and edge purge gas to a substrate in a processing chamber. A seal band within a pocket of a substrate support defines an inner pocket region and an outer pocket region. The seal band has a pressure dependent controlled leakage rate so that a backside gas flow to the inner pocket region can diffuse through the seal band to the outer pocket region to create an edge purge while providing backside pressure to the substrate. Processing chambers, methods of processing a substrate and non-transitory computer-readable medium containing instructions to process a substrate are also disclosed.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: March 5, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Joseph AuBuchon, Tejas Ulavi
  • Patent number: 11919120
    Abstract: A polishing system includes a platen having a top surface to support a main polishing pad. The platen is rotatable about an axis of rotation that passes through approximately the center of the platen. An annular flange projects radially outward from the platen to support an outer polishing pad. The annular flange has an inner edge secured to and rotatable with the platen and vertically fixed relative to the top surface of the platen. The annular flange is vertically deflectable such that an outer edge of the annular flange is vertically moveable relative to the inner edge. An actuator applies pressure to an underside of the annular flange in an angularly limited region, and a carrier head holds a substrate in contact with the polishing pad and is movable to selectively position a portion of the substrate over the outer polishing pad.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: March 5, 2024
    Assignee: Applied Materials, Inc.
    Inventors: David J. Lischka, Jay Gurusamy, Danielle Loi, Steven M. Zuniga
  • Patent number: 11922058
    Abstract: Embodiments of a three-dimensional (3D) memory device and a method of operating the 3D memory device are provided. The 3D memory device includes an array of 3D NAND memory cells, an array of static random-access memory (SRAM) cells, and a peripheral circuit. The array of SRAM cells and the peripheral circuit arranged at one side are bonded with the array of 3D NAND memory cells at another side to form a chip. Data is received from a host through the peripheral circuit, buffered in the array of SRAM cells, and transmitted from the array of SRAM cells to the array of 3D NAND memory cells. The data is programmed into the array of 3D NAND memory cells.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: March 5, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Yue Ping Li, Wei Jun Wan, Chun Yuan Hou
  • Patent number: 11919126
    Abstract: In an embodiment, a chemical mechanical planarization (CMP) system includes: a monolithic platen within a platen housing, wherein the monolithic platen is formed of a single piece of material, wherein the monolithic platen includes: a first portion within a first opening, and a second portion within a second opening, wherein the first portion has a different diameter than the second portion; and a polishing fluid delivery module above the monolithic platen, wherein the polishing fluid delivery module is configured to deliver slurry to the monolithic platen during performance of CMP.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Lung Lai, Cheng-Ping Chen, Shih-Chung Chen, Sheng-Tai Peng
  • Patent number: 11908863
    Abstract: A transistor device includes a substrate, a fin structure extending on the substrate in a direction parallel to a top surface of the substrate, a source region and a drain region provided at an upper portion of the fin structure, a constant current generating layer provided at a lower portion of the fin structure, a gate insulating film provided on both side surfaces and a top surface of the upper portion of the fin structure, and a gate electrode provided on the gate insulating film, wherein the gate electrode is provided on the fin structure and between the source region and the drain region, the constant current generating layer generates a constant current between the drain region and the substrate, and the constant current is independent from a gate voltage applied to the gate electrode.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: February 20, 2024
    Assignee: UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)
    Inventors: Kyung Rok Kim, Jae Won Jeong, Young Eun Choi, Woo Seok Kim, Jiwon Chang
  • Patent number: 11894263
    Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a first metal line extending along a first direction, a second metal line lengthwise aligned with and spaced apart from the first metal line, and a third metal line extending along the first direction. The third metal line includes a branch extending along a second direction perpendicular to the first direction and the branch partially extends between the first metal line and the second metal line.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hsien Wu, Chung-Yi Lin, Yen-Sen Wang
  • Patent number: 11890715
    Abstract: A carrier head for holding a substrate in a polishing system includes a housing, a first flexible membrane secured to the housing to form one or more pressurizable chambers to apply pressure through a central membrane portion of the first flexible membrane to a central portion of a substrate, and a plurality of independently operable piezoelectric actuators supported by the housing, the plurality of piezoelectric actuators positioned radially outward of the central membrane portion and at different angular positions so as to independently adjust pressure on a plurality of angular zones in an annular outer region of the substrate surrounding the central portion of the substrate.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: February 6, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Brian J. Brown, Andrew J. Nagengast, Justin Ho Kuen Wong
  • Patent number: 11890717
    Abstract: A polishing system includes a platen having a top surface to support a main polishing pad. The platen is rotatable about an axis of rotation that passes through approximately the center of the platen. An annular flange projects radially outward from the platen to support an outer polishing pad. The annular flange has an inner edge secured to and rotatable with the platen and vertically fixed relative to the top surface of the platen. The annular flange is vertically deflectable such that an outer edge of the annular flange is vertically moveable relative to the inner edge. An actuator applies pressure to an underside of the annular flange in an angularly limited region, and a carrier head holds a substrate in contact with the polishing pad and is movable to selectively position a portion of the substrate over the outer polishing pad.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: February 6, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Jay Gurusamy, Steven M. Zuniga, Jeonghoon Oh
  • Patent number: 11883845
    Abstract: A method of forming an ultrasonic transducer device involves depositing a first layer on a substrate, depositing a second layer on the first layer, patterning the second layer at a region corresponding to a location of a transducer cavity, depositing a third layer that refills regions created by patterning the second layer, planarizing the third layer to a top surface of the second layer, removing the second layer, conformally depositing a fourth layer over the first layer and the third layer, defining the transducer cavity in a support layer formed over the fourth layer; and bonding a membrane to the support layer.
    Type: Grant
    Filed: January 5, 2023
    Date of Patent: January 30, 2024
    Assignee: BFLY OPERATIONS, INC.
    Inventors: Lingyun Miao, Keith G. Fife, Jianwei Liu, Jonathan M. Rothberg
  • Patent number: 11883926
    Abstract: A polishing pad is described. The polishing pad includes a surface having plural recess portions, and a substrate is polished by the surface. In the pad, an average width of the recess portions at one area of the surface in a direction parallel to the surface is 20 ?m or less, and an average density of the recess portions at one area of the surface is 1,300/mm2 or more.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: January 30, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Takahiko Kawasaki, Yukiteru Matsui, Akifumi Gawase
  • Patent number: 11875996
    Abstract: A method of depositing a metal material on an isolated seed layer uses a barrier layer as a conductive path for plating. The method may include depositing a barrier layer on a substrate wherein the barrier layer provides adhesion for seed layer material and inhibits migration of the seed layer material, forming at least one isolated seed layer area on the barrier layer on the substrate, and depositing the metal material on the at least one isolated seed layer area using an electrochemical deposition process wherein the barrier layer provides a current path to deposit the metal material on the at least one isolated seed layer area.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: January 16, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Marvin Louis Bernt
  • Patent number: 11862607
    Abstract: Composite dielectric structures for semiconductor die assemblies, and associated systems and methods are disclosed. In some embodiments, the composite dielectric structure includes a flexible dielectric layer configured to conform to irregularities (e.g., particles, defects) at a bonding interface of directly bonded semiconductor dies (or wafers). The flexible dielectric layer may include a polymer material configured to deform in response to localized pressure generated by the irregularities during bonding process steps. The composite dielectric structure includes additional dielectric layers sandwiching the flexible dielectric layer such that the composite dielectric structure can provide robust bonding strength to other dielectric layers through the additional dielectric layers. In some embodiments, a chemical vapor deposition process may be used to form the composite dielectric structure utilizing siloxane derivatives as a precursor.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: January 2, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Hung Cheng Chen, Yu Chun Chen, Hsuan Chao Hou
  • Patent number: 11862523
    Abstract: An apparatus for detecting an endpoint of a grinding process includes a connecting device, a timer and a controller. The connecting device is connected to a sensor that periodically senses an interface of a reconstructed wafer comprising a plurality of dies of at least two types to generate a thickness signal comprising thicknesses from a surface of an insulating layer of the reconstructed wafer to the interface of the reconstructed wafer. The timer is configured to generate a clock signal having a plurality of pulses with a time interval. The controller is coupled to the sensor and the timer, and configured to filter the thickness signal according to the clock signal to output a thickness extremum among the thicknesses in the thickness signal within each time interval, wherein the thickness signal after the filtering is used to determine the endpoint of the grinding process being performed on the reconstructed wafer.
    Type: Grant
    Filed: March 28, 2021
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chao Mao, Chin-Chuan Chang, Szu-Wei Lu
  • Patent number: 11862472
    Abstract: Methods for polishing dielectric layers using an auto-stop slurry in forming semiconductor devices, such as three-dimensional (3D) memory devices, are provided. The methods include forming a stack structure in a staircase region and a core array region, the stack structure including a staircase structure in the staircase region; forming a dielectric layer over the staircase region and a peripheral region outside the stack structure; and polishing the dielectric layer using an auto-stop slurry containing a ceria-based abrasive.
    Type: Grant
    Filed: August 23, 2022
    Date of Patent: January 2, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventor: Xiaohong Zhou
  • Patent number: 11854821
    Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Che-Hao Tu, William Weilun Hong, Ying-Tsung Chen
  • Patent number: 11854872
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first metal layer over a substrate, forming a dielectric layer over the first metal layer. The method includes forming a trench in the dielectric layer, and performing a surface treatment process on a sidewall surface of the trench to form a hydrophobic layer. The hydrophobic layer is formed on a sidewall surface of the dielectric layer. The method further includes depositing a metal material in the trench and over the hydrophobic layer to form a via structure.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Hao Kung, Chih-Chieh Chang, Kao-Feng Liao, Hui-Chi Huang, Kei-Wei Chen
  • Patent number: 11848200
    Abstract: A method for selectively forming a silicon nitride film on a substrate comprising a first metallic surface and a second dielectric surface by a cyclical deposition process is disclosed. The method may comprise contacting the substrate with a first reactant comprising a silicon halide source and contacting the substrate with a second reactant comprising a nitrogen source, wherein the incubation period for the first metallic surface is less than the incubation period for the second dielectric surface. Semiconductor device structures comprising a selective silicon nitride film are also disclosed.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: December 19, 2023
    Assignee: ASM IP Holding B.V.
    Inventors: Jacob Woodruff, Bed Sharma
  • Patent number: 11833638
    Abstract: A polishing pad useful in chemical mechanical polishing can comprise a base pad having a top surface and surface, a plurality of polishing elements each having a top polishing surface and a bottom surface, and wherein each of the plurality of polishing elements is connected to the top surface of the base pad to the polishing element by three or more supports wherein the bottom surface of the polishing element, the top surface of the base pad and the supports define a region comprising at least one void and there are openings between the three or more supports. Such pad can be used in a method by providing a substrate and polishing the substrate with the pad, optionally, with a polishing medium.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: December 5, 2023
    Assignee: Rohm and Haas Electronic Materials Holding, Inc.
    Inventors: John R. McCormick, Bryan E. Barton
  • Patent number: 11830729
    Abstract: Exemplary methods of semiconductor processing may include providing a boron-and-carbon-and-nitrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include generating a capacitively-coupled plasma of the boron-and-carbon-and-nitrogen-containing precursor. The methods may include forming a boron-and-carbon-and-nitrogen-containing layer on the substrate. The boron-and-carbon-and-nitrogen-containing layer may be characterized by a dielectric constant below or about 3.5.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: November 28, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Zeqing Shen, Bo Qi, Abhijit Basu Mallick, Nitin K. Ingle
  • Patent number: 11829077
    Abstract: A wafer shape metrology system includes a wafer shape metrology sub-system configured to perform one or more stress-free shape measurements on a first wafer, a second wafer, and a post-bonding pair of the first and second wafers. The wafer shape metrology system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller is configured to receive stress-free shape measurements from the wafer shape sub-system; predict overlay between one or more features on the first wafer and the second wafer based on the stress-free shape measurements of the first wafer, the second wafer, and the post-bonding pair of the first wafer and the second wafer; and provide a feedback adjustment to one or more process tools based on the predicted overlay. Additionally, feedforward and feedback adjustments may be provided to one or more process tools.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: November 28, 2023
    Assignee: KLA Corporation
    Inventors: Franz Zach, Mark D. Smith, Xiaomeng Shen, Jason Saito, David Owen
  • Patent number: 11820919
    Abstract: The present disclosure provides a new corrosion control chemistry for use in ruthenium (Ru) chemical-mechanical polishing (CMP) processes. More specifically, the present disclosure provides an improved CMP slurry chemistry and CMP process for planarizing a ruthenium surface. In the CMP process disclosed herein, a ruthenium surface (e.g., a post-etch ruthenium surface) is exposed to a CMP slurry containing a halogenation reagent, which reacts with the ruthenium surface to create a halogenated ruthenium surface, and a ligand for ligand-assisted reactive dissolution of the halogenated ruthenium surface. Relative amounts of the halogenation agent and the ligand can be controlled in the CMP slurry, so as to provide a diffusion-limited etch process that improves pos-etch surface morphology, while providing high material removal rates.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: November 21, 2023
    Assignee: Tokyo Electron Limited
    Inventor: Paul Abel
  • Patent number: 11817408
    Abstract: A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view.
    Type: Grant
    Filed: January 6, 2023
    Date of Patent: November 14, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Minjung Choi, Sooho Shin, Yeonjin Lee, Junghoon Han
  • Patent number: 11812607
    Abstract: A semiconductor device may include active pattern, a silicon liner, an insulation layer, an isolation pattern and a transistor. The active pattern may protrude from a substrate. The silicon liner having a crystalline structure may be formed conformally on surfaces of the active pattern and the substrate. The insulation layer may be formed on the silicon liner. The isolation pattern may be formed on the insulation layer to fill a trench adjacent to the active pattern. The transistor may include a gate structure and impurity regions. The gate structure may be disposed on the silicon liner, and the impurity regions may be formed at the silicon liner and the active pattern adjacent to both sides of the gate structure.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: November 7, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sungmi Yoon, Donghyun Im, Jooyub Kim, Juhyung We, Namhoon Lee, Chunhyung Chung
  • Patent number: 11806835
    Abstract: An apparatus for chemical mechanical polishing includes a rotatable platen having a surface to support a polishing pad, a carrier head to hold a substrate in contact with the polishing pad, and a polishing liquid distribution system. The polishing liquid distribution system includes a dispenser positioned to deliver a polishing liquid to a portion of a polishing surface of the polishing pad, and a first barrier positioned before the portion of the polishing surface and configured to block used polishing liquid from reaching the portion of the polishing surface.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: November 7, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Yen-Chu Yang, Stephen Jew, Jianshe Tang, Haosheng Wu, Shou-Sung Chang, Paul D. Butterfield, Alexander John Fisher, Bum Jick Kim
  • Patent number: 11809945
    Abstract: An apparatus for marking a component by applying readable identifying information is provided. The identifying information has at least one identifying feature, in particular an identifying symbol. The apparatus includes a detection device which is designed to detect, on the basis of an eddy current measurement, identifying information applied or to be applied to a component by way of the apparatus.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: November 7, 2023
    Assignee: Bayerische Motoren Werke Aktiengesellschaft
    Inventors: Felix Burger, Bernhard Glueck, Robert Kirschner, Mario Meinhardt, Peter Soell
  • Patent number: 11806836
    Abstract: A composition is provided that comprises a calcium carbonate slurry. The calcium carbonate slurry comprises a plurality of calcium carbonate particles suspended in a solution, where the solution comprises a dispersant and an anionic surfactant. The concentration of the calcium carbonate particles in the calcium carbonate slurry is equal to or less than about 2.0 wt. %.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: November 7, 2023
    Assignee: Illumina, Inc.
    Inventors: Robert Yang, Samantha K. Brittelle, You-Jung Cheng, Scott William Bailey, James M. Tsay
  • Patent number: 11802220
    Abstract: The invention provides a chemical-mechanical polishing composition comprising: (a) a silica abrasive, (b) a surfactant, (c) an iron cation, (d) optionally a ligand, and (e) water, wherein the silica abrasive has a negative zeta potential in the chemical-mechanical polishing composition. The invention also provides a method of chemically-mechanically polishing a substrate, especially a substrate comprising a carbon-based film, using said composition.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: October 31, 2023
    Assignee: CMC Materials, Inc.
    Inventors: Brian Reiss, Fernando Hung Low, Michael Morrow, Helin Huang
  • Patent number: 11771874
    Abstract: A method for producing a balloon for a balloon catheter includes providing the balloon that has an outer surface. A solution including a solvent and a polymer is used to deposit the polymer onto the surface and form a surface coating of the polymer.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: October 3, 2023
    Assignee: BIOTRONIK AG
    Inventors: Bodo Quint, Jeremy Wernli
  • Patent number: 11772230
    Abstract: The present invention provides CMP polishing pads or layers having a unfilled Shore D (2 second) hardness of from 57-77 or a filled Shore D (2 second) hardness of from 18-50, made from a two-component reaction mixture of (i) a liquid aromatic isocyanate component comprising one or more aromatic diisocyanates or a linear aromatic isocyanate-terminated urethane prepolymer having an unreacted isocyanate (NCO) concentration of from 18 to 47 wt. %, based on the total solids weight of the aromatic isocyanate component, and (ii) a liquid polyol component including one or more curatives selected from the group of amines defined by Formulas (I) and (II).
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: October 3, 2023
    Assignee: Rohm and Haas Electronic Materials CMP Holdings Inc.
    Inventors: Jing Ren, Kwadwo Tettey, Bryan E. Barton
  • Patent number: 11776850
    Abstract: The present disclosure relates to a method for forming a semiconductor structure includes depositing a dielectric layer on a substrate and depositing a patterning layer on the dielectric layer. The method also includes performing a first etching process on the patterning layer to form a first region including a first plurality of blocks at a first pattern density and a second region including a second plurality of blocks at a second pattern density that is lower than the first pattern density. The method also includes performing a second etching process on the second plurality of blocks to decrease a width of each block of the second plurality of blocks and etching the dielectric layer and the substrate using the first and second pluralities of blocks to form a plurality of fin structures.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: October 3, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Lun Chen, Li-Te Lin, Chao-Hsien Huang
  • Patent number: 11773292
    Abstract: An object of the present invention is to provide a polishing composition that can achieve both a high polishing removal rate and high surface quality. According to the present invention, provided is a polishing composition for polishing a material to be polished. The polishing composition contains sodium metavanadate, hydrogen peroxide, and silica abrasive. The content C1 of sodium metavanadate is 0.7% to 3.5% by weight, the content C2 of hydrogen peroxide is 0.3% to 3% by weight, and the content C3 of the silica abrasive is 12% to 50% by weight.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: October 3, 2023
    Assignee: FUJIMI INCORPORATED
    Inventors: Hiroki Kon, Naoto Noguchi
  • Patent number: 11769699
    Abstract: A semiconductor manufacturing apparatus includes a sound measuring unit that measures a first polishing sound of a film formed on a wafer, a sound pressure prediction regression model generation unit that generates a first regression model for obtaining a first sound pressure prediction value of the first polishing sound, a sound pressure prediction value calculation unit that performs a first calculation of the first sound pressure prediction value by using the first regression model, a residual difference calculation unit that performs a second calculation of a first residual difference, the first residual difference being a difference between a first sound pressure actual measurement value of the first polishing sound and the first sound pressure prediction value, and an end point determination unit that determines a polishing end point of the film by using the first residual difference.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: September 26, 2023
    Assignee: KIOXIA CORPORATION
    Inventor: Tsutomu Miki
  • Patent number: 11735477
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: August 22, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Feng Shieh, Hung-Chang Hsieh, Wen-Hung Tseng