Simultaneous (e.g., Chemical-mechanical Polishing, Etc.) Patents (Class 438/692)
  • Patent number: 11417566
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first metal layer over a substrate, forming a dielectric layer over the first metal layer. The method includes forming a trench in the dielectric layer, and performing a surface treatment process on a sidewall surface of the trench to form a hydrophobic layer. The hydrophobic layer is formed on a sidewall surface of the dielectric layer. The method further includes depositing a metal material in the trench and over the hydrophobic layer to form a via structure.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Hao Kung, Chih-Chieh Chang, Kao-Feng Liao, Hui-Chi Huang, Kei-Wei Chen
  • Patent number: 11407908
    Abstract: A radiation-curable ink jet composition includes a monofunctional (meth)acrylate monomer and vinyl methyl oxazolidinone.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: August 9, 2022
    Inventors: Toru Saito, Naoki Koike, Toshiyuki Yoda, Kyohei Tanaka
  • Patent number: 11407909
    Abstract: A radiation-curable ink jet composition includes vinyl methyl oxazolidinone and a vinyl ether group-containing (meth)acrylate represented by the following formula (1): H2C?CR1—CO—OR2—O—CH?CH—R3 (where, R1 is a hydrogen atom or a methyl group, R2 is a divalent C2-C20 organic residue, and R3 is a hydrogen atom or a monovalent C1-C11 organic residue).
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: August 9, 2022
    Inventors: Toshiyuki Yoda, Toru Saito, Naoki Koike, Kiyoshi Nakamura, Kyohei Tanaka
  • Patent number: 11398557
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first well, a second well, an isolation structure, a first field plate, a gate structure, a drain structure, and a source structure. The first well and the second well adjoin each other. The first well and the second well are disposed in the substrate. The isolation structure is disposed on the first well. The first field plate is disposed on the isolation structure. The gate structure crosses the first well and the second well, and an opening is defined between the first field plate and the gate structure to expose an edge of the isolation structure adjacent to the gate structure. The drain structure is disposed in the first well. The source structure is disposed in the second well.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: July 26, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yi-Ching Chung, Jui-Chun Chang, Fu-Chun Tseng, Yu-Ping Ho
  • Patent number: 11384255
    Abstract: The present invention relates to a polishing slurry composition for an STI process, the polishing slurry composition comprising: a polishing solution including polishing particles; and an additive solution containing a nitride film polishing barrier inclusive of a polymer having an amide bond.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: July 12, 2022
    Assignee: KCTECH CO., LTD.
    Inventors: Hae Won Yang, Jun Ha Hwang, Jung Yoon Kim, Kwang Soo Park
  • Patent number: 11361946
    Abstract: In a substrate processing apparatus, a processing chamber, in which a target substrate is disposed and substrate processing is performed on the target substrate, is provided. A consumable part is disposed in the processing chamber and consumed by the substrate processing. A supply unit is configured to supply an ionic liquid in response to a consumption of the consumable part. A drive unit is configured to drive the consumable part by using the ionic liquid supplied from the supply unit.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: June 14, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Masato Kon
  • Patent number: 11348820
    Abstract: The present disclosure relates to an installation fixture for an electrode plate of a semiconductor equipment. The installation fixture includes: an alignment assembly, including a support disc and at least two guide shafts, where the support disc is provided with at least two positioning holes, at least two fixing holes and at least two mounting holes; a drive assembly, including a mounting plate assembly, at least two support rods and a drive rod assembly, where the support rods are connected to the mounting plate assembly, and one end of each of the support rods is connected to one of the mounting holes; and the drive rod assembly is connected to the mounting plate assembly; and a support assembly, including at least two support bases, where each of the support bases is provided with a mounting groove.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: May 31, 2022
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Jiangyi Jin, Jungsu Kang
  • Patent number: 11325220
    Abstract: A double-side polishing method, including: simultaneously polishing both surfaces of a semiconductor wafer by holding the semiconductor wafer in a carrier, interposing the held semiconductor wafer between an upper turn table and a lower turn table each having a polishing pad attached thereto, and bringing both surfaces of the semiconductor wafer into sliding contact with the polishing pads, wherein the semiconductor wafer is polished under a condition that a thickness A (mm) of the polishing pad attached to the upper turn table and a thickness B (mm) of the polishing pad attached to the lower turn table satisfy relations of 1.0?A+B?2.0 and A/B>1.0. This provides a double-side polishing method capable of obtaining a semiconductor wafer in which F-ZDD<0 while controlling the GBIR value to be equal to or smaller than a required value.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: May 10, 2022
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Yuki Tanaka, Shiro Amagai
  • Patent number: 11289504
    Abstract: A three-dimensional semiconductor memory device may include horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other, memory structures provided on the horizontal patterns, respectively, each of the memory structures including a three-dimensional arrangement of memory cells. Penetrating insulating patterns and separation structures may isolate the horizontal patterns from one another. Through vias may extend through the penetrating insulating patterns to connect logic circuits of the peripheral circuit structure to the memory structure.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: March 29, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Woosung Yang, Dong-Sik Lee, Sung-Min Hwang, Joon-Sung Lim
  • Patent number: 11279904
    Abstract: Provided is a cleaning liquid composition which is useful for cleaning of a substrate or the like that has been subjected to a chemical mechanical polishing (CMP) process, etc in the production steps of an electronic device such as a semiconductor element. A cleaning liquid composition according to the present invention is used for the purpose of cleaning a substrate that has a Cu wiring, and comprises one or more basic compounds and one or more nitrogen-containing monocyclic heterocyclic aromatic compounds that contain one or more carboxyl groups or ester groups, provided that in cases where one or more amino groups are contained therein, only amino groups directly bonded to a nitrogen-containing heterocyclic rind are contained. This cleaning liquid composition has a hydrogen ion concentration (pH) of 8-12.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: March 22, 2022
    Assignee: KANTO KAGAKU KABUSHIKI KAISHA
    Inventors: Kikue Morita, Areji Takanaka, Takuo Ohwada
  • Patent number: 11261336
    Abstract: Processes, compositions and agents are included for inhibiting corrosion in various substrates, for example metal substrates. Corrosion inhibitors include organometallic polymers such as metal-organic frameworks (MOFs), including compositions and processes comprising MOFs for inhibiting corrosion in metal substrates. In some aspects, a method of protecting a substrate from corrosion includes applying a protective composition including a corrosion inhibitor to the surface of a substrate, where the corrosion inhibitor includes a metal organic framework (MOF).
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: March 1, 2022
    Assignee: THE BOEING COMPANY
    Inventors: James Ivan Mardel, Ivan Stewart Cole, Paul Andrew White, Anthony Ewart Hughes, Tracey Anne Markley, Timothy Graham Harvey, Joseph Osborne, Erik Sapper
  • Patent number: 11257257
    Abstract: a device and a method are disclosed to detect obstructed objects, usually behind a wall or other similar surface. The device may be used by dragging it across the surface of the wall to scan, detect and display the objects behind the wall. The types of hidden objects and materials they are made of vary and may include wooden or metal studs used in building construction, electrical AC or DC wires and conduits, metal rebar and the like. Each type of material may need a different type of sensor to be detected. In some examples, the device may include memory to record the objects detected and display them on the screen in a persistent manner. The objects may be displayed via graphics that are similar to the real objects that were detected. In effect, the device may display a picture of what is hidden behind the wall.
    Type: Grant
    Filed: March 13, 2021
    Date of Patent: February 22, 2022
    Inventors: Michael H. Panosian, Joshua M. Keeler
  • Patent number: 11201134
    Abstract: A method of manufacturing a semiconductor device includes the following steps. A device wafer having a product-obtaining part and an edge part surrounding the product-obtaining part is provided. A passivation layer is formed to cover the device wafer. A first oxide cap layer is formed to cover the passivation layer. An edge trimming process is performed to polish an edge part of the first oxide cap layer, an edge part of the passivation layer and the edge part of the device wafer. A removing process is performed to remove the first oxide cap layer after the edge trimming process is performed. A second oxide cap layer is formed to cover the first oxide cap layer and the edge part of the device wafer.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: December 14, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yonghui Gao, Yi Liu, Guohai Zhang
  • Patent number: 11193044
    Abstract: An acidic slurry composition for use in chemical-mechanical polishing including an acid pH adjuster and a cationic polishing suppressant comprising a quaternized aromatic heterocycle. The quaternized aromatic heterocycle imparts a polishing selectivity of silica over crystalline silicon of at least 100.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: December 7, 2021
    Assignee: Ferro Corporation
    Inventor: Nathaniel D. Urban
  • Patent number: 11195810
    Abstract: A device includes an interconnect structure over a substrate, multiple first conductive pads over and connected to the interconnect structure, a planarization stop layer extending over the sidewalls and top surfaces of the first conductive pads of the multiple first conductive pads, a surface dielectric layer extending over the planarization stop layer, and multiple first bonding pads within the surface dielectric layer and connected to the multiple first conductive pads.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: December 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen
  • Patent number: 11107682
    Abstract: A method of patterning a substrate includes forming mandrels on a target layer of a substrate, the mandrels being comprised of at least two layers of material, the mandrels including a bottom layer comprised of a first material, and a top layer comprised of a second material, the target layer being comprised of a fifth material. The method includes forming sidewall spacers on sidewalls of the mandrels, the sidewall spacers comprised of a third material. The method includes depositing a fill material on the substrate that at least partially fills open spaces defined between the sidewall spacers, the fill material being comprised of a fourth material. The method includes executing a chemical-mechanical polishing step that uses the bottom layer of the mandrels as a planarization stop material layer, the chemical-mechanical polishing step removing the third material above a top surface of the bottom layer of the mandrels.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: August 31, 2021
    Assignee: Tokyo Electron Limited
    Inventor: Anton J. deVilliers
  • Patent number: 11098224
    Abstract: A method for polishing a glass substrate, by which a polishing speed that is higher than a conventional polishing speed can be maintained for a long period of time in processing for polishing a glass substrate using cerium oxide as polishing abrasive particles is provided. A polishing liquid containing cerium oxide as polishing abrasive particles is supplied to a polishing surface of a glass substrate, and the glass substrate is subjected to polishing processing. This polishing liquid contains the cerium oxide as polishing abrasive particles and a substance that reduces cerium oxide in response to light irradiation. Also, processing for irradiating the polishing liquid with light is performed when polishing processing is performed.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: August 24, 2021
    Assignee: HOYA CORPORATION
    Inventors: Hiroki Nakagawa, Kashio Nakayama
  • Patent number: 11069563
    Abstract: Planarization is performed on heterogeneous films with high accuracy. According to one embodiment, a method for processing a substrate is provided. The substrate is formed of an insulating film layer where a groove is formed, a barrier metal layer, and a wiring metal layer in order from a bottom in at least a part of a region. The method includes (3) while the wiring metal layer, the barrier metal layer, and the insulating film layer are exposed to the surface of the substrate: a step of bringing the surface of the substrate into contact with a catalyst; a step of supplying a process liquid between the catalyst and the surface of the substrate; and a step of flowing a current between the catalyst and the surface of the substrate.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: July 20, 2021
    Assignee: EBARA CORPORATION
    Inventors: Atsuo Katagiri, Itsuki Kobata
  • Patent number: 11059145
    Abstract: A dressing apparatus 200 includes a bus member 203 which is equipped with a ceiling plate 201 and a circular or polygonal cylindrical skirt portion 202 provided at a bottom surface of the ceiling plate 201 and which is configured to accommodate a polishing pad 131 from thereabove. The bus member 203 includes a dual fluid nozzle 204 configured to jet a cleaning liquid and a gas onto a polishing surface of the polishing pad 131; a dress board 205 configured to come into contact with the polishing surface of the polishing pad 131; and a rinse nozzle 206 configured to supply a rinse liquid onto a contact surface between the polishing surface of the polishing pad 131 and the dress board 205. A cleaning liquid, a fragment of a grindstone or a sludge is suppressed from being scattered around by the skirt portion 202.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: July 13, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yoshiki Okamoto, Yasushi Takiguchi, Akihiro Kubo, Hayato Hosaka, Ryuto Ozasa
  • Patent number: 11043396
    Abstract: Methods of manufacturing a chemical-mechanical polishing (CMP) slurry and methods of performing CMP process on a substrate comprising metal features are described herein. The CMP slurry may be manufactured using a balanced concentration ratio of chelator additives to inhibitor additives, the ratio being determined based on an electro potential (Ev) value of a metal material of the substrate. The CMP process may be performed on the substrate based on the balanced concentration ratio of chelator additives to inhibitor additives of the CMP slurry.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: June 22, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hao Kung, Tung-Kai Chen, Chih-Chieh Chang, Kao-Feng Liao, Hui-Chi Huang, Kei-Wei Chen
  • Patent number: 10995238
    Abstract: A neutral to alkaline chemical mechanical composition for polishing tungsten includes, as initial components: water; an oxidizing agent selected from an iodate compound, a periodate compound and mixtures thereof; colloidal silica abrasive particles including a nitrogen-containing compound; optionally, a pH adjusting agent; and, optionally, a biocide. The chemical mechanical polishing method includes providing a chemical mechanical polishing pad, having a polishing surface; creating dynamic contact at an interface between the polishing pad and the substrate; and dispensing the neutral to alkaline chemical mechanical polishing composition onto the polishing surface at or near the interface between the polishing pad and the substrate; wherein some of the tungsten is polished away from the substrate and, further, to at least inhibit static etch of the tungsten.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: May 4, 2021
    Assignee: Rohm and Haas Electronic Materials CMP Holdings
    Inventors: Yi Guo, Tony Quan Tran
  • Patent number: 10991573
    Abstract: Plasma enhanced atomic layer deposition (PEALD) processes for simultaneously depositing SiOC on two or more different surfaces of a substrate are provided. For example, SiOC may be deposited simultaneously on a first dielectric surface and a second metal or metallic surface. The PEALD processes can comprise two or more deposition cycles for forming SiOC on the two surfaces. The deposition cycles may comprise alternately and sequentially contacting the substrate with a first precursor comprising silicon and a second plasma reactant, such as an Ar/H2 plasma. In some embodiments, a PEALD process further comprises contacting the substrate with a plasma reactant prior to beginning the deposition cycle. In some embodiments, the deposition cycle is repeated more than 500 times and a uniform SiOC film may be formed on the two different surfaces.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: April 27, 2021
    Assignee: ASM IP HOLDING B.V.
    Inventors: Lingyun Jia, Viljami Pore, Eva Tois, Sun Ja Kim
  • Patent number: 10988636
    Abstract: To provide a polishing composition capable of polishing an object to be polished containing a silicon nitride film at a high polishing removal rate and reducing the particle residual amount on the object to be polished and a method for manufacturing the same, a polishing method, and a method for manufacturing a substrate. A polishing composition is a polishing composition containing abrasives, an anionic surfactant, and a dispersion medium, in which the anionic surfactant has at least one kind of acidic functional group selected from the group consisting of a sulfo group, a phosphate group, and a phosphonic acid group and a polyoxyalkylene group and the pH is less than 7 and which is used for polishing an object to be polished containing a silicon nitride film.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: April 27, 2021
    Assignee: FUJIMI INCORPORATED
    Inventors: Toshio Shinoda, Aya Nishimura
  • Patent number: 10978311
    Abstract: The present invention relates to a method for separating at least one solid-body layer (4) from at least one solid body (1). Thereby, the method as claimed in the invention comprises the steps: creating a plurality of modifications (9) by means of laser beams within the interior space of the solid body (1) to form a detachment plane (8), producing a composite structure by arranging or producing layers and/or components (150) on or above an initially exposed surface (5) of the solid body (1), wherein the exposed surface (5) is an integral part of the solid-body layer (4) to be separated, introducing an external force into the solid body (1) for generating tensions within the solid body (1), wherein the external force is so strong that the tensions initialize a crack propagation along the detachment plane (8), wherein the modifications for forming the detachment plane (8) are created before producing the composite structure.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: April 13, 2021
    Assignee: Siltectra GmbH
    Inventors: Wolfram Drescher, Marko Swoboda, Ralf Rieske, Christian Beyer, Jan Richter
  • Patent number: 10954411
    Abstract: An acid chemical mechanical polishing composition polishes silicon nitride over silicon dioxide and simultaneously inhibits damage to the silicon dioxide. The acid chemical mechanical polishing composition includes polyvinylpyrrolidone polymers, anionic functional colloidal silica abrasive particles and an amine carboxylic acid. The pH of the acid chemical mechanical polishing composition is 5 or less.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: March 23, 2021
    Assignee: Rohm and Haas Electronic Materials CMP Holdings
    Inventors: Naresh Kumar Penta, Kwadwo E. Tettey, Matthew Van Hanehem
  • Patent number: 10899945
    Abstract: Use of a chemical mechanical polishing (CMP) composition (Q) for chemical mechanical polishing of a substrate (S) comprising (i) cobalt and/or (ii) a cobalt alloy and (iii) Ti N and/or TaN, wherein the CMP composition (Q) comprises (E) Inorganic particles (F) at least one organic compound comprising an amino-group and an acid group (Y), wherein said compound comprises n amino groups and at least n+1 acidic protons, wherein n is a integer?1. (G) at least one oxidizer in an amount of from 0.2 to 2.5 wt.-% based on the total weight of the respective CMP composition, (H) an aqueous medium wherein the CMP composition (Q) has a pH of more than 6 and less than 9.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: January 26, 2021
    Assignee: BASF SE
    Inventors: Robert Reichardt, Max Siebert, Yongqing Lan, Michael Lauter, Sheik Ansar Usman Ibrahim, Reza M. Golzarian, Te Yu Wei, Haci Osman Guevenc, Julian Proelss, Leonardus Leunissen
  • Patent number: 10892165
    Abstract: A semiconductor manufacturing device including: a polishing head that is capable of retaining a semiconductor substrate; a polishing pad having a processing surface to be abutted to the semiconductor substrate retained by the polishing head, the processing surface including a groove; a platen that is capable of rotating about a rotary shaft running along a direction intersecting the processing surface, in a state in which the polishing pad is retained by the platen; a measuring section that is configured to output a measurement value indicating a height of the processing surface at a predetermined location along a circumference of a circle centered about the rotary shaft of the platen; and a derivation section that is configured to derive a depth of the groove from the measurement value of the measuring section.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: January 12, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Kiyohiko Toshikawa, Hiroyuki Baba
  • Patent number: 10867794
    Abstract: A hard mask formed over a patterned photoresist layer in a tri-layer photoresist and a method for patterning a target layer using the same are disclosed. In an embodiment, a method includes depositing a photoresist layer over a first hard mask layer; patterning the photoresist layer to form a plurality of openings in the photoresist layer; depositing a second hard mask layer over the photoresist layer, the second hard mask layer filling the plurality of openings, the second hard mask layer having a first etch selectivity relative to the first hard mask layer, the photoresist layer having a second etch selectivity relative to the first hard mask layer, the first etch selectivity being greater than the second etch selectivity; planarizing the second hard mask layer; removing the photoresist layer; and etching the first hard mask layer using the second hard mask layer as a mask.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Yu Chang, Jung-Hau Shiu, Szu-Ping Tung, Chun-Kai Chen, Jen Hung Wang, Tze-Liang Lee
  • Patent number: 10865361
    Abstract: Described is a post chemical-mechanical-polishing (post-CMP) cleaning composition comprising or consisting of: (A) one or more water-soluble nonionic copolymers of the general formula (I) and mixtures thereof, formula (I) wherein R1 and R3 are independently from each other hydrogen, methyl, ethyl, n-propyl, iso-propyl, n-butyl, iso-Butyl, or sec-butyl, R2 is methyl and x and y are an integer, 1 (B)poly(acrylic acid) (PAA) or acrylic acid-maleic acid copolymer with a mass average molar mass (Mw) of up to 10,000 g/mol, and (C) water, wherein the pH of the composition is in the range of from 7.0 to 10.5.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: December 15, 2020
    Assignee: BASF SE
    Inventors: Christian Daeschlein, Max Siebert, Michael Lauter, Leonardus Leunissen, Ivan Garcia Romero, Haci Osman Guevenc, Peter Przybylski, Julian Proelss, Andreas Klipp
  • Patent number: 10751738
    Abstract: A spray manifold for a brush box is disclosed which includes an elongated body having a plurality of holes formed in a line along a direction parallel to a longitudinal axis of the body, a linear slot formed along a length of the body aligning with the line of the holes, a central bore formed along the length of the body and between each of the holes and the slot, and a cover disposed on the slot.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: August 25, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jagan Rangarajan, Gee Sun Hoey, Jaimie Stomberg, Ekaterina Mikhaylichenko
  • Patent number: 10741381
    Abstract: A cleaning apparatus and a method of using the cleaning apparatus are provided. The method includes first moving a pencil pad into contact with a top surface of a wafer, wherein the pencil pad is connected to a pivot arm and second moving the pivot arm in a sweeping motion from a first zone to a second zone, the first zone being closer to a center of the top surface of the wafer than the second zone, wherein the sweeping motion is controlled by a controller, the pivot arm moves at a first speed in the first zone and the pivot arm moves at a second speed in the second zone, wherein the first speed is different from the second speed.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: August 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kaw-Wei Kuo, Chun-Hao Kung, Kuo-Feng Huang, Yi-Wei Chiu, Wei-Chun Chen
  • Patent number: 10720358
    Abstract: Devices and methods that include for configuring a profile of a liner layer before filling an opening disposed over a semiconductor substrate. The liner layer has a first thickness at the bottom of the opening and a second thickness a top of the opening, the second thickness being smaller that the first thickness. In an embodiment, the filled opening provides a contact structure.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: July 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Joanna Chaw Yane Yin, Hua Feng Chen
  • Patent number: 10680535
    Abstract: A vertical comb-drive actuator comprising a support base and a movable body is described. The support base comprises first comb electrodes and a first surface wherein the first comb electrodes extend from the first surface. The movable body attached to the support base comprises second comb electrodes and a second surface wherein the second comb electrodes extend from the second surface. The movable body may rotate about a rotation axis and the first comb electrodes are interdigitated with the second comb electrodes correspondingly. The second comb electrodes extend along a first direction, the rotation axis extends along a second direction, and the first comb electrodes extend along a third direction. The distance between the first lateral face of the first comb electrode and the second surface is shorter than the second length defined as the distance between the end surface of the second comb electrode and the second surface.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: June 9, 2020
    Assignee: OPUS MICROSYSTEMS CORPORATION
    Inventors: Chang-li Hung, Ta-wei Lin, Kai-yu Jiang
  • Patent number: 10625392
    Abstract: The present invention is a polishing pad formed by foamed polyurethane, with a content of S phase in the foamed polyurethane, as determined by pulsed NMR measurement at 25° C., exceeding 70%.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: April 21, 2020
    Assignee: NITTA HAAS INCORPORATED
    Inventors: Yohei Murakami, Nobuyuki Oshima, Hiroyuki Nakano
  • Patent number: 10610994
    Abstract: A polishing module includes a chuck having a substrate receiving surface and a perimeter, and one or more polishing pad assemblies positioned about the perimeter of the chuck, wherein each of the one or more polishing pad assemblies are coupled to an actuator that provides movement of the respective polishing pad assemblies in a sweep direction, a radial direction, and a oscillating mode relative to the substrate receiving surface and are limited in radial movement to about less than one-half of the radius of the chuck as measured from the perimeter of the chuck.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: April 7, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Eric Lau, Hui Chen, King Yi Heung, Chih Chung Chou, Edwin C. Suarez, Garrett Ho Yee Sin, Charles C. Garretson, Jeonghoon Oh
  • Patent number: 10586694
    Abstract: According to one embodiment, a method for fabricating a semiconductor device includes performing a back surface processing to remove at least one of a scratch and a foreign material formed on a back surface of a substrate to be processed, a front surface of the substrate being retained in a non-contact state, contacting the back surface of the substrate to a stage to be retained, and providing a pattern on the front surface of the substrate by using lithography.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: March 10, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Masako Kodera, Hiroshi Tomita, Takeshi Nishioka
  • Patent number: 10510540
    Abstract: Methods of forming semiconductor devices comprising etching a hardmask and spin-on-carbon layer through an opening in a photoresist to expose a gapfill material. The photoresist, spin-on-carbon layer and gapfill material are removed. A new spin-on-carbon layer, hardmask and photoresist are formed with an opening over a spacer mandrel. The hardmask, spin-on-carbon layer are etched through the opening and the layers and spacer mandrel are removed. An etch stop layer and oxide layer are removed and a height of the spacer mandrel and gapfill material are reduced exposing portions of the substrate. The exposed portions of the substrate are fin etched and the layers removed.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: December 17, 2019
    Assignee: MICROMATERIALS LLC
    Inventors: Ying Zhang, Qingjun Zhou, Yung-Chen Lin, Ho-yung David Hwang
  • Patent number: 10478939
    Abstract: The present invention provides a means allowing achievement of sufficient planarization of the surface of an object to be polished containing two or more types of materials. The present invention is a polishing method for polishing an object to be polished containing two or more types of materials by using a polishing composition, the polishing method including equalization of the surface zeta potential of the object to be polished.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: November 19, 2019
    Assignee: FUJIMI INCORPORATED
    Inventors: Yukinobu Yoshizaki, Satoru Yarita, Shogo Onishi
  • Patent number: 10434623
    Abstract: A polishing module including a chuck having a substrate receiving surface and a perimeter, and one or more polishing pad assemblies positioned about the perimeter of the chuck, wherein each of the one or more polishing pad assemblies are coupled to an actuator that provides movement of the respective polishing pad assemblies in one or more of a sweep direction, a radial direction, and a oscillating mode relative to the substrate receiving surface and are limited in radial movement to about less than one-half of the radius of the chuck as measured from the perimeter of the chuck.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: October 8, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Eric Lau, Hui Chen, King Yi Heung, Wei-Cheng Lee, Chih Chung Chou, Edwin C. Suarez, Garrett Ho Yee Sin, Charles C. Garretson, Jeonghoon Oh
  • Patent number: 10371939
    Abstract: One or more apparatus providing over-travel protection for actuators are disclosed. An example apparatus includes a mirror; a first plate coupled to the mirror; and a support post coupled the first plate, the support post structured to prevent the mirror from moving within a threshold distance to a second plate.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: August 6, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: William Craig McDonald, James Norman Hall, Adam Joseph Fruehling
  • Patent number: 10350728
    Abstract: Polishing pad cleaning systems and related methods are disclosed. A rotatable platen comprising a polishing pad in combination with a fluid, such as a polishing fluid, contacts a substrate to planarize material at the surface thereof and resultantly creates debris. A cleaning system introduces a spray system to remove debris from the polishing pad to prevent substrate damage and improve efficiency, a waste removal system for removing used spray, used polishing fluid, and debris from the polishing pad, and a polishing fluid delivery system for providing fresh polishing fluid to the polishing pad, such that the substrate only receives fresh polishing fluid upon each complete rotation of the platen. In this manner, within die performance is enhanced, the range of certain CMP processes is improved, scratches and contamination are avoided for each polished substrate and for later-polished substrates, and platen temperatures are reduced.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: July 16, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Jie Diao, Erik S. Rondum, Thomas Ho Fai Li, Bum Jick Kim, Christopher Heung-Gyun Lee
  • Patent number: 10334184
    Abstract: An electronic device may have an optical system that includes one or more light-based components. The light-based components may include light-emitting components such as light-emitting diodes or lasers and may include light-detecting components such as photodiodes or digital image sensors. The optical system may include a light diffuser. The light diffuser may diffuse light that is being detected by a light-detecting component or may diffuse light that is being emitted by a light-emitting component. Light diffusers in optical systems may be formed from patterned light diffuser layers on transparent substrates. Layers of sealant, thin glass layers, antireflection coatings, and other layers may be incorporated into the light diffusers. The light diffuser layers may operate at visible wavelengths and infrared wavelengths. An infrared light diffuser layer may be formed from a patterned silicon layer such as a patterned layer of hydrogenated amorphous silicon.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: June 25, 2019
    Assignee: Apple Inc.
    Inventors: Ligang Wang, Miodrag Scepanovic, Neil MacKinnon, Zhenbin Ge
  • Patent number: 10322493
    Abstract: An apparatus for polishing a semiconductor wafer using a pad resurfacing arm and an apparatus therefor are disclosed. Embodiments may include providing a semiconductor wafer on a chemical mechanical polishing (CMP) tool, the CMP tool including a polish pad and a pad resurfacing arm which includes a pad cleaning part, a pad conditioning part, and a slurry dispensing part, dispensing a slurry to the polish pad utilizing the pad resurfacing arm, and polishing the semiconductor wafer utilizing the polish pad.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: June 18, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Jens Kramer
  • Patent number: 10323162
    Abstract: The present invention provides an abrasive material capable of polishing difficult-to-polish silicon carbide at a high degree of surface precision. The present invention relates to an abrasive material including manganese dioxide particles having a non-needle-like shape possessing a ratio of the longitudinal axis to the transverse axis of the particles observed with a scanning electron microscope of 3.0 or less. The abrasive material is preferable if the average particle size DSEM of the longitudinal axis of the observed particles is 1.0 ?m or less, and if the particle size D50 of the volume-based cumulative fraction of 50% in laser diffraction/scattering particle size distribution measurement is 2.0 ?m or less.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: June 18, 2019
    Assignee: Mitsui Minig & Smelting Co., Ltd.
    Inventors: Mikimasa Horiuchi, Ryutaro Kuroda, Yasuhide Yamaguchi
  • Patent number: 10326040
    Abstract: Embodiments relate to forming a conformable interface layers (clayers) on small semiconductor devices, such as light emitting diodes (LEDs) to facilitate adhesion with a pick-up head for operations during the manufacturing of an electronic display. A conformable material is formed in regions between LED dies on a carrier substrate and over the LED dies. A mask is applied over the conformable material to selectively cover the conformable material. Portions of the conformable material are exposed to light to selectively cure or not cure the portions of the conformable material. The conformable material between the LED dies is removed to form a conformable interface layer over each of the LED dies.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: June 18, 2019
    Assignee: Facebook Technologies, LLC
    Inventors: Oscar Torrents Abad, Tilman Zehender, Pooya Saketi, Karsten Moh
  • Patent number: 10312103
    Abstract: A method for forming fins includes forming a three-color hardmask fin pattern on a fin base layer. The three-color hardmask fin pattern has hardmask fins of three mutually selectively etchable compositions. A region on the three-color hardmask fin pattern is masked, leaving one or more fins of a first color exposed. All exposed fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color. The mask and all fins of a second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: June 4, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sean D. Burns, Nelson M. Felix, Chi-Chun Liu, Yann A. M. Mignot, Stuart A. Sieg
  • Patent number: 10301580
    Abstract: A composition for cleaning integrated circuit substrates, the composition comprising: water; an oxidizer comprising an ammonium salt of an oxidizing species; a corrosion inhibitor comprising a primary alkylamine having the general formula: R?NH2, wherein R? is an alkyl group containing up to about 150 carbon atoms and will more often be an aliphatic alkyl group containing from about 4 to about 30 carbon atoms; optionally, a water-miscible organic solvent; optionally, an organic acid; optionally, a buffer species; optionally, a fluoride ion source; and optionally, a metal chelating agent.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: May 28, 2019
    Assignee: VERSUM MATERIALS US, LLC
    Inventors: Wen Dar Liu, Yi-Chia Lee, Tianniu Chen, William Jack Casteel, Jr., Seiji Inaoka, Gene Everad Parris
  • Patent number: 10262869
    Abstract: A planarization method includes providing a substrate having a semiconductor structure formed thereon. A dielectric layer is formed on the substrate, and a mask layer is formed on the dielectric layer. A first chemical mechanical polishing process is performed to remove a portion of the mask layer thereby forming an opening directly over the semiconductor structure and exposing the dielectric layer. A first etching process is performed to anisotropically remove a portion of the dielectric layer from the opening. The mask layer is then removed and a second chemical mechanical polishing process is then performed.
    Type: Grant
    Filed: February 25, 2018
    Date of Patent: April 16, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Jen-Chieh Lin, Lee-Yuan Chen, Wen-Chin Lin, Chi-Lune Huang, Pi-Hung Chuang, Tai-Lin Chen, Sun-Hong Chen
  • Patent number: 10256111
    Abstract: A method for polishing dies locations on a substrate with a polishing module. A thickness at selected locations on the substrate is premeasured at a metrology station, each location corresponding to a location of a single die. The thickness obtained by the metrology station for the selected locations of the substrate is provided to a controller of a polishing module. The thickness corrections for each selected location on the substrate are determined. A polishing step in a polishing recipe is formed from the thickness correction for each selected location. A polishing parameter for each die location is calculated for the recipe.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: April 9, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Eric Lau, King Yi Heung, Charles C. Garretson, Jun Qian, Thomas H. Osterheld, Shuchivrat Datar, David Chui
  • Patent number: 10252396
    Abstract: The present disclosure relates to polishing pads which include a polishing layer, wherein the polishing layer includes a working surface and a second surface opposite the working surface. The working surface includes at least one of a plurality of precisely shaped pores and a plurality of precisely shaped asperities. The present disclosure further relates to a polishing system, the polishing system includes the preceding polishing pad and a polishing solution. The present disclosure relates to a method of polishing a substrate, the method of polishing including: providing a polishing pad according to any one of the previous polishing pads; providing a substrate, contacting the working surface of the polishing pad with the substrate surface, moving the polishing pad and the substrate relative to one another while maintaining contact between the working surface of the polishing pad and the substrate surface, wherein polishing is conducted in the presence of a polishing solution.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: April 9, 2019
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Duy K. Lehuu, Kenneth A. P. Meyer, Moses M. David