Abstract: Polishing liquid comprising abrasive grains, a phosphonic acid compound having a molecular weight of 210 or more, and at least one selected from the group consisting of amino acids and amino acid derivatives, in which a silanol group density of the abrasive grains is 6.5 groups/nm2 or less, and a degree of association of the abrasive grains is 1.5 or more.

Abstract: Described herein are novel emulsion liquid membranes useful for extracting pollutants from industrial wastewater and water. The emulsion liquid membranes include, in various phases, at least one of nanoparticles, an ionic liquid, and combinations of nanoparticles and ionic liquids. Use of the present emulsion liquid membranes enhances the separation and the stability of the ELM method for pollutant extraction and recovery from wastewater and water.

Abstract: In one embodiment, a semiconductor device includes a first interconnection including a first extending portion extending in a first direction, and a first curved portion curved with respect to the first extending portion. The device further includes a second interconnection including a second extending portion extending in the first direction and adjacent to the first extending portion in a second direction, and a second curved portion curved with respect to the second extending portion. The device further includes a first plug provided on the first curved portion, or on a first non-opposite portion included in the first extending portion and not opposite to the second extending portion in the second direction. The device further includes a second plug provided on the second curved portion, or on a second non-opposite portion included in the second extending portion and not opposite to the first extending portion in the second direction.

Abstract: Techniques for fabricating a package substrate comprising a via, a conductive line, and a pad are described. The package substrate can be included in a semiconductor package. For one technique, a package substrate includes: a pad in a dielectric layer; a via; and a conductive line. The via and the conductive line can be part of a structure. Alternatively, the conductive line can be adjacent to the via. The dielectric layer can include a pocket above the pad. One or more portions of the via may be formed in the pocket above the pad. Zero or more portions of the via can be formed on the dielectric layer outside the pocket. In some scenarios, no pad is above the via. The package substrate provides several advantages. One exemplary advantage is that the package substrate can assist with increasing an input/output density per millimeter per layer (IO/mm/layer) of the package substrate.

Abstract: A semiconductor chip includes; an intermetal dielectric (IMD) layer on a substrate, an uppermost insulation layer on the IMD layer, the uppermost insulation layer having a dielectric constant different from a dielectric constant of the IMD layer, a metal wiring in the IMD layer, the metal wiring including a via contact and a metal pattern, a metal pad in the uppermost insulation layer, the metal pad being electrically connected to the metal wiring, and a bump pad on the metal pad. An interface portion between the IMD layer and the uppermost insulation layer is disposed at a height of a portion between an upper surface and a lower surface of an uppermost metal pattern in the IMD layer.

Abstract: A semiconductor cleaning agent containing a sulfonic acid group-containing polymer, wherein a content of at least one metal selected from the group consisting of Na, Al, K, Ca and Fe is 0.7 ppm or less.

Abstract: A method of defining a pattern includes forming a plurality of cut shapes and a first plurality of openings within a first layer of a multi-layer hard mask to expose first portions of the second layer. A plurality of etch stops is formed by implanting an etch rate modifying species in a portion of the plurality of cut shapes. The first layer is directionally etched at the plurality of cut shapes such that the plurality of etch stops remain. A spacer layer is formed on the first layer and the first portions. A second plurality of openings is formed within the spacer layer to expose second portions of the second layer. The spacer layer is directionally etched to remove the spacer layer from sidewalls of the plurality of etch stops. Portions of the second layer exposed through the first plurality of openings and the second plurality of openings are etched.

Abstract: A substrate cleaning method according to an aspect of the present disclosure includes: supplying a film-forming treatment liquid containing a volatile component to a substrate to form a film on the substrate; supplying a peeling treatment liquid, which peels off a treatment film from the substrate, to the treatment film formed by solidifying or curing the film-forming treatment liquid on the substrate due to volatilization of the volatile component; and supplying a hydrophobic liquid, which hydrophobizes the substrate, to the substrate to which the peeling treatment liquid has been supplied.

Abstract: To terminate polishing at an appropriate position, an end point position of the polishing is sensed. According to one embodiment, a method that chemomechanically polishes a substrate including a functional chip is provided. The method includes: a step of disposing the functional chip on the substrate; a step of disposing an end point sensing element on the substrate; a step of sealing the substrate on which the functional chip and the end point sensing element are disposed with an insulating material; a step of polishing the insulating material; and a step of sensing an end point of the polishing based on the end point sensing element while the insulating material is polished.

Abstract: To provide a touch sensor including a tail having a terminal protective layer that allows smooth insertion into or removal from a circuit board without causing any problem, which is likely to occur in a typical terminal protective layer provided on a terminal at a distal end of a tail of a touch sensor used for, for example, input operations of various electronic devices. A touch sensor having a plurality of sensor electrodes and a plurality of wires on a single substrate film includes a body including a flat portion and a deformed portion, which is three-dimensionally shaped relative to the flat portion surrounding the deformed portion and has an operation surface having the sensor electrodes, and a tail projecting from the body and having a terminal to connect the wires to a circuit board. The terminal has a terminal protective layer protecting the wires.

Abstract: A neutral to alkaline chemical mechanical composition for polishing tungsten includes, as initial components: water; an oxidizing agent selected from an iodate compound, a periodate compound and mixtures thereof; colloidal silica abrasive particles including a nitrogen-containing compound; optionally, a pH adjusting agent; and, optionally, a biocide. The chemical mechanical polishing method includes providing a chemical mechanical polishing pad, having a polishing surface; creating dynamic contact at an interface between the polishing pad and the substrate; and dispensing the neutral to alkaline chemical mechanical polishing composition onto the polishing surface at or near the interface between the polishing pad and the substrate; wherein some of the tungsten is polished away from the substrate and, further, to at least inhibit static etch of the tungsten.

Abstract: The present disclosure provides a method for fabricating a semiconductor structure, including forming an inter dielectric layer over a first region and a second region of a substrate, wherein the second region is adjacent to the first region, forming a high-k material over the inter dielectric layer in the first region and the second region, forming an oxygen capturing layer over the high-k material in the first region, and applying oxidizing agent over the oxygen capturing layer.

Abstract: A chemical mechanical polishing apparatus includes a fixing portion; and a rotary body module including a rotating shaft rotatably installed on the fixing portion, a first rotating unit connected to the rotating shaft and on which a wafer is mounted, and a second rotating unit disposed around the first rotating unit and on which a retainer ring is mounted, wherein the fixing portion comprises a first driving member disposed above the first rotating unit and a second driving member disposed above the second rotating unit, wherein the first and second driving members are comprised of a magnet or an electromagnet, wherein a first magnet, disposed opposite to the first driving member, is provided in the first rotating unit, and a second magnet, disposed opposite to the second driving member, is provided in the second rotating unit, and wherein the first rotating unit and the second rotating unit are independently tilted.

Abstract: Disclosed are a photoresist composition, a pixel definition structure and a manufacturing method thereof, and a display panel. The photoresist composition includes an organic film-forming resin, a superhydrophobic polymerizable monomer, a polyfunctional crosslinkable polymerizable monomer, a photoinitiator, an additive and a solvent.

Abstract: A semiconductor cleaning agent containing a sulfonic acid group-containing polymer, wherein a content of at least one metal selected from the group consisting of Na, Al, K, Ca and Fe is 0.7 ppm or less.

Abstract: A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view.

Abstract: Provided are a method of polishing a silicon wafer and a method of producing a silicon wafer which can reduce the formation of step-forming microdefects on a silicon wafer. The method includes: a double-side polishing step of performing polishing on front and back surfaces of a silicon wafer; a notch portion polishing step of performing polishing on a beveled portion of a notch portion of the silicon wafer after the double-side polishing step; a peripheral beveled portion polishing step of performing polishing on the beveled portion on the periphery of the silicon wafer other than the beveled portion of the notch portion after the notch portion polishing step; and a finish polishing step of performing finish polishing on the front surface of the silicon wafer after the peripheral beveled portion polishing step. The notch portion polishing step is performed in a state where the front surface is wet with water.

Abstract: Devices and methods that include for configuring a profile of a liner layer before filling an opening disposed over a semiconductor substrate. The liner layer has a first thickness at the bottom of the opening and a second thickness a top of the opening, the second thickness being smaller that the first thickness. In an embodiment, the filled opening provides a contact structure.

Abstract: In one embodiment, a semiconductor wafer includes a first substrate, a first insulator provided on the first substrate, and a plurality of first pads provided in the first insulator. The wafer further includes a second insulator provided on the first insulator, a plurality of second pads provided on the first pads in the second insulator, a stacked film alternately including a plurality of first insulating layers and a plurality of second insulating layers provided in the second insulator, and a second substrate provided on the second insulator. Furthermore, the first insulator and the second insulator are connected to each other between an edge face of the first insulator and an edge face of the second insulator, and the second insulator intervenes between the first insulator and the stacked film at the edge faces of the first and second insulators.

Abstract: Provided herein are compositions comprising a first colloidal silica particle that is not surface-modified and a second colloidal silica particle that is surface modified to carry a negative charge. Also provided herein are methods for selectively removing HfO2 or SiO2 from a surface.

Abstract: A DIMA semiconductor structure is disclosed. The DIMA semiconductor structure includes a frontend including a semiconductor substrate, a transistor switch of a memory cell coupled to the semiconductor substrate and a computation circuit on the periphery of the frontend coupled to the semiconductor substrate. Additionally, the DIMA includes a backend that includes an RRAM component of the memory cell that is coupled to the transistor switch.

Abstract: An object of the present invention is to provide a nanobubble-containing inorganic oxide fine particle dispersion having excellent concentration stability in a process used as an abrasive. The object is achieved by the nanobubble-containing inorganic oxide fine particle dispersion including: inorganic oxide fine particles having an average particle size of 1 to 500 nm and containing fine particles containing Ce; and nanobubbles having an average cell size of 50 to 500 nm and being at least one non-oxidizing gas selected from a group consisting of N2 and H2.

Abstract: A method of manufacturing a semiconductor device includes: forming a first stack structure; forming first holes penetrating the first stack structure; forming a second stack structure on the first stack structure; forming second holes penetrating the second stack structure; measuring first direction distances between edges of the first holes and edges of the second holes; and correcting a first direction position at which the second holes are to be formed. The second holes may include one of a first shift hole shifted in a positive first direction from a first hole and a second shift hole shifted in a negative first direction from a first hole.

Abstract: The invention provides a method for polishing or planarizing a substrate. First, the method comprises attaching a polymer-polymer composite polishing pad to a polishing device. The polishing pad has a polymer matrix and fluoropolymer particles embedded in the polymeric matrix. The fluoropolymer particles have a zeta potential more negative than the polymeric matrix. Cationic particle-containing slurry is applied to the polishing pad. Conditioning the polymer-polymer composite polishing pad exposes the fluoropolymer particles to the polishing surface and creates fluoropolymer-containing debris particles in the slurry. Polishing or planarizing the substrate with the increased electronegativity from the fluoropolymer at the polishing surface and in the fluoropolymer-containing debris particles stabilizes the cationic particle-containing slurry to decreases the precipitation rate of the cationic particle-containing slurry.

Abstract: An integrated circuit structure includes a first low-k dielectric layer having a first k value, and a second low-k dielectric layer having a second k value lower than the first k value. The second low-k dielectric layer is overlying the first low-k dielectric layer. A dual damascene structure includes a via with a portion in the first low-k dielectric layer, and a metal line over and joined to the via. The metal line includes a portion in the second low-k dielectric layer.

Abstract: A semiconductor structure includes a substrate including a first surface; a dielectric layer disposed over the first surface of the substrate; a first conductive line surrounded by the dielectric layer and extended over the first surface of the substrate; a second conductive line disposed adjacent to the first conductive line, surrounded by the dielectric layer and extended parallel to the first conductive line; a conductive via disposed over the first conductive line and extended through the dielectric layer; and a cross section of the conductive via substantially parallel to the first surface of the substrate, wherein the cross section of the conductive via is at least partially protruded from the first conductive line towards the second conductive line. Further, a method of manufacturing the semiconductor structure is also disclosed.

Abstract: Methods for polishing dielectric layers using an auto-stop slurry in forming semiconductor devices, such as three-dimensional (3D) memory devices, are provided. For example, a stack structure is formed in a staircase region and a core array region. The stack structure includes a plurality of interleaved first material layers and second material layers. Edges of the interleaved first material layers and second material layers define a staircase structure on a side of the stack structure in the staircase region. A dielectric layer is formed over the staircase region and a peripheral region outside the stack structure. The dielectric layer includes a protrusion from the stack structure. The dielectric layer is polished using an auto-stop slurry to remove the protrusion of the dielectric layer.

Abstract: An object of the present invention is to provide an abrasive slurry regeneration method capable of efficiently regenerating an abrasive slurry having a high polishing rate. The abrasive slurry regeneration method is an abrasive slurry regeneration method for polishing a polishing target containing silicon oxide as a main component using an abrasive slurry containing abrasive particles and a plurality of kinds of additives and then regenerating a collected abrasive slurry, characterized by including a regeneration step of collecting an additive having a molecular weight of 500 or more and an additive adsorbed by the abrasive particles among additives contained in the collected abrasive slurry together with the abrasive particles while an abrasive concentration (% by mass) is maintained within a range of 0.2 to 3000% with respect to an abrasive concentration (% by mass) of an unused abrasive slurry when being used for polishing a polishing target.

Abstract: Semiconductor devices can be formed over a semiconductor substrate, and interconnect-level dielectric material layers embedding metal interconnect structures can be formed thereupon. In one embodiment, a pad-connection-via-level dielectric material layer, a proximal dielectric diffusion barrier layer, and a pad-level dielectric material layer can be formed. Bonding pads surrounded by dielectric diffusion barrier portions can be formed in the pad-level dielectric material layer. In another embodiment, a layer stack of a proximal dielectric diffusion barrier layer and a pad-and-via-level dielectric material layer can be formed. Integrated pad and via cavities can be formed through the pad-and-via-level dielectric material layer, and can be filled with bonding pads containing dielectric diffusion barrier portions and integrated pad and via structures.

Abstract: A structure and method use different stress-inducing isolation dielectrics to induce appropriate stresses in different polarity FETs to improve performance of both type FETs. The structure may include a first stress-inducing isolation dielectric surrounding and contacting a first active region for a p-type field effect transistor (PFET), and a second stress-inducing isolation dielectric surrounding and contacting a second active region for an n-type field effect transistor (NFET). The first and second stress-inducing isolation dielectrics induce different types of stress, thus improving performance of both polarity of FETs.

Abstract: A semiconductor device including a semiconductor die, an encapsulant and a redistribution structure is provided. The encapsulant laterally encapsulates the semiconductor die. The redistribution structure is disposed on the semiconductor die and the encapsulant and is electrically connected to the semiconductor die. The redistribution structure includes a dielectric layer, a conductive via in the dielectric layer and a redistribution wiring covering the conductive via and a portion of the dielectric layer. The conductive via includes a pillar portion embedded in the dielectric layer and a protruding portion protruding from the pillar portion, wherein the protruding portion has a tapered sidewall.

Abstract: An inner-periphery-side cutoff part where a polishing surface of an upper plate inclines upward toward an inner periphery part of the upper plate and an inner-periphery-side cutoff part where a polishing surface of a lower plate inclines downward toward an inner periphery part of the lower plate are respectively formed on the respective inner periphery parts of the upper plate and the lower plate, or an outer-periphery-side cutoff part where the polishing surface of the upper plate inclines upward toward an outer periphery part of the upper plate and an outer-periphery-side cutoff part where the polishing surface of the lower plate inclines downward toward an outer periphery part of the lower plate are respectively formed on the respective outer periphery parts of the upper plate and the lower plate, or all of them are formed thereon.

Abstract: Semiconductor devices can be formed over a semiconductor substrate, and interconnect-level dielectric material layers embedding metal interconnect structures can be formed thereupon. In one embodiment, a pad-connection-via-level dielectric material layer, a proximal dielectric diffusion barrier layer, and a pad-level dielectric material layer can be formed. Bonding pads surrounded by dielectric diffusion barrier portions can be formed in the pad-level dielectric material layer. In another embodiment, a layer stack of a proximal dielectric diffusion barrier layer and a pad-and-via-level dielectric material layer can be formed. Integrated pad and via cavities can be formed through the pad-and-via-level dielectric material layer, and can be filled with bonding pads containing dielectric diffusion barrier portions and integrated pad and via structures.

Abstract: A display device includes: a substrate; an inorganic insulating layer disposed on the substrate; a conductor disposed on the inorganic insulating layer; and an organic insulating layer disposed on the conductor, where an opening is defined through the organic insulating layer to expose a part of the upper surface of the conductor, and at least one material selected from a siloxane, a thiol, a phosphate, a disulfide including a sulfur series, and an amine is bonded on the part of the upper surface of the conductor exposed through the opening.

Abstract: An electrode structure includes: a first nonconductive layer; a first conductive layer disposed on the first nonconductive layer; a second nonconductive layer disposed on the first conductive layer; a second conductive layer disposed on the second nonconductive layer; and a third nonconductive layer disposed on the second conductive layer, where at least one of the first conductive layer and the second conductive layer includes a two-dimensional conductive material.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first metal layer over a substrate, forming a dielectric layer over the first metal layer. The method includes forming a trench in the dielectric layer, and performing a surface treatment process on a sidewall surface of the trench to form a hydrophobic layer. The hydrophobic layer is formed on a sidewall surface of the dielectric layer. The method further includes depositing a metal material in the trench and over the hydrophobic layer to form a via structure.

Abstract: A radiation-curable ink jet composition includes vinyl methyl oxazolidinone and a vinyl ether group-containing (meth)acrylate represented by the following formula (1): H2C?CR1—CO—OR2—O—CH?CH—R3 (where, R1 is a hydrogen atom or a methyl group, R2 is a divalent C2-C20 organic residue, and R3 is a hydrogen atom or a monovalent C1-C11 organic residue).

Abstract: A radiation-curable ink jet composition includes a monofunctional (meth)acrylate monomer and vinyl methyl oxazolidinone.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first well, a second well, an isolation structure, a first field plate, a gate structure, a drain structure, and a source structure. The first well and the second well adjoin each other. The first well and the second well are disposed in the substrate. The isolation structure is disposed on the first well. The first field plate is disposed on the isolation structure. The gate structure crosses the first well and the second well, and an opening is defined between the first field plate and the gate structure to expose an edge of the isolation structure adjacent to the gate structure. The drain structure is disposed in the first well. The source structure is disposed in the second well.

Abstract: The present invention relates to a polishing slurry composition for an STI process, the polishing slurry composition comprising: a polishing solution including polishing particles; and an additive solution containing a nitride film polishing barrier inclusive of a polymer having an amide bond.

Abstract: In a substrate processing apparatus, a processing chamber, in which a target substrate is disposed and substrate processing is performed on the target substrate, is provided. A consumable part is disposed in the processing chamber and consumed by the substrate processing. A supply unit is configured to supply an ionic liquid in response to a consumption of the consumable part. A drive unit is configured to drive the consumable part by using the ionic liquid supplied from the supply unit.

Abstract: The present disclosure relates to an installation fixture for an electrode plate of a semiconductor equipment. The installation fixture includes: an alignment assembly, including a support disc and at least two guide shafts, where the support disc is provided with at least two positioning holes, at least two fixing holes and at least two mounting holes; a drive assembly, including a mounting plate assembly, at least two support rods and a drive rod assembly, where the support rods are connected to the mounting plate assembly, and one end of each of the support rods is connected to one of the mounting holes; and the drive rod assembly is connected to the mounting plate assembly; and a support assembly, including at least two support bases, where each of the support bases is provided with a mounting groove.

Abstract: A double-side polishing method, including: simultaneously polishing both surfaces of a semiconductor wafer by holding the semiconductor wafer in a carrier, interposing the held semiconductor wafer between an upper turn table and a lower turn table each having a polishing pad attached thereto, and bringing both surfaces of the semiconductor wafer into sliding contact with the polishing pads, wherein the semiconductor wafer is polished under a condition that a thickness A (mm) of the polishing pad attached to the upper turn table and a thickness B (mm) of the polishing pad attached to the lower turn table satisfy relations of 1.0?A+B?2.0 and A/B>1.0. This provides a double-side polishing method capable of obtaining a semiconductor wafer in which F-ZDD<0 while controlling the GBIR value to be equal to or smaller than a required value.

Abstract: A three-dimensional semiconductor memory device may include horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other, memory structures provided on the horizontal patterns, respectively, each of the memory structures including a three-dimensional arrangement of memory cells. Penetrating insulating patterns and separation structures may isolate the horizontal patterns from one another. Through vias may extend through the penetrating insulating patterns to connect logic circuits of the peripheral circuit structure to the memory structure.

Abstract: Provided is a cleaning liquid composition which is useful for cleaning of a substrate or the like that has been subjected to a chemical mechanical polishing (CMP) process, etc in the production steps of an electronic device such as a semiconductor element. A cleaning liquid composition according to the present invention is used for the purpose of cleaning a substrate that has a Cu wiring, and comprises one or more basic compounds and one or more nitrogen-containing monocyclic heterocyclic aromatic compounds that contain one or more carboxyl groups or ester groups, provided that in cases where one or more amino groups are contained therein, only amino groups directly bonded to a nitrogen-containing heterocyclic rind are contained. This cleaning liquid composition has a hydrogen ion concentration (pH) of 8-12.

Abstract: Processes, compositions and agents are included for inhibiting corrosion in various substrates, for example metal substrates. Corrosion inhibitors include organometallic polymers such as metal-organic frameworks (MOFs), including compositions and processes comprising MOFs for inhibiting corrosion in metal substrates. In some aspects, a method of protecting a substrate from corrosion includes applying a protective composition including a corrosion inhibitor to the surface of a substrate, where the corrosion inhibitor includes a metal organic framework (MOF).

Abstract: a device and a method are disclosed to detect obstructed objects, usually behind a wall or other similar surface. The device may be used by dragging it across the surface of the wall to scan, detect and display the objects behind the wall. The types of hidden objects and materials they are made of vary and may include wooden or metal studs used in building construction, electrical AC or DC wires and conduits, metal rebar and the like. Each type of material may need a different type of sensor to be detected. In some examples, the device may include memory to record the objects detected and display them on the screen in a persistent manner. The objects may be displayed via graphics that are similar to the real objects that were detected. In effect, the device may display a picture of what is hidden behind the wall.

Abstract: A method of manufacturing a semiconductor device includes the following steps. A device wafer having a product-obtaining part and an edge part surrounding the product-obtaining part is provided. A passivation layer is formed to cover the device wafer. A first oxide cap layer is formed to cover the passivation layer. An edge trimming process is performed to polish an edge part of the first oxide cap layer, an edge part of the passivation layer and the edge part of the device wafer. A removing process is performed to remove the first oxide cap layer after the edge trimming process is performed. A second oxide cap layer is formed to cover the first oxide cap layer and the edge part of the device wafer.

Abstract: A device includes an interconnect structure over a substrate, multiple first conductive pads over and connected to the interconnect structure, a planarization stop layer extending over the sidewalls and top surfaces of the first conductive pads of the multiple first conductive pads, a surface dielectric layer extending over the planarization stop layer, and multiple first bonding pads within the surface dielectric layer and connected to the multiple first conductive pads.

Abstract: An acidic slurry composition for use in chemical-mechanical polishing including an acid pH adjuster and a cationic polishing suppressant comprising a quaternized aromatic heterocycle. The quaternized aromatic heterocycle imparts a polishing selectivity of silica over crystalline silicon of at least 100.