Simultaneous (e.g., Chemical-mechanical Polishing, Etc.) Patents (Class 438/692)
  • Patent number: 10262869
    Abstract: A planarization method includes providing a substrate having a semiconductor structure formed thereon. A dielectric layer is formed on the substrate, and a mask layer is formed on the dielectric layer. A first chemical mechanical polishing process is performed to remove a portion of the mask layer thereby forming an opening directly over the semiconductor structure and exposing the dielectric layer. A first etching process is performed to anisotropically remove a portion of the dielectric layer from the opening. The mask layer is then removed and a second chemical mechanical polishing process is then performed.
    Type: Grant
    Filed: February 25, 2018
    Date of Patent: April 16, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Jen-Chieh Lin, Lee-Yuan Chen, Wen-Chin Lin, Chi-Lune Huang, Pi-Hung Chuang, Tai-Lin Chen, Sun-Hong Chen
  • Patent number: 10252396
    Abstract: The present disclosure relates to polishing pads which include a polishing layer, wherein the polishing layer includes a working surface and a second surface opposite the working surface. The working surface includes at least one of a plurality of precisely shaped pores and a plurality of precisely shaped asperities. The present disclosure further relates to a polishing system, the polishing system includes the preceding polishing pad and a polishing solution. The present disclosure relates to a method of polishing a substrate, the method of polishing including: providing a polishing pad according to any one of the previous polishing pads; providing a substrate, contacting the working surface of the polishing pad with the substrate surface, moving the polishing pad and the substrate relative to one another while maintaining contact between the working surface of the polishing pad and the substrate surface, wherein polishing is conducted in the presence of a polishing solution.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: April 9, 2019
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Duy K. Lehuu, Kenneth A. P. Meyer, Moses M. David
  • Patent number: 10256111
    Abstract: A method for polishing dies locations on a substrate with a polishing module. A thickness at selected locations on the substrate is premeasured at a metrology station, each location corresponding to a location of a single die. The thickness obtained by the metrology station for the selected locations of the substrate is provided to a controller of a polishing module. The thickness corrections for each selected location on the substrate are determined. A polishing step in a polishing recipe is formed from the thickness correction for each selected location. A polishing parameter for each die location is calculated for the recipe.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: April 9, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Eric Lau, King Yi Heung, Charles C. Garretson, Jun Qian, Thomas H. Osterheld, Shuchivrat Datar, David Chui
  • Patent number: 10236436
    Abstract: An element manufacturing method includes a first step of obtaining a thickness distribution in a planar direction of a workpiece, a second step of calculating a processing amount distribution from a difference between the thickness distribution and a desired film-thickness distribution, a third step of locally processing the workpiece in accordance with the processing amount distribution, a fourth step of, after the third step, dividing an inside of a plane of the workpiece into a plurality of element parts and forming an electrode in each of the element parts, and a fifth step of making the plurality of element parts apart from each other to form a plurality of elements.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: March 19, 2019
    Assignee: KYOCERA CORPORATION
    Inventor: Keiichiro Watanabe
  • Patent number: 10214663
    Abstract: Described are a chemical-mechanical polishing (CMP) composition comprising abrasive particles in the form of organic/inorganic composite particles as well as the use of said composite particles as abrasive particles in a CMP composition and processes for the manufacture of a semiconductor device comprising chemical mechanical polishing of a substrate in the presence said CMP composition.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: February 26, 2019
    Assignees: ST. LAWRENCE NANOTECHNOLOGY, BASF TAIWAN LTD., BASF CORPORATION
    Inventors: Yongqing Lan, Bastian Marten Noller, Yuzhuo Li, Liang Jiang, Daniel Kwo-Hung Shen, Reza Golzarian
  • Patent number: 10157776
    Abstract: A method for manufacturing a semiconductor device includes forming a hard mask layer overlying a device layer of a semiconductor device, a mandrel underlayer over hard mask layer, and a mandrel layer over mandrel underlayer. The mandrel layer has a plurality of mandrel lines extending along a first direction. A plurality of openings are formed in mandrel underlayer extending in a second direction substantially perpendicular to first direction. A spacer layer is formed over mandrel underlayer and layer. Spacer layer fills plurality of openings in underlayer. Portions of spacer layer are removed to expose an upper surface of underlayer and mandrel layer, and mandrel layer is removed. By using remaining portions of spacer layer as a mask, underlayer and hard mask layer are removed, to form a hard mask pattern with first hard mask pattern lines extending along first direction and second hard mask pattern lines extending along second direction.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yan-Jhi Huang, Yu-Yu Chen
  • Patent number: 10147647
    Abstract: A method of detaching a growth substrate from a layer sequence includes introducing at least one wafer composite into an etching bath containing an etching solution such that the etching solution is located at least in regions within separating trenches, repeatedly varying a pressure of a base pressure prevailing in the etching bath with at least one pressure variation device, and detaching the growth substrate, wherein at least one of 1-3 is satisfied: 1) a buffer chamber attached to the etching bath and connected thereto is provided and the volume variation is effected by a movement of a piston or hydraulic plunger introduced into the buffer chamber, 2) the volume variation is at least partly effected with a compressor attached to the etching bath, and 3) the pressure variation is at least partly effected by at least one of removal of a gas and a liquid from the etching bath or by addition of at least one of the gas and the liquid thereto.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: December 4, 2018
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Christoph Klemp, Marco Englhard
  • Patent number: 10134614
    Abstract: A projecting/receiving unit (52) projects a laser light to a peripheral portion (30) and receives the reflected light while a liquid is being fed to a substrate (14) and is flowing on the peripheral portion (30). A signal processing controller (54) processes the electric signal of the reflected light to decide the state of the peripheral portion (30). The state of the peripheral portion being polished is monitored. Moreover, the polish end point is detected. A transmission wave other than the laser light may also be used. The peripheral portion (30) may also be enclosed by a passage forming member thereby to form a passage properly. The peripheral portion can be properly measured even in the situation where the liquid is flowing on the substrate peripheral portion.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: November 20, 2018
    Assignee: Ebara Corporation
    Inventors: Mitsuo Tada, Yasunari Suto, Hirofumi Ichihara, Kenya Ito, Tamami Takahashi
  • Patent number: 10128147
    Abstract: Semiconductor structures include a patterned interlayer dielectric overlaying a semiconductor substrate. The interlayer dielectric includes a first dielectric layer and at least one additional dielectric layer disposed on the first dielectric layer, wherein the patterned interlayer dielectric comprises at least one opening extending through the interlayer dielectric to the semiconductor substrate. Chemically enriched regions including ions of Si, P, B, N, O and combinations thereof are disposed in surfaces of the first dielectric layer and the at least one dielectric layer defined by the at least one opening. Also described are methods of for forming an interconnect structure in a semiconductor structure.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: November 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Roger A. Quon, Terry A. Spooner, Wei Wang, Chih-Chao Yang
  • Patent number: 10121651
    Abstract: A technique capable of forming a side wall of a gate electrode having high resistance-to-etching and low leakage current is provided. A method of manufacturing a semiconductor device according to the technique includes: (a) loading a substrate into a processing space in a process vessel, the substrate having thereon a gate electrode and an insulating film formed on a side surface of the gate electrode as a side wall; and (b) forming an etching-resistant film containing carbon and nitrogen on a surface of the insulating film by supplying a carbon-containing gas into the processing space.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: November 6, 2018
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Arito Ogawa, Shin Hiyama
  • Patent number: 10077381
    Abstract: A polishing slurry composition is provided. The polishing slurry composition includes at least two types of abrasive particles among first abrasive particles, second abrasive particles, and third abrasive particles, and an oxidizer. A peak-to-valley roughness Rpv decreases when a contact area between the abrasive particles and a tungsten-containing film increases.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: September 18, 2018
    Assignee: KCTech Co., Ltd.
    Inventors: Dong Kyu Choi, Young Ho Yoon, Hyun Goo Kong, Jin Sook Hwang, Han Teo Park
  • Patent number: 10062566
    Abstract: A semiconductor device, comprising a base substrate, a buffer layer and a polysilicon layer film, wherein the base substrate, the buffer layer and the polysilicon layer film being laminated sequentially, and wherein regularly arranged first grooves being provided on a surface of the buffer layer contacting the polysilicon film; the polysilicon film being formed, by applying crystallization treatment, through an optical annealing process, to an amorphous silicon film on the buffer layer having regularly arranged first grooves.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: August 28, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wenqing Xu, Chunping Long
  • Patent number: 10062759
    Abstract: A MOSFET using a SiC substrate has a problem that a carbon-excess layer is formed on a surface by the application of mechanical stress due to thermal oxidation and the carbon-excess layer degrades mobility of channel carriers. In the invention, (1) a layer containing carbon-carbon bonds is removed; (2) a gate insulating film is formed by a deposition method; and (3) an interface between a crystal surface and the insulating film is subjected to an interface treatment at a low temperature for a short time. Due to this, the carbon-excess layer causing characteristic degradation is effectively eliminated, and at the same time, dangling bonds can be effectively eliminated by subjecting an oxide film and an oxynitride film to an interface treatment.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: August 28, 2018
    Assignee: HITACHI, LTD.
    Inventors: Digh Hisamoto, Keisuke Kobayashi, Naoki Tega, Toshiyuki Ohno, Hirotaka Hamamura, Mieko Matsumura
  • Patent number: 10056277
    Abstract: A polishing method capable of obtaining a stable film thickness without being affected by a difference in measurement position is disclosed. The polishing method includes: rotating a polishing table that supports a polishing pad; pressing the surface of the wafer against the polishing pad; obtaining a plurality of film-thickness signals from a film thickness sensor during a latest predetermined number of revolutions of the polishing pad, the film thickness sensor being installed in the polishing table; determining a plurality of measured film thicknesses from the plurality of film-thickness signals; determining an estimated film thickness at a topmost portion of the raised portion based on the plurality of measured film thicknesses; and monitoring polishing of the wafer based on the estimated film thickness at the topmost portion of the raised portion.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: August 21, 2018
    Assignee: EBARA CORPORATION
    Inventors: Yoichi Kobayashi, Yoichi Shiokawa, Katsuhide Watanabe
  • Patent number: 10043678
    Abstract: The present invention relates to a slurry composition for reducing scratches generated when polishing the metal film in a manufacturing process of a semiconductor integrated circuit, by lowering frictional force so that a temperature of the composition which may rise during the polishing is lowered, the thermal stability of the slurry is improved and the size increase of particles in the slurry is suppressed, and a method for reducing scratches using the same. The method comprises the steps of applying a slurry composition for polishing a metal film to a substrate on which the metal film is formed, the slurry composition containing an organic solvent including a nitrogen atom and a glycol-based organic solvent; and making a polishing pad to be contacted to the substrate and moving the polishing pad with respect to the substrate, thereby removing at least part of the metal film from the substrate.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: August 7, 2018
    Assignee: DONGJIN SEMICHEM CO., LTD.
    Inventors: Chang Yong Park, Jong Dai Park, Jong Chul Shin, Jae Hyun Kim, Goo Hwa Lee, Min Sung Park
  • Patent number: 10032871
    Abstract: A MOSFET using a SiC substrate has a problem that a carbon-excess layer is formed on a surface by the application of mechanical stress due to thermal oxidation and the carbon-excess layer degrades mobility of channel carriers. In the invention, (1) a layer containing carbon-carbon bonds is removed; (2) a gate insulating film is formed by a deposition method; and (3) an interface between a crystal surface and the insulating film is subjected to an interface treatment at a low temperature for a short time. Due to this, the carbon-excess layer causing characteristic degradation is effectively eliminated, and at the same time, dangling bonds can be effectively eliminated by subjecting an oxide film and an oxynitride film to an interface treatment.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: July 24, 2018
    Assignee: HITACHI, LTD.
    Inventors: Digh Hisamoto, Keisuke Kobayashi, Naoki Tega, Toshiyuki Ohno, Hirotaka Hamamura, Mieko Matsumura
  • Patent number: 10030172
    Abstract: A polishing agent comprises: a fluid medium; an abrasive grain containing a hydroxide of a tetravalent metal element; a first additive; a second additive; and a third additive, wherein: the first additive is at least one selected from the group consisting of a compound having a polyoxyalkylene chain and a vinyl alcohol polymer; the second additive is a cationic polymer; and the third additive is an amino group-containing sulfonic acid compound.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: July 24, 2018
    Assignee: HITACHI CHEMICAL COMPANY, LTD.
    Inventors: Hisataka Minami, Tomohiro Iwano, Toshiaki Akutsu
  • Patent number: 10017669
    Abstract: A polishing composition includes crystalline metal oxide particles as abrasive grains, wherein the full width at half maximum of a peak portion having the maximum diffracted intensity in an X-ray powder diffraction pattern of the metal oxide particles is less than 1°. Thus, a polishing composition and a polishing method have high polishing speed and suppress defect generation such as a scratch and dishing, which causes to degrade reliability of a semiconductor apparatus in a polishing process of a semiconductor substrate, particularly in a chemical mechanical polishing process of a semiconductor substrate with a metal layer having tungsten, etc.; and a method produces the polishing composition.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: July 10, 2018
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventor: Yoshihiro Nojima
  • Patent number: 9982165
    Abstract: A polishing slurry for silicon, a method of polishing polysilicon, and a method of manufacturing a thin film transistor substrate, the slurry including a polishing particle; a dispersing agent including an anionic polymer, a hydroxyl acid, or an amino acid; a stabilizing agent including an organic acid, the organic acid including a carboxyl group; a hydrophilic agent including a hydrophilic group and a hydrophobic group, and water, wherein the polishing particle is included in the polishing slurry in an amount of about 0.1% by weight to about 10% by weight, based on a total weight of the slurry, a weight ratio of the polishing particle and the dispersing agent is about 1:0.01 to about 1:0.2, a weight ratio of the polishing particle and the stabilizing agent is about 1:0.001 to about 1:0.1, and a weight ratio of the polishing particle and the hydrophilic agent is about 1:0.01 to about 1:3.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: May 29, 2018
    Assignees: SAMSUNG DISPLAY CO., LTD., UBmaterials Inc.
    Inventors: Byoung-Kwon Choo, Jin-Hyung Park, Jeong-Kyun Na, Joon-Hwa Bae, Byoung-Ho Cheong, Joo-Woan Cho, In-Sun Hwang
  • Patent number: 9893116
    Abstract: A manufacturing method of an electronic device processes a surface of a first wafer, bonds a surface of a second wafer to the processed surface of the first wafer, thins the first wafer by polishing a back surface of the first wafer, the back surface being located on an opposite side of the processed surface, forms a groove along a periphery of the back surface of the thinned first wafer by using a dicing blade, attaches a protective layer to the back surface of the first wafer having the groove, via a bonding layer, and polishes a back surface of the second wafer, the back surface being located on an opposite side of the surface attached to the protective layer.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: February 13, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinya Takyu, Hideo Numata, Hiroyuki Okura
  • Patent number: 9885831
    Abstract: An silicon photonics device of hybrid waveguides having a coupling interlayer with an accurately controlled thickness and a method of making the same. The device includes a first plurality of Si waveguides formed in a SOI substrate and a first layer of SiO2 overlying the first plurality of Si waveguides and a second plurality of Si3N4 waveguides formed on the first layer of SiO2. At least one Si3N4 waveguide is disposed partially overlapping with at least one of the first plurality Si waveguides in vertical direction separated by the first layer of SiO2 with a thickness controlled no greater than 90 nm. The device includes a second layer of SiO2 overlying the second plurality of Si3N4 waveguides. The method of accurately controlling the coupling interlayer SiO2 thickness includes a multilayer SiO2/Si3N4/SiO2 hard mask process for SiO2 etching and polishing as stopping and buffering layer as well as Si waveguide etching mask.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: February 6, 2018
    Assignee: INPHI CORPORATION
    Inventors: Liang Ding, Radhakrishnan L. Nagarajan
  • Patent number: 9856401
    Abstract: Embodiments of the invention provide a polishing composition including colloidal silica, pulverized wet-process silica particles, and a water-soluble polymer compound, wherein the water-soluble polymer compound is a polymer or copolymer having a constituent unit derived from an unsaturated aliphatic carboxylic acid. Various embodiments achieve a high polishing rate and obtain a good surface smoothness and end-face shape without the use of alumina particles.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: January 2, 2018
    Assignee: YAMAGUCHI SEIKEN KOGYO CO., LTD.
    Inventors: Toru Iwata, Akira Sugawa
  • Patent number: 9812571
    Abstract: A thermal mixing process is employed to convert a portion of a silicon germanium alloy fin having a first germanium content and an overlying non-doped epitaxial silicon source material into a silicon germanium alloy source structure having a second germanium content that is less than the first germanium content, to convert another portion of the silicon germanium alloy fin and an overlying non-doped epitaxial silicon drain material into a silicon germanium alloy drain structure having the second germanium content, and to provide a tensile strained silicon germanium alloy fin portion having the first germanium content. A dopant is then introduced into the silicon germanium alloy source structure and into the silicon germanium alloy drain structure.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: November 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Pouya Hashemi, Alexander Reznicek, Joshua M. Rubin, Robin M. Schulz
  • Patent number: 9802294
    Abstract: Provided are a pressure-sensitive adhesive tape, a polishing pad, a method of manufacturing the same, a polishing device and a method of manufacturing a glass substrate. The illustrative pressure-sensitive adhesive tape may be a pressure-sensitive adhesive tape for a polishing material. The pressure-sensitive adhesive tape may be effectively fixed to a surface plate without bubbles, and have excellent resistance to water and a polishing solution and shear strength applied in a polishing process. In addition, the pressure-sensitive adhesive tape may be easily removed from a carrier or surface plate for a polishing pad without residues after polishing.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: October 31, 2017
    Assignee: LG CHEM, LTD.
    Inventors: Se Woo Yang, Suk Ky Chang, Min Soo Park
  • Patent number: 9748144
    Abstract: First and second semiconductor structures, a CESL, and an ILD layer are formed on a substrate. The first semiconductor structure includes first dummy gate, first nitride mask, and first oxide mask. The second semiconductor structure includes second dummy gate, second nitride mask, and second oxide mask. A first planarization is performed to remove a portion of the ILD layer, exposing CESL. A portion of the CESL, a portion of the ILD layer, the first and the second oxide masks are removed. A hard mask layer is formed on the first and the second nitride masks, and in a recess of the ILD layer. A second planarization is performed to remove a portion of the hard mask layer, the first and the second nitride masks, exposing first and second dummy gates. A remaining portion of the hard mask layer covers the ILD layer.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: August 29, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Ling Lin, Yi-Wen Chen, Chen-Ming Huang, Ren-Peng Huang, Ching-Fu Lin
  • Patent number: 9728622
    Abstract: Forming a dummy gate on a semiconductor device is disclosed. A first sacrificial layer is formed on a fin, and a second sacrificial layer is formed on the first sacrificial layer. A first hardmask layer is formed on the second sacrificial layer, and a second hardmask layer is formed on the first hardmask layer and patterned. The first hardmask layer is laterally recessed in a lateral direction under the second hardmask layer. The first and second sacrificial layers are etched to a corresponding width of the first hardmask layer. A spacer layer is formed on the fin, the first sacrificial layer, second sacrificial layer, the first hardmask layer and the second hardmask layer. The spacer layer is etched until it remains on a sidewall of the first sacrificial layer, the second sacrificial layer and the first hardmask layer, wherein the first and second sacrificial layers form the dummy gate.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: August 8, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
  • Patent number: 9631121
    Abstract: A polishing composition is used to polish a polishing subject having a phase change alloy. The polishing composition includes abrasive grains and a brittle film formation agent. The brittle film formation agent is at least one or more selected from a saturated monocarboxylic acid and an organophosphorus compound.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: April 25, 2017
    Assignee: FUJIMI INCORPORATED
    Inventors: Yukinobu Yoshizaki, Yoshihiro Izawa
  • Patent number: 9627216
    Abstract: Embodiments of methods for forming features in a silicon containing layer of a substrate disposed on a substrate support are provided herein. In some embodiments, a method for forming features in a silicon containing layer of a substrate disposed on a substrate support in a processing volume of a process chamber includes: exposing the substrate to a first plasma formed from a first process gas while providing a bias power to the substrate support, wherein the first process gas comprises one or more of a chlorine-containing gas or a bromine containing gas; and exposing the substrate to a second plasma formed from a second process gas while no bias power is provided to the substrate support, wherein the second process gas comprises one or more of an oxygen-containing gas or nitrogen gas, and wherein a source power provided to form the first plasma and the second plasma is continuously provided.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: April 18, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Byungkook Kong, Hoon Sang Lee, Jinsu Kim, Ho Jeong Kim, Xiaosong Ji, Hun Sang Kim, Jinhan Choi
  • Patent number: 9589799
    Abstract: Methods of forming high etch selectivity, low stress ashable hard masks using plasma enhanced chemical vapor deposition are provided. In certain embodiments, the methods involve pulsing low frequency radio frequency power while keeping high frequency radio frequency power constant during deposition of the ashable hard mask using a dual radio frequency plasma source. According to various embodiments, the low frequency radio frequency power can be pulsed between non-zero levels or by switching the power on and off. The resulting deposited highly selective ashable hard mask may have decreased stress due to one or more factors including decreased ion and atom impinging on the ashable hard mask and lower levels of hydrogen trapped in the ashable hard mask.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: March 7, 2017
    Assignee: Lam Research Corporation
    Inventors: Sirish K. Reddy, Chunhai Ji, Xinyi Chen, Pramod Subramonium
  • Patent number: 9559103
    Abstract: Provided is a memory device. The memory device includes a substrate including a cell area and a peripheral area; gate line stacks and bit line stacks configured to vertically cross in the cell area; buried contacts disposed in areas, which are simultaneously shared by neighboring gate line stacks and neighboring bit line stacks; expanded landing pads including expanded portions connected to the buried contacts and expanded over adjacent bit line stacks, and disposed in a row; landing pads spaced apart from the expanded landing pads as a column, connected to the buried contacts, and having horizontal widths smaller than those of the expanded landing pads; and first storage nodes connected to the expanded portions of the expanded landing pads, and second storage nodes connected to the landing pads.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: January 31, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Je-Min Park, Tae-Jin Park, Yong-Kwan Kim, Yoo-Sang Hwang
  • Patent number: 9533445
    Abstract: Methods for nanoimprint lithography using a deformable mold. Generally, the method includes a deformable mold fixed firmly onto a hollow mold holder around its full periphery is attached to top inner surface of the chamber and positioned underneath the transparent section. The central area of the mold is freely accessible from underneath through the opening of the mold holder. At beginning of the imprinting, the substrate with a layer of resist is positioned underneath the mold at a predetermined gap between them and a substrate is moved up to contact with the mold either under vacuum or under atmosphere. After consolidating the resist, the substrate is separated from the mold by either direct pull-down enabled by stage movement or deforming the mold enabled by differential pressure between the mold mini-chamber and the bulk volume of the chamber, or mixing of both.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: January 3, 2017
    Assignee: NANONEX CORPORATION
    Inventors: Wei Zhang, Hua Tan, Lin Hu, Stephen Y. Chou
  • Patent number: 9525041
    Abstract: A semiconductor process for forming gates with different pitches includes the following steps. A gate layer is formed on a substrate. A first mandrel and a second mandrel are respectively formed on the gate layer. A first spacer material is formed to conformally cover the first mandrel but exposing the second mandrel. A second spacer material is formed to conformally cover the first spacer material and the second mandrel. The first spacer material and the second spacer material are etched to form a first spacer beside the first mandrel and a second spacer beside the second mandrel simultaneously. The first mandrel and the second mandrel are removed. Layouts of the first spacer and the second spacer are transferred to the gate layer, thereby a first gate and a second gate being formed. Moreover, a semiconductor process, which forms the first spacer and the second spacer separately, is also provided.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: December 20, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 9500541
    Abstract: A method and a device for determining the pressure distribution for bonding of a first substrate to a second substrate, with the following steps, especially with the following sequence: placing a measurement layer between a first tool for holding the first substrate and an opposite second tool which is aligned to the first tool for bonding of the substrate, deformation of the measurement layer by bringing the tools closer to one another, measurement of the deformation of the measurement layer and computation of the pressure distribution.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: November 22, 2016
    Assignee: EV Group E. Thallner GmbH
    Inventors: Bernhard Rebhan, Markus Wimplinger, Jürgen Burggraf
  • Patent number: 9496145
    Abstract: An electrochemical process for applying a conductive film onto a substrate having a seed layer includes placing the substrate into contact with an electrochemical plating bath containing cobalt or nickel, with the plating bath having pH of 4.0 to 9.0. Electric current is conducted through the bath to the substrate. The cobalt or nickel ions in the bath deposit onto the seed layer. The plating bath may contain cobalt chloride and glycine. The electric current may range from 1-50 milli-ampere per square cm. After completion of the electrochemical process, the substrate may be removed from the plating bath, rinsed and dried, and then annealed at a temperature of 200 to 400 C to improve the material properties and reduce seam line defects. The plating and anneal process may be performed through multiple cycles.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: November 15, 2016
    Assignee: APPLIED Materials, Inc.
    Inventors: John W. Lam, Ismail Emesh, Roey Shaviv
  • Patent number: 9484212
    Abstract: A chemical mechanical polishing method is provided comprising: providing a substrate, wherein the substrate comprises a silicon oxide and a silicon nitride; providing a polishing slurry; providing polishing pad, comprising: a polishing layer having a composition that is a reaction product of ingredients, comprising: a polyfunctional isocyanate and an amine initiated polyol curative; wherein the stoichiometric ratio of the amine initiated polyol curative to the polyfunctional isocyanate is selected to tune the removal rate selectivity of the polishing layer; creating dynamic contact between the polishing surface and the substrate; dispensing the polishing slurry on the polishing pad at or near the interface between the polishing surface and the substrate; and, removing at least some of the silicon oxide and the silicon nitride from the substrate.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: November 1, 2016
    Assignees: Rohm and Haas Electronic Materials CMP Holdings, Inc., Dow Global Techologies LLC
    Inventors: Bainian Qian, Yi Guo, Marty W. DeGroot, George C. Jacob
  • Patent number: 9481811
    Abstract: The invention provides a chemical-mechanical polishing composition containing (a) an abrasive selected from wet-process silica, alpha alumina, fumed alumina, ceria, zirconia, titania, and combinations thereof, (b) an oxidation catalyst, (c) a non-transition metal sulfate salt, (d) a complexing agent, (e) hydrogen peroxide, (f) a nonionic surfactant, (g) an anionic surfactant, and (h) water. The polishing composition has a pH of about 1 to about 5, and the polishing composition is substantially free of a peroxydisulfate salt. The invention also provides a method of chemically-mechanically polishing a substrate, especially a nickel-phosphorous substrate, by contacting a substrate with a polishing pad and the chemical-mechanical polishing composition, moving the polishing pad and the polishing composition relative to the substrate, and abrading at least a portion of the substrate to polish the substrate.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: November 1, 2016
    Assignee: Cabot Microelectronics Corporation
    Inventors: Tong Li, Hon-Wu Lau, Michael White
  • Patent number: 9472467
    Abstract: A method of forming a semiconductor device including a semiconductor substrate having a first surface and a second surface, and having a gallium nitride-containing layer provided on the first surface of the semiconductor substrate includes grinding, polishing, and etching the second surface of the semiconductor substrate of which a thickness is d1, and reducing the thickness of the semiconductor substrate to one-fifth or less of d1.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: October 18, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shingo Masuko
  • Patent number: 9472475
    Abstract: A method of controlling polishing includes storing a desired ratio representing a ratio for a clearance time of a first zone of a substrate to a clearance time of a second zone of the substrate. During polishing of a first substrate, an overlying layer is monitored, a sequence of measurements is generated, and the measurements are sorted a first group associated with the first zone of the substrate and a second group associated with the second zone on the substrate. A first time and a second time at which the overlying layer is cleared is determined based on the measurements from the first group and the second group, respectively. At least one adjusted polishing pressure is calculated for the first zone based on a first pressure applied in the first zone during polishing the first substrate, the first time, the second time, and the desired ratio.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: October 18, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Kun Xu, Ingemar Carlsson, Tzu-Yu Liu, Shih-Haur Shen, Boguslaw A. Swedek, Wen-Chiang Tu, Lakshmanan Karuppiah
  • Patent number: 9460933
    Abstract: A patterning method is provided. Mask structures including first mask layers and first photoresist layers are formed sequentially on a material layer. A second mask layer covering the mask structures is conformally formed on the material layer. First sacrificed layers are formed between the mask structures. Parts of the second mask layer are removed to expose the first photoresist layers and form first U-shape mask layers. The first photoresist layers and the first sacrificed layers are removed. A third mask layer having first surfaces and second surfaces lower than the first surfaces is conformally formed on the material layer. Second sacrificed layers are formed on the second surfaces. Parts of the third mask layer are removed to expose protrusions of the first U-shape mask layers and form second U-shape mask layers. The material layer is patterned by using protrusions of the second U-shape mask layers as masks.
    Type: Grant
    Filed: August 2, 2015
    Date of Patent: October 4, 2016
    Assignee: Powerchip Technology Corporation
    Inventor: Zih-Song Wang
  • Patent number: 9449809
    Abstract: The present disclosure describes methods of an interface adhesion improvement methods used on a transparent substrate for OLED or thin film transistor applications. In one embodiment, a method of forming a buffer layer on a surface of a substrate includes providing a substrate having an planarization material disposed thereon in a processing chamber, supplying a buffer layer gas mixture including a silicon containing gas into the processing chamber, controlling a substrate temperature less than about 100 degrees Celsius, forming a buffer layer on the planarization material, supplying an encapsulating barrier layer deposition gas mixture including a silicon containing gas and a nitrogen containing gas into the processing chamber, and forming an encapsulating barrier layer on the buffer layer.
    Type: Grant
    Filed: July 20, 2013
    Date of Patent: September 20, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Young Jin Choi, Jrjyan Jerry Chen, Beom Soo Park, Soo Young Choi
  • Patent number: 9437547
    Abstract: A device and methods for forming a device are disclosed. A substrate is provided and a TSV is formed in the substrate through a top surface of the substrate. The TSV and top surface of the substrate is lined with an insulation stack having a first insulation layer, a polish stop layer and a second insulation layer. A conductive layer is formed on the substrate. The TSV is filled with conductive material of the conductive layer. The substrate is planarized to remove excess conductive material of the conductive layer. The planarizing stops on the polish stop layer to form a planar top surface.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: September 6, 2016
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Benfu Lin, Hong Yu, Lup San Leong, Alex See, Wei Lu
  • Patent number: 9425053
    Abstract: A trilayer stack that can be used as a block mask for forming patterning features in semiconductor structures with high aspect ratio topography is provided. The trilayer stack includes an organic planarization (OPL) layer, a titanium-containing antireflective coating (TiARC) layer on the OPL layer and a photoresist layer on the TiARC layer. Employing a combination of an OPL having a high etch rate and a TiARC layer that can be easily removed by a mild chemical etchant solution in the trilayer stack can significantly minimize substrate damage during lithographic patterning processes.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: August 23, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Martin Glodde, Steven J. Holmes, Daiji Kawamura
  • Patent number: 9412643
    Abstract: A method of fabricating a fin field effect transistor (FinFET) device and the device are described. The method includes forming a deep STI region adjacent to a first side of an end fin among a plurality of fins and lining the deep STI region, including the first side of the end fin, with a passivation layer. The method also includes depositing an STI oxide into the deep STI region, the passivation layer separating the STI oxide and the first side of the end fin, etching back the passivation layer separating the STI oxide and the first side of the end fin to a specified depth to create a gap, and depositing gate material, the gate material covering the gap.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: August 9, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 9365935
    Abstract: The present invention provides an etching solution for silver or silver alloy comprising one at least ammonium compound represented by the formula (1), (2) or (3) below and an oxidant: wherein each of the variables is as defined herein.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: June 14, 2016
    Assignee: Inktec Co., Ltd.
    Inventors: Kwang Choon Chung, Hyun-Nam Cho, Young-Kwan Seo
  • Patent number: 9343372
    Abstract: A method includes forming an n-FET device and a p-FET device on a substrate, each of the n-FET device and the p-FET device include a metal gate stack consisting of a titanium-aluminum carbide (TiAlC) layer above and in direct contact with a titanium nitride (TiN) cap, and removing, from the p-FET device, the TiAlC layer selective to the TiN cap. The removal of the TiAlC layer includes using a selective TiAlC to TiN wet etch chemistry solution with a substantially high TiAlC to TiN etch ratio such that the TiN cap remains in the p-FET device.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: May 17, 2016
    Assignee: GlobalFoundries, Inc.
    Inventors: Ruqiang Bao, Unoh Kwon, Rekha Rajaram, Keith Kwong Hon Wong
  • Patent number: 9330935
    Abstract: Disclosed is a plasma etching method which suppresses the narrowing of the line-width of the line formed by etching and maintain the height of a remaining photoresist. The plasma etching method includes a modification process and an etching process. The modification process modifies a photoresist having a predetermined pattern by plasma of HBr/Ar gas while applying a negative DC voltage to an upper electrode containing silicon disposed to face a target object in which an organic film and the photoresist are sequentially laminated. The etching process etches the organic film by plasma of a processing gas which contains a CF-based gas and a CHF-based gas.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: May 3, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Toru Hisamatsu, Masanobu Honda, Yoshihide Kihara
  • Patent number: 9330937
    Abstract: Two-step process sequences uniformly etch both tungsten-based and titanium-based structures on a substrate. A sequence of wet etches using peroxide and heated nitric acid uniformly recesses a metal stack that includes W, TiN, and TiAl. W, TiN and TiC are uniformly recessed by a peroxide etch at ˜25 C followed by an acid solution with a very small amount of added peroxide at ˜60 C. TiC is etched without etching trench oxides or other metals in a work-function metal stack by either (1) highly-dilute of ultra-dilute HF at 25-35 C, (2) dilute HCl at 25-60 C, (3) dilute NH4OH at 25-60 C, or (4) solution (2) or (3) with small amounts of peroxide. Other metals in the stack may then be plasma-etched without being blocked by TiC residues.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: May 3, 2016
    Assignee: Intermolecular, Inc.
    Inventors: Gregory Nowling, John Foster
  • Patent number: 9317650
    Abstract: One or more techniques or systems for determining double patterning technology (DPT) layout routing compliance are provided herein. For example, a layout routing component of a system is configured to assign a pin loop value to a pin loop. In some embodiments, the pin loop value is assigned based on a mask assignment of a pin of the pin loop. In some embodiments, the pin loop value is assigned based on a number of nodes associated with the pin loop. DPT compliance or a DPT violation is determined for the pin loop based on the pin loop value. In this manner, odd loop detection associated with DPT layout routing is provided because a DPT violation results in generation of an additional instance of a net, for example. Detecting an odd loop allows a design to be redesigned before fabrication, where the odd loop would present undesired issues.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: April 19, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Huang-Yu Chen, Fang-Yu Fan, Yuan-Te Hou, Wen-Hao Chen, Chung-Hsing Wang, Yi-Kan Cheng
  • Patent number: 9297959
    Abstract: Disclosed herein is a method for fabricating an optical device that includes depositing an etch stop material to form an etch stop layer, wherein the etch stop material has a refractive index in the infrared wavelength range, n1; depositing a core material to form a core layer, wherein the core material has a refractive index in the infrared wavelength range, n2; and etching the core layer using a halide based etch process, wherein the etch stop material has an etch rate in the halide based etch process and the core material has an etch rate in the halide based etch process, wherein the etch rate of the core material is at least about five times higher than the etch rate of the etch stop material, and wherein n1 is not greater than n2.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: March 29, 2016
    Assignee: Seagate Technology LLC
    Inventors: Xiaoyue Huang, Lijuan Zou, Yongjun Zhao, Michael Kautzky
  • Patent number: 9287158
    Abstract: A substrate processing apparatus includes first and second polishing units for polishing a peripheral portion of a substrate, a primary cleaning unit for cleaning the substrate, a secondary cleaning and drying unit for drying the substrate cleaned in the primary cleaning unit, and a measurement unit for measuring the peripheral portion of the substrate. The measurement unit includes a mechanism for measurement required for polishing in the first and second polishing units, such as a diameter measurement mechanism, a cross-sectional shape measurement mechanism, or a surface condition measurement mechanism.
    Type: Grant
    Filed: April 18, 2006
    Date of Patent: March 15, 2016
    Assignee: EBARA CORPORATION
    Inventors: Tamami Takahashi, Mitsuhiko Shirakashi, Kenya Ito, Kazuyuki Inoue, Kenji Yamaguchi, Masaya Seki