Simultaneous (e.g., Chemical-mechanical Polishing, Etc.) Patents (Class 438/692)
  • Patent number: 10680535
    Abstract: A vertical comb-drive actuator comprising a support base and a movable body is described. The support base comprises first comb electrodes and a first surface wherein the first comb electrodes extend from the first surface. The movable body attached to the support base comprises second comb electrodes and a second surface wherein the second comb electrodes extend from the second surface. The movable body may rotate about a rotation axis and the first comb electrodes are interdigitated with the second comb electrodes correspondingly. The second comb electrodes extend along a first direction, the rotation axis extends along a second direction, and the first comb electrodes extend along a third direction. The distance between the first lateral face of the first comb electrode and the second surface is shorter than the second length defined as the distance between the end surface of the second comb electrode and the second surface.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: June 9, 2020
    Assignee: OPUS MICROSYSTEMS CORPORATION
    Inventors: Chang-li Hung, Ta-wei Lin, Kai-yu Jiang
  • Patent number: 10625392
    Abstract: The present invention is a polishing pad formed by foamed polyurethane, with a content of S phase in the foamed polyurethane, as determined by pulsed NMR measurement at 25° C., exceeding 70%.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: April 21, 2020
    Assignee: NITTA HAAS INCORPORATED
    Inventors: Yohei Murakami, Nobuyuki Oshima, Hiroyuki Nakano
  • Patent number: 10610994
    Abstract: A polishing module includes a chuck having a substrate receiving surface and a perimeter, and one or more polishing pad assemblies positioned about the perimeter of the chuck, wherein each of the one or more polishing pad assemblies are coupled to an actuator that provides movement of the respective polishing pad assemblies in a sweep direction, a radial direction, and a oscillating mode relative to the substrate receiving surface and are limited in radial movement to about less than one-half of the radius of the chuck as measured from the perimeter of the chuck.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: April 7, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Eric Lau, Hui Chen, King Yi Heung, Chih Chung Chou, Edwin C. Suarez, Garrett Ho Yee Sin, Charles C. Garretson, Jeonghoon Oh
  • Patent number: 10586694
    Abstract: According to one embodiment, a method for fabricating a semiconductor device includes performing a back surface processing to remove at least one of a scratch and a foreign material formed on a back surface of a substrate to be processed, a front surface of the substrate being retained in a non-contact state, contacting the back surface of the substrate to a stage to be retained, and providing a pattern on the front surface of the substrate by using lithography.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: March 10, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Masako Kodera, Hiroshi Tomita, Takeshi Nishioka
  • Patent number: 10510540
    Abstract: Methods of forming semiconductor devices comprising etching a hardmask and spin-on-carbon layer through an opening in a photoresist to expose a gapfill material. The photoresist, spin-on-carbon layer and gapfill material are removed. A new spin-on-carbon layer, hardmask and photoresist are formed with an opening over a spacer mandrel. The hardmask, spin-on-carbon layer are etched through the opening and the layers and spacer mandrel are removed. An etch stop layer and oxide layer are removed and a height of the spacer mandrel and gapfill material are reduced exposing portions of the substrate. The exposed portions of the substrate are fin etched and the layers removed.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: December 17, 2019
    Assignee: MICROMATERIALS LLC
    Inventors: Ying Zhang, Qingjun Zhou, Yung-Chen Lin, Ho-yung David Hwang
  • Patent number: 10478939
    Abstract: The present invention provides a means allowing achievement of sufficient planarization of the surface of an object to be polished containing two or more types of materials. The present invention is a polishing method for polishing an object to be polished containing two or more types of materials by using a polishing composition, the polishing method including equalization of the surface zeta potential of the object to be polished.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: November 19, 2019
    Assignee: FUJIMI INCORPORATED
    Inventors: Yukinobu Yoshizaki, Satoru Yarita, Shogo Onishi
  • Patent number: 10434623
    Abstract: A polishing module including a chuck having a substrate receiving surface and a perimeter, and one or more polishing pad assemblies positioned about the perimeter of the chuck, wherein each of the one or more polishing pad assemblies are coupled to an actuator that provides movement of the respective polishing pad assemblies in one or more of a sweep direction, a radial direction, and a oscillating mode relative to the substrate receiving surface and are limited in radial movement to about less than one-half of the radius of the chuck as measured from the perimeter of the chuck.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: October 8, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Eric Lau, Hui Chen, King Yi Heung, Wei-Cheng Lee, Chih Chung Chou, Edwin C. Suarez, Garrett Ho Yee Sin, Charles C. Garretson, Jeonghoon Oh
  • Patent number: 10371939
    Abstract: One or more apparatus providing over-travel protection for actuators are disclosed. An example apparatus includes a mirror; a first plate coupled to the mirror; and a support post coupled the first plate, the support post structured to prevent the mirror from moving within a threshold distance to a second plate.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: August 6, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: William Craig McDonald, James Norman Hall, Adam Joseph Fruehling
  • Patent number: 10350728
    Abstract: Polishing pad cleaning systems and related methods are disclosed. A rotatable platen comprising a polishing pad in combination with a fluid, such as a polishing fluid, contacts a substrate to planarize material at the surface thereof and resultantly creates debris. A cleaning system introduces a spray system to remove debris from the polishing pad to prevent substrate damage and improve efficiency, a waste removal system for removing used spray, used polishing fluid, and debris from the polishing pad, and a polishing fluid delivery system for providing fresh polishing fluid to the polishing pad, such that the substrate only receives fresh polishing fluid upon each complete rotation of the platen. In this manner, within die performance is enhanced, the range of certain CMP processes is improved, scratches and contamination are avoided for each polished substrate and for later-polished substrates, and platen temperatures are reduced.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: July 16, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Jie Diao, Erik S. Rondum, Thomas Ho Fai Li, Bum Jick Kim, Christopher Heung-Gyun Lee
  • Patent number: 10334184
    Abstract: An electronic device may have an optical system that includes one or more light-based components. The light-based components may include light-emitting components such as light-emitting diodes or lasers and may include light-detecting components such as photodiodes or digital image sensors. The optical system may include a light diffuser. The light diffuser may diffuse light that is being detected by a light-detecting component or may diffuse light that is being emitted by a light-emitting component. Light diffusers in optical systems may be formed from patterned light diffuser layers on transparent substrates. Layers of sealant, thin glass layers, antireflection coatings, and other layers may be incorporated into the light diffusers. The light diffuser layers may operate at visible wavelengths and infrared wavelengths. An infrared light diffuser layer may be formed from a patterned silicon layer such as a patterned layer of hydrogenated amorphous silicon.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: June 25, 2019
    Assignee: Apple Inc.
    Inventors: Ligang Wang, Miodrag Scepanovic, Neil MacKinnon, Zhenbin Ge
  • Patent number: 10323162
    Abstract: The present invention provides an abrasive material capable of polishing difficult-to-polish silicon carbide at a high degree of surface precision. The present invention relates to an abrasive material including manganese dioxide particles having a non-needle-like shape possessing a ratio of the longitudinal axis to the transverse axis of the particles observed with a scanning electron microscope of 3.0 or less. The abrasive material is preferable if the average particle size DSEM of the longitudinal axis of the observed particles is 1.0 ?m or less, and if the particle size D50 of the volume-based cumulative fraction of 50% in laser diffraction/scattering particle size distribution measurement is 2.0 ?m or less.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: June 18, 2019
    Assignee: Mitsui Minig & Smelting Co., Ltd.
    Inventors: Mikimasa Horiuchi, Ryutaro Kuroda, Yasuhide Yamaguchi
  • Patent number: 10322493
    Abstract: An apparatus for polishing a semiconductor wafer using a pad resurfacing arm and an apparatus therefor are disclosed. Embodiments may include providing a semiconductor wafer on a chemical mechanical polishing (CMP) tool, the CMP tool including a polish pad and a pad resurfacing arm which includes a pad cleaning part, a pad conditioning part, and a slurry dispensing part, dispensing a slurry to the polish pad utilizing the pad resurfacing arm, and polishing the semiconductor wafer utilizing the polish pad.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: June 18, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Jens Kramer
  • Patent number: 10326040
    Abstract: Embodiments relate to forming a conformable interface layers (clayers) on small semiconductor devices, such as light emitting diodes (LEDs) to facilitate adhesion with a pick-up head for operations during the manufacturing of an electronic display. A conformable material is formed in regions between LED dies on a carrier substrate and over the LED dies. A mask is applied over the conformable material to selectively cover the conformable material. Portions of the conformable material are exposed to light to selectively cure or not cure the portions of the conformable material. The conformable material between the LED dies is removed to form a conformable interface layer over each of the LED dies.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: June 18, 2019
    Assignee: Facebook Technologies, LLC
    Inventors: Oscar Torrents Abad, Tilman Zehender, Pooya Saketi, Karsten Moh
  • Patent number: 10312103
    Abstract: A method for forming fins includes forming a three-color hardmask fin pattern on a fin base layer. The three-color hardmask fin pattern has hardmask fins of three mutually selectively etchable compositions. A region on the three-color hardmask fin pattern is masked, leaving one or more fins of a first color exposed. All exposed fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color. The mask and all fins of a second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: June 4, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sean D. Burns, Nelson M. Felix, Chi-Chun Liu, Yann A. M. Mignot, Stuart A. Sieg
  • Patent number: 10301580
    Abstract: A composition for cleaning integrated circuit substrates, the composition comprising: water; an oxidizer comprising an ammonium salt of an oxidizing species; a corrosion inhibitor comprising a primary alkylamine having the general formula: R?NH2, wherein R? is an alkyl group containing up to about 150 carbon atoms and will more often be an aliphatic alkyl group containing from about 4 to about 30 carbon atoms; optionally, a water-miscible organic solvent; optionally, an organic acid; optionally, a buffer species; optionally, a fluoride ion source; and optionally, a metal chelating agent.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: May 28, 2019
    Assignee: VERSUM MATERIALS US, LLC
    Inventors: Wen Dar Liu, Yi-Chia Lee, Tianniu Chen, William Jack Casteel, Jr., Seiji Inaoka, Gene Everad Parris
  • Patent number: 10262869
    Abstract: A planarization method includes providing a substrate having a semiconductor structure formed thereon. A dielectric layer is formed on the substrate, and a mask layer is formed on the dielectric layer. A first chemical mechanical polishing process is performed to remove a portion of the mask layer thereby forming an opening directly over the semiconductor structure and exposing the dielectric layer. A first etching process is performed to anisotropically remove a portion of the dielectric layer from the opening. The mask layer is then removed and a second chemical mechanical polishing process is then performed.
    Type: Grant
    Filed: February 25, 2018
    Date of Patent: April 16, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Jen-Chieh Lin, Lee-Yuan Chen, Wen-Chin Lin, Chi-Lune Huang, Pi-Hung Chuang, Tai-Lin Chen, Sun-Hong Chen
  • Patent number: 10252396
    Abstract: The present disclosure relates to polishing pads which include a polishing layer, wherein the polishing layer includes a working surface and a second surface opposite the working surface. The working surface includes at least one of a plurality of precisely shaped pores and a plurality of precisely shaped asperities. The present disclosure further relates to a polishing system, the polishing system includes the preceding polishing pad and a polishing solution. The present disclosure relates to a method of polishing a substrate, the method of polishing including: providing a polishing pad according to any one of the previous polishing pads; providing a substrate, contacting the working surface of the polishing pad with the substrate surface, moving the polishing pad and the substrate relative to one another while maintaining contact between the working surface of the polishing pad and the substrate surface, wherein polishing is conducted in the presence of a polishing solution.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: April 9, 2019
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Duy K. Lehuu, Kenneth A. P. Meyer, Moses M. David
  • Patent number: 10256111
    Abstract: A method for polishing dies locations on a substrate with a polishing module. A thickness at selected locations on the substrate is premeasured at a metrology station, each location corresponding to a location of a single die. The thickness obtained by the metrology station for the selected locations of the substrate is provided to a controller of a polishing module. The thickness corrections for each selected location on the substrate are determined. A polishing step in a polishing recipe is formed from the thickness correction for each selected location. A polishing parameter for each die location is calculated for the recipe.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: April 9, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Eric Lau, King Yi Heung, Charles C. Garretson, Jun Qian, Thomas H. Osterheld, Shuchivrat Datar, David Chui
  • Patent number: 10236436
    Abstract: An element manufacturing method includes a first step of obtaining a thickness distribution in a planar direction of a workpiece, a second step of calculating a processing amount distribution from a difference between the thickness distribution and a desired film-thickness distribution, a third step of locally processing the workpiece in accordance with the processing amount distribution, a fourth step of, after the third step, dividing an inside of a plane of the workpiece into a plurality of element parts and forming an electrode in each of the element parts, and a fifth step of making the plurality of element parts apart from each other to form a plurality of elements.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: March 19, 2019
    Assignee: KYOCERA CORPORATION
    Inventor: Keiichiro Watanabe
  • Patent number: 10214663
    Abstract: Described are a chemical-mechanical polishing (CMP) composition comprising abrasive particles in the form of organic/inorganic composite particles as well as the use of said composite particles as abrasive particles in a CMP composition and processes for the manufacture of a semiconductor device comprising chemical mechanical polishing of a substrate in the presence said CMP composition.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: February 26, 2019
    Assignees: ST. LAWRENCE NANOTECHNOLOGY, BASF TAIWAN LTD., BASF CORPORATION
    Inventors: Yongqing Lan, Bastian Marten Noller, Yuzhuo Li, Liang Jiang, Daniel Kwo-Hung Shen, Reza Golzarian
  • Patent number: 10157776
    Abstract: A method for manufacturing a semiconductor device includes forming a hard mask layer overlying a device layer of a semiconductor device, a mandrel underlayer over hard mask layer, and a mandrel layer over mandrel underlayer. The mandrel layer has a plurality of mandrel lines extending along a first direction. A plurality of openings are formed in mandrel underlayer extending in a second direction substantially perpendicular to first direction. A spacer layer is formed over mandrel underlayer and layer. Spacer layer fills plurality of openings in underlayer. Portions of spacer layer are removed to expose an upper surface of underlayer and mandrel layer, and mandrel layer is removed. By using remaining portions of spacer layer as a mask, underlayer and hard mask layer are removed, to form a hard mask pattern with first hard mask pattern lines extending along first direction and second hard mask pattern lines extending along second direction.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yan-Jhi Huang, Yu-Yu Chen
  • Patent number: 10147647
    Abstract: A method of detaching a growth substrate from a layer sequence includes introducing at least one wafer composite into an etching bath containing an etching solution such that the etching solution is located at least in regions within separating trenches, repeatedly varying a pressure of a base pressure prevailing in the etching bath with at least one pressure variation device, and detaching the growth substrate, wherein at least one of 1-3 is satisfied: 1) a buffer chamber attached to the etching bath and connected thereto is provided and the volume variation is effected by a movement of a piston or hydraulic plunger introduced into the buffer chamber, 2) the volume variation is at least partly effected with a compressor attached to the etching bath, and 3) the pressure variation is at least partly effected by at least one of removal of a gas and a liquid from the etching bath or by addition of at least one of the gas and the liquid thereto.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: December 4, 2018
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Christoph Klemp, Marco Englhard
  • Patent number: 10134614
    Abstract: A projecting/receiving unit (52) projects a laser light to a peripheral portion (30) and receives the reflected light while a liquid is being fed to a substrate (14) and is flowing on the peripheral portion (30). A signal processing controller (54) processes the electric signal of the reflected light to decide the state of the peripheral portion (30). The state of the peripheral portion being polished is monitored. Moreover, the polish end point is detected. A transmission wave other than the laser light may also be used. The peripheral portion (30) may also be enclosed by a passage forming member thereby to form a passage properly. The peripheral portion can be properly measured even in the situation where the liquid is flowing on the substrate peripheral portion.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: November 20, 2018
    Assignee: Ebara Corporation
    Inventors: Mitsuo Tada, Yasunari Suto, Hirofumi Ichihara, Kenya Ito, Tamami Takahashi
  • Patent number: 10128147
    Abstract: Semiconductor structures include a patterned interlayer dielectric overlaying a semiconductor substrate. The interlayer dielectric includes a first dielectric layer and at least one additional dielectric layer disposed on the first dielectric layer, wherein the patterned interlayer dielectric comprises at least one opening extending through the interlayer dielectric to the semiconductor substrate. Chemically enriched regions including ions of Si, P, B, N, O and combinations thereof are disposed in surfaces of the first dielectric layer and the at least one dielectric layer defined by the at least one opening. Also described are methods of for forming an interconnect structure in a semiconductor structure.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: November 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Roger A. Quon, Terry A. Spooner, Wei Wang, Chih-Chao Yang
  • Patent number: 10121651
    Abstract: A technique capable of forming a side wall of a gate electrode having high resistance-to-etching and low leakage current is provided. A method of manufacturing a semiconductor device according to the technique includes: (a) loading a substrate into a processing space in a process vessel, the substrate having thereon a gate electrode and an insulating film formed on a side surface of the gate electrode as a side wall; and (b) forming an etching-resistant film containing carbon and nitrogen on a surface of the insulating film by supplying a carbon-containing gas into the processing space.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: November 6, 2018
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Arito Ogawa, Shin Hiyama
  • Patent number: 10077381
    Abstract: A polishing slurry composition is provided. The polishing slurry composition includes at least two types of abrasive particles among first abrasive particles, second abrasive particles, and third abrasive particles, and an oxidizer. A peak-to-valley roughness Rpv decreases when a contact area between the abrasive particles and a tungsten-containing film increases.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: September 18, 2018
    Assignee: KCTech Co., Ltd.
    Inventors: Dong Kyu Choi, Young Ho Yoon, Hyun Goo Kong, Jin Sook Hwang, Han Teo Park
  • Patent number: 10062566
    Abstract: A semiconductor device, comprising a base substrate, a buffer layer and a polysilicon layer film, wherein the base substrate, the buffer layer and the polysilicon layer film being laminated sequentially, and wherein regularly arranged first grooves being provided on a surface of the buffer layer contacting the polysilicon film; the polysilicon film being formed, by applying crystallization treatment, through an optical annealing process, to an amorphous silicon film on the buffer layer having regularly arranged first grooves.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: August 28, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wenqing Xu, Chunping Long
  • Patent number: 10062759
    Abstract: A MOSFET using a SiC substrate has a problem that a carbon-excess layer is formed on a surface by the application of mechanical stress due to thermal oxidation and the carbon-excess layer degrades mobility of channel carriers. In the invention, (1) a layer containing carbon-carbon bonds is removed; (2) a gate insulating film is formed by a deposition method; and (3) an interface between a crystal surface and the insulating film is subjected to an interface treatment at a low temperature for a short time. Due to this, the carbon-excess layer causing characteristic degradation is effectively eliminated, and at the same time, dangling bonds can be effectively eliminated by subjecting an oxide film and an oxynitride film to an interface treatment.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: August 28, 2018
    Assignee: HITACHI, LTD.
    Inventors: Digh Hisamoto, Keisuke Kobayashi, Naoki Tega, Toshiyuki Ohno, Hirotaka Hamamura, Mieko Matsumura
  • Patent number: 10056277
    Abstract: A polishing method capable of obtaining a stable film thickness without being affected by a difference in measurement position is disclosed. The polishing method includes: rotating a polishing table that supports a polishing pad; pressing the surface of the wafer against the polishing pad; obtaining a plurality of film-thickness signals from a film thickness sensor during a latest predetermined number of revolutions of the polishing pad, the film thickness sensor being installed in the polishing table; determining a plurality of measured film thicknesses from the plurality of film-thickness signals; determining an estimated film thickness at a topmost portion of the raised portion based on the plurality of measured film thicknesses; and monitoring polishing of the wafer based on the estimated film thickness at the topmost portion of the raised portion.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: August 21, 2018
    Assignee: EBARA CORPORATION
    Inventors: Yoichi Kobayashi, Yoichi Shiokawa, Katsuhide Watanabe
  • Patent number: 10043678
    Abstract: The present invention relates to a slurry composition for reducing scratches generated when polishing the metal film in a manufacturing process of a semiconductor integrated circuit, by lowering frictional force so that a temperature of the composition which may rise during the polishing is lowered, the thermal stability of the slurry is improved and the size increase of particles in the slurry is suppressed, and a method for reducing scratches using the same. The method comprises the steps of applying a slurry composition for polishing a metal film to a substrate on which the metal film is formed, the slurry composition containing an organic solvent including a nitrogen atom and a glycol-based organic solvent; and making a polishing pad to be contacted to the substrate and moving the polishing pad with respect to the substrate, thereby removing at least part of the metal film from the substrate.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: August 7, 2018
    Assignee: DONGJIN SEMICHEM CO., LTD.
    Inventors: Chang Yong Park, Jong Dai Park, Jong Chul Shin, Jae Hyun Kim, Goo Hwa Lee, Min Sung Park
  • Patent number: 10032871
    Abstract: A MOSFET using a SiC substrate has a problem that a carbon-excess layer is formed on a surface by the application of mechanical stress due to thermal oxidation and the carbon-excess layer degrades mobility of channel carriers. In the invention, (1) a layer containing carbon-carbon bonds is removed; (2) a gate insulating film is formed by a deposition method; and (3) an interface between a crystal surface and the insulating film is subjected to an interface treatment at a low temperature for a short time. Due to this, the carbon-excess layer causing characteristic degradation is effectively eliminated, and at the same time, dangling bonds can be effectively eliminated by subjecting an oxide film and an oxynitride film to an interface treatment.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: July 24, 2018
    Assignee: HITACHI, LTD.
    Inventors: Digh Hisamoto, Keisuke Kobayashi, Naoki Tega, Toshiyuki Ohno, Hirotaka Hamamura, Mieko Matsumura
  • Patent number: 10030172
    Abstract: A polishing agent comprises: a fluid medium; an abrasive grain containing a hydroxide of a tetravalent metal element; a first additive; a second additive; and a third additive, wherein: the first additive is at least one selected from the group consisting of a compound having a polyoxyalkylene chain and a vinyl alcohol polymer; the second additive is a cationic polymer; and the third additive is an amino group-containing sulfonic acid compound.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: July 24, 2018
    Assignee: HITACHI CHEMICAL COMPANY, LTD.
    Inventors: Hisataka Minami, Tomohiro Iwano, Toshiaki Akutsu
  • Patent number: 10017669
    Abstract: A polishing composition includes crystalline metal oxide particles as abrasive grains, wherein the full width at half maximum of a peak portion having the maximum diffracted intensity in an X-ray powder diffraction pattern of the metal oxide particles is less than 1°. Thus, a polishing composition and a polishing method have high polishing speed and suppress defect generation such as a scratch and dishing, which causes to degrade reliability of a semiconductor apparatus in a polishing process of a semiconductor substrate, particularly in a chemical mechanical polishing process of a semiconductor substrate with a metal layer having tungsten, etc.; and a method produces the polishing composition.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: July 10, 2018
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventor: Yoshihiro Nojima
  • Patent number: 9982165
    Abstract: A polishing slurry for silicon, a method of polishing polysilicon, and a method of manufacturing a thin film transistor substrate, the slurry including a polishing particle; a dispersing agent including an anionic polymer, a hydroxyl acid, or an amino acid; a stabilizing agent including an organic acid, the organic acid including a carboxyl group; a hydrophilic agent including a hydrophilic group and a hydrophobic group, and water, wherein the polishing particle is included in the polishing slurry in an amount of about 0.1% by weight to about 10% by weight, based on a total weight of the slurry, a weight ratio of the polishing particle and the dispersing agent is about 1:0.01 to about 1:0.2, a weight ratio of the polishing particle and the stabilizing agent is about 1:0.001 to about 1:0.1, and a weight ratio of the polishing particle and the hydrophilic agent is about 1:0.01 to about 1:3.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: May 29, 2018
    Assignees: SAMSUNG DISPLAY CO., LTD., UBmaterials Inc.
    Inventors: Byoung-Kwon Choo, Jin-Hyung Park, Jeong-Kyun Na, Joon-Hwa Bae, Byoung-Ho Cheong, Joo-Woan Cho, In-Sun Hwang
  • Patent number: 9893116
    Abstract: A manufacturing method of an electronic device processes a surface of a first wafer, bonds a surface of a second wafer to the processed surface of the first wafer, thins the first wafer by polishing a back surface of the first wafer, the back surface being located on an opposite side of the processed surface, forms a groove along a periphery of the back surface of the thinned first wafer by using a dicing blade, attaches a protective layer to the back surface of the first wafer having the groove, via a bonding layer, and polishes a back surface of the second wafer, the back surface being located on an opposite side of the surface attached to the protective layer.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: February 13, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinya Takyu, Hideo Numata, Hiroyuki Okura
  • Patent number: 9885831
    Abstract: An silicon photonics device of hybrid waveguides having a coupling interlayer with an accurately controlled thickness and a method of making the same. The device includes a first plurality of Si waveguides formed in a SOI substrate and a first layer of SiO2 overlying the first plurality of Si waveguides and a second plurality of Si3N4 waveguides formed on the first layer of SiO2. At least one Si3N4 waveguide is disposed partially overlapping with at least one of the first plurality Si waveguides in vertical direction separated by the first layer of SiO2 with a thickness controlled no greater than 90 nm. The device includes a second layer of SiO2 overlying the second plurality of Si3N4 waveguides. The method of accurately controlling the coupling interlayer SiO2 thickness includes a multilayer SiO2/Si3N4/SiO2 hard mask process for SiO2 etching and polishing as stopping and buffering layer as well as Si waveguide etching mask.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: February 6, 2018
    Assignee: INPHI CORPORATION
    Inventors: Liang Ding, Radhakrishnan L. Nagarajan
  • Patent number: 9856401
    Abstract: Embodiments of the invention provide a polishing composition including colloidal silica, pulverized wet-process silica particles, and a water-soluble polymer compound, wherein the water-soluble polymer compound is a polymer or copolymer having a constituent unit derived from an unsaturated aliphatic carboxylic acid. Various embodiments achieve a high polishing rate and obtain a good surface smoothness and end-face shape without the use of alumina particles.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: January 2, 2018
    Assignee: YAMAGUCHI SEIKEN KOGYO CO., LTD.
    Inventors: Toru Iwata, Akira Sugawa
  • Patent number: 9812571
    Abstract: A thermal mixing process is employed to convert a portion of a silicon germanium alloy fin having a first germanium content and an overlying non-doped epitaxial silicon source material into a silicon germanium alloy source structure having a second germanium content that is less than the first germanium content, to convert another portion of the silicon germanium alloy fin and an overlying non-doped epitaxial silicon drain material into a silicon germanium alloy drain structure having the second germanium content, and to provide a tensile strained silicon germanium alloy fin portion having the first germanium content. A dopant is then introduced into the silicon germanium alloy source structure and into the silicon germanium alloy drain structure.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: November 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Pouya Hashemi, Alexander Reznicek, Joshua M. Rubin, Robin M. Schulz
  • Patent number: 9802294
    Abstract: Provided are a pressure-sensitive adhesive tape, a polishing pad, a method of manufacturing the same, a polishing device and a method of manufacturing a glass substrate. The illustrative pressure-sensitive adhesive tape may be a pressure-sensitive adhesive tape for a polishing material. The pressure-sensitive adhesive tape may be effectively fixed to a surface plate without bubbles, and have excellent resistance to water and a polishing solution and shear strength applied in a polishing process. In addition, the pressure-sensitive adhesive tape may be easily removed from a carrier or surface plate for a polishing pad without residues after polishing.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: October 31, 2017
    Assignee: LG CHEM, LTD.
    Inventors: Se Woo Yang, Suk Ky Chang, Min Soo Park
  • Patent number: 9748144
    Abstract: First and second semiconductor structures, a CESL, and an ILD layer are formed on a substrate. The first semiconductor structure includes first dummy gate, first nitride mask, and first oxide mask. The second semiconductor structure includes second dummy gate, second nitride mask, and second oxide mask. A first planarization is performed to remove a portion of the ILD layer, exposing CESL. A portion of the CESL, a portion of the ILD layer, the first and the second oxide masks are removed. A hard mask layer is formed on the first and the second nitride masks, and in a recess of the ILD layer. A second planarization is performed to remove a portion of the hard mask layer, the first and the second nitride masks, exposing first and second dummy gates. A remaining portion of the hard mask layer covers the ILD layer.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: August 29, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Ling Lin, Yi-Wen Chen, Chen-Ming Huang, Ren-Peng Huang, Ching-Fu Lin
  • Patent number: 9728622
    Abstract: Forming a dummy gate on a semiconductor device is disclosed. A first sacrificial layer is formed on a fin, and a second sacrificial layer is formed on the first sacrificial layer. A first hardmask layer is formed on the second sacrificial layer, and a second hardmask layer is formed on the first hardmask layer and patterned. The first hardmask layer is laterally recessed in a lateral direction under the second hardmask layer. The first and second sacrificial layers are etched to a corresponding width of the first hardmask layer. A spacer layer is formed on the fin, the first sacrificial layer, second sacrificial layer, the first hardmask layer and the second hardmask layer. The spacer layer is etched until it remains on a sidewall of the first sacrificial layer, the second sacrificial layer and the first hardmask layer, wherein the first and second sacrificial layers form the dummy gate.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: August 8, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
  • Patent number: 9631121
    Abstract: A polishing composition is used to polish a polishing subject having a phase change alloy. The polishing composition includes abrasive grains and a brittle film formation agent. The brittle film formation agent is at least one or more selected from a saturated monocarboxylic acid and an organophosphorus compound.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: April 25, 2017
    Assignee: FUJIMI INCORPORATED
    Inventors: Yukinobu Yoshizaki, Yoshihiro Izawa
  • Patent number: 9627216
    Abstract: Embodiments of methods for forming features in a silicon containing layer of a substrate disposed on a substrate support are provided herein. In some embodiments, a method for forming features in a silicon containing layer of a substrate disposed on a substrate support in a processing volume of a process chamber includes: exposing the substrate to a first plasma formed from a first process gas while providing a bias power to the substrate support, wherein the first process gas comprises one or more of a chlorine-containing gas or a bromine containing gas; and exposing the substrate to a second plasma formed from a second process gas while no bias power is provided to the substrate support, wherein the second process gas comprises one or more of an oxygen-containing gas or nitrogen gas, and wherein a source power provided to form the first plasma and the second plasma is continuously provided.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: April 18, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Byungkook Kong, Hoon Sang Lee, Jinsu Kim, Ho Jeong Kim, Xiaosong Ji, Hun Sang Kim, Jinhan Choi
  • Patent number: 9589799
    Abstract: Methods of forming high etch selectivity, low stress ashable hard masks using plasma enhanced chemical vapor deposition are provided. In certain embodiments, the methods involve pulsing low frequency radio frequency power while keeping high frequency radio frequency power constant during deposition of the ashable hard mask using a dual radio frequency plasma source. According to various embodiments, the low frequency radio frequency power can be pulsed between non-zero levels or by switching the power on and off. The resulting deposited highly selective ashable hard mask may have decreased stress due to one or more factors including decreased ion and atom impinging on the ashable hard mask and lower levels of hydrogen trapped in the ashable hard mask.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: March 7, 2017
    Assignee: Lam Research Corporation
    Inventors: Sirish K. Reddy, Chunhai Ji, Xinyi Chen, Pramod Subramonium
  • Patent number: 9559103
    Abstract: Provided is a memory device. The memory device includes a substrate including a cell area and a peripheral area; gate line stacks and bit line stacks configured to vertically cross in the cell area; buried contacts disposed in areas, which are simultaneously shared by neighboring gate line stacks and neighboring bit line stacks; expanded landing pads including expanded portions connected to the buried contacts and expanded over adjacent bit line stacks, and disposed in a row; landing pads spaced apart from the expanded landing pads as a column, connected to the buried contacts, and having horizontal widths smaller than those of the expanded landing pads; and first storage nodes connected to the expanded portions of the expanded landing pads, and second storage nodes connected to the landing pads.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: January 31, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Je-Min Park, Tae-Jin Park, Yong-Kwan Kim, Yoo-Sang Hwang
  • Patent number: 9533445
    Abstract: Methods for nanoimprint lithography using a deformable mold. Generally, the method includes a deformable mold fixed firmly onto a hollow mold holder around its full periphery is attached to top inner surface of the chamber and positioned underneath the transparent section. The central area of the mold is freely accessible from underneath through the opening of the mold holder. At beginning of the imprinting, the substrate with a layer of resist is positioned underneath the mold at a predetermined gap between them and a substrate is moved up to contact with the mold either under vacuum or under atmosphere. After consolidating the resist, the substrate is separated from the mold by either direct pull-down enabled by stage movement or deforming the mold enabled by differential pressure between the mold mini-chamber and the bulk volume of the chamber, or mixing of both.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: January 3, 2017
    Assignee: NANONEX CORPORATION
    Inventors: Wei Zhang, Hua Tan, Lin Hu, Stephen Y. Chou
  • Patent number: 9525041
    Abstract: A semiconductor process for forming gates with different pitches includes the following steps. A gate layer is formed on a substrate. A first mandrel and a second mandrel are respectively formed on the gate layer. A first spacer material is formed to conformally cover the first mandrel but exposing the second mandrel. A second spacer material is formed to conformally cover the first spacer material and the second mandrel. The first spacer material and the second spacer material are etched to form a first spacer beside the first mandrel and a second spacer beside the second mandrel simultaneously. The first mandrel and the second mandrel are removed. Layouts of the first spacer and the second spacer are transferred to the gate layer, thereby a first gate and a second gate being formed. Moreover, a semiconductor process, which forms the first spacer and the second spacer separately, is also provided.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: December 20, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 9500541
    Abstract: A method and a device for determining the pressure distribution for bonding of a first substrate to a second substrate, with the following steps, especially with the following sequence: placing a measurement layer between a first tool for holding the first substrate and an opposite second tool which is aligned to the first tool for bonding of the substrate, deformation of the measurement layer by bringing the tools closer to one another, measurement of the deformation of the measurement layer and computation of the pressure distribution.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: November 22, 2016
    Assignee: EV Group E. Thallner GmbH
    Inventors: Bernhard Rebhan, Markus Wimplinger, Jürgen Burggraf
  • Patent number: 9496145
    Abstract: An electrochemical process for applying a conductive film onto a substrate having a seed layer includes placing the substrate into contact with an electrochemical plating bath containing cobalt or nickel, with the plating bath having pH of 4.0 to 9.0. Electric current is conducted through the bath to the substrate. The cobalt or nickel ions in the bath deposit onto the seed layer. The plating bath may contain cobalt chloride and glycine. The electric current may range from 1-50 milli-ampere per square cm. After completion of the electrochemical process, the substrate may be removed from the plating bath, rinsed and dried, and then annealed at a temperature of 200 to 400 C to improve the material properties and reduce seam line defects. The plating and anneal process may be performed through multiple cycles.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: November 15, 2016
    Assignee: APPLIED Materials, Inc.
    Inventors: John W. Lam, Ismail Emesh, Roey Shaviv
  • Patent number: 9484212
    Abstract: A chemical mechanical polishing method is provided comprising: providing a substrate, wherein the substrate comprises a silicon oxide and a silicon nitride; providing a polishing slurry; providing polishing pad, comprising: a polishing layer having a composition that is a reaction product of ingredients, comprising: a polyfunctional isocyanate and an amine initiated polyol curative; wherein the stoichiometric ratio of the amine initiated polyol curative to the polyfunctional isocyanate is selected to tune the removal rate selectivity of the polishing layer; creating dynamic contact between the polishing surface and the substrate; dispensing the polishing slurry on the polishing pad at or near the interface between the polishing surface and the substrate; and, removing at least some of the silicon oxide and the silicon nitride from the substrate.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: November 1, 2016
    Assignees: Rohm and Haas Electronic Materials CMP Holdings, Inc., Dow Global Techologies LLC
    Inventors: Bainian Qian, Yi Guo, Marty W. DeGroot, George C. Jacob