Abstract: The present disclosure is directed to techniques of zone-based target control in chemical mechanical polishing of wafers. Multiple zones are identified on a surface of a wafer. The CMP target is achieved on each zone in a sequence of CMP processes. Each CMP process in the sequence achieves the CMP target for only one zone, using a CMP process selective to other zones.

Abstract: Generating a recipe for controlling a polishing system includes receiving a target removal profile that includes a target thickness to remove for a plurality of locations on a substrate that are angularly distributed around the substrate, and storing a first function defining a polishing rate for a zone from a plurality of pressurizable zones of a carrier head that are angularly distributed around a the carrier head. The first function defines polishing rates as a function of pressures. For each particular zone of the plurality of zones a recipe defining a pressure for the particular zone over time is calculated by calculating an expected thickness profile after polishing using the first function, and minimizing a cost function that incorporates a first term representing a difference between the expected thickness profile and a target thickness profile.

Abstract: Described herein are etching solutions and method of using the etching solutions suitable for etching aluminum nitride (AlN) from a semiconductor substrate during the manufacture of a semiconductor device comprising AlN and silicon material without harming the silicon material. The etching solution comprises a cationic surfactant, water, a base, and a water-miscible organic solvent.

Abstract: A three-dimensional semiconductor memory device may include horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other, memory structures provided on the horizontal patterns, respectively, each of the memory structures including a three-dimensional arrangement of memory cells. Penetrating insulating patterns and separation structures may isolate the horizontal patterns from one another. Through vias may extend through the penetrating insulating patterns to connect logic circuits of the peripheral circuit structure to the memory structure.

Abstract: Apparatus and methods for providing backside pressure control and edge purge gas to a substrate in a processing chamber. A seal band within a pocket of a substrate support defines an inner pocket region and an outer pocket region. The seal band has a pressure dependent controlled leakage rate so that a backside gas flow to the inner pocket region can diffuse through the seal band to the outer pocket region to create an edge purge while providing backside pressure to the substrate. Processing chambers, methods of processing a substrate and non-transitory computer-readable medium containing instructions to process a substrate are also disclosed.

Abstract: In an embodiment, a chemical mechanical planarization (CMP) system includes: a monolithic platen within a platen housing, wherein the monolithic platen is formed of a single piece of material, wherein the monolithic platen includes: a first portion within a first opening, and a second portion within a second opening, wherein the first portion has a different diameter than the second portion; and a polishing fluid delivery module above the monolithic platen, wherein the polishing fluid delivery module is configured to deliver slurry to the monolithic platen during performance of CMP.

Abstract: Embodiments of a three-dimensional (3D) memory device and a method of operating the 3D memory device are provided. The 3D memory device includes an array of 3D NAND memory cells, an array of static random-access memory (SRAM) cells, and a peripheral circuit. The array of SRAM cells and the peripheral circuit arranged at one side are bonded with the array of 3D NAND memory cells at another side to form a chip. Data is received from a host through the peripheral circuit, buffered in the array of SRAM cells, and transmitted from the array of SRAM cells to the array of 3D NAND memory cells. The data is programmed into the array of 3D NAND memory cells.

Abstract: A polishing system includes a platen having a top surface to support a main polishing pad. The platen is rotatable about an axis of rotation that passes through approximately the center of the platen. An annular flange projects radially outward from the platen to support an outer polishing pad. The annular flange has an inner edge secured to and rotatable with the platen and vertically fixed relative to the top surface of the platen. The annular flange is vertically deflectable such that an outer edge of the annular flange is vertically moveable relative to the inner edge. An actuator applies pressure to an underside of the annular flange in an angularly limited region, and a carrier head holds a substrate in contact with the polishing pad and is movable to selectively position a portion of the substrate over the outer polishing pad.

Abstract: A transistor device includes a substrate, a fin structure extending on the substrate in a direction parallel to a top surface of the substrate, a source region and a drain region provided at an upper portion of the fin structure, a constant current generating layer provided at a lower portion of the fin structure, a gate insulating film provided on both side surfaces and a top surface of the upper portion of the fin structure, and a gate electrode provided on the gate insulating film, wherein the gate electrode is provided on the fin structure and between the source region and the drain region, the constant current generating layer generates a constant current between the drain region and the substrate, and the constant current is independent from a gate voltage applied to the gate electrode.

Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a first metal line extending along a first direction, a second metal line lengthwise aligned with and spaced apart from the first metal line, and a third metal line extending along the first direction. The third metal line includes a branch extending along a second direction perpendicular to the first direction and the branch partially extends between the first metal line and the second metal line.

Abstract: A carrier head for holding a substrate in a polishing system includes a housing, a first flexible membrane secured to the housing to form one or more pressurizable chambers to apply pressure through a central membrane portion of the first flexible membrane to a central portion of a substrate, and a plurality of independently operable piezoelectric actuators supported by the housing, the plurality of piezoelectric actuators positioned radially outward of the central membrane portion and at different angular positions so as to independently adjust pressure on a plurality of angular zones in an annular outer region of the substrate surrounding the central portion of the substrate.

Abstract: A polishing system includes a platen having a top surface to support a main polishing pad. The platen is rotatable about an axis of rotation that passes through approximately the center of the platen. An annular flange projects radially outward from the platen to support an outer polishing pad. The annular flange has an inner edge secured to and rotatable with the platen and vertically fixed relative to the top surface of the platen. The annular flange is vertically deflectable such that an outer edge of the annular flange is vertically moveable relative to the inner edge. An actuator applies pressure to an underside of the annular flange in an angularly limited region, and a carrier head holds a substrate in contact with the polishing pad and is movable to selectively position a portion of the substrate over the outer polishing pad.

Abstract: A method of forming an ultrasonic transducer device involves depositing a first layer on a substrate, depositing a second layer on the first layer, patterning the second layer at a region corresponding to a location of a transducer cavity, depositing a third layer that refills regions created by patterning the second layer, planarizing the third layer to a top surface of the second layer, removing the second layer, conformally depositing a fourth layer over the first layer and the third layer, defining the transducer cavity in a support layer formed over the fourth layer; and bonding a membrane to the support layer.

Abstract: A polishing pad is described. The polishing pad includes a surface having plural recess portions, and a substrate is polished by the surface. In the pad, an average width of the recess portions at one area of the surface in a direction parallel to the surface is 20 ?m or less, and an average density of the recess portions at one area of the surface is 1,300/mm2 or more.

Abstract: A method of depositing a metal material on an isolated seed layer uses a barrier layer as a conductive path for plating. The method may include depositing a barrier layer on a substrate wherein the barrier layer provides adhesion for seed layer material and inhibits migration of the seed layer material, forming at least one isolated seed layer area on the barrier layer on the substrate, and depositing the metal material on the at least one isolated seed layer area using an electrochemical deposition process wherein the barrier layer provides a current path to deposit the metal material on the at least one isolated seed layer area.

Abstract: Composite dielectric structures for semiconductor die assemblies, and associated systems and methods are disclosed. In some embodiments, the composite dielectric structure includes a flexible dielectric layer configured to conform to irregularities (e.g., particles, defects) at a bonding interface of directly bonded semiconductor dies (or wafers). The flexible dielectric layer may include a polymer material configured to deform in response to localized pressure generated by the irregularities during bonding process steps. The composite dielectric structure includes additional dielectric layers sandwiching the flexible dielectric layer such that the composite dielectric structure can provide robust bonding strength to other dielectric layers through the additional dielectric layers. In some embodiments, a chemical vapor deposition process may be used to form the composite dielectric structure utilizing siloxane derivatives as a precursor.

Abstract: An apparatus for detecting an endpoint of a grinding process includes a connecting device, a timer and a controller. The connecting device is connected to a sensor that periodically senses an interface of a reconstructed wafer comprising a plurality of dies of at least two types to generate a thickness signal comprising thicknesses from a surface of an insulating layer of the reconstructed wafer to the interface of the reconstructed wafer. The timer is configured to generate a clock signal having a plurality of pulses with a time interval. The controller is coupled to the sensor and the timer, and configured to filter the thickness signal according to the clock signal to output a thickness extremum among the thicknesses in the thickness signal within each time interval, wherein the thickness signal after the filtering is used to determine the endpoint of the grinding process being performed on the reconstructed wafer.

Abstract: Methods for polishing dielectric layers using an auto-stop slurry in forming semiconductor devices, such as three-dimensional (3D) memory devices, are provided. The methods include forming a stack structure in a staircase region and a core array region, the stack structure including a staircase structure in the staircase region; forming a dielectric layer over the staircase region and a peripheral region outside the stack structure; and polishing the dielectric layer using an auto-stop slurry containing a ceria-based abrasive.

Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first metal layer over a substrate, forming a dielectric layer over the first metal layer. The method includes forming a trench in the dielectric layer, and performing a surface treatment process on a sidewall surface of the trench to form a hydrophobic layer. The hydrophobic layer is formed on a sidewall surface of the dielectric layer. The method further includes depositing a metal material in the trench and over the hydrophobic layer to form a via structure.

Abstract: A method for selectively forming a silicon nitride film on a substrate comprising a first metallic surface and a second dielectric surface by a cyclical deposition process is disclosed. The method may comprise contacting the substrate with a first reactant comprising a silicon halide source and contacting the substrate with a second reactant comprising a nitrogen source, wherein the incubation period for the first metallic surface is less than the incubation period for the second dielectric surface. Semiconductor device structures comprising a selective silicon nitride film are also disclosed.

Abstract: A polishing pad useful in chemical mechanical polishing can comprise a base pad having a top surface and surface, a plurality of polishing elements each having a top polishing surface and a bottom surface, and wherein each of the plurality of polishing elements is connected to the top surface of the base pad to the polishing element by three or more supports wherein the bottom surface of the polishing element, the top surface of the base pad and the supports define a region comprising at least one void and there are openings between the three or more supports. Such pad can be used in a method by providing a substrate and polishing the substrate with the pad, optionally, with a polishing medium.

Abstract: Exemplary methods of semiconductor processing may include providing a boron-and-carbon-and-nitrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include generating a capacitively-coupled plasma of the boron-and-carbon-and-nitrogen-containing precursor. The methods may include forming a boron-and-carbon-and-nitrogen-containing layer on the substrate. The boron-and-carbon-and-nitrogen-containing layer may be characterized by a dielectric constant below or about 3.5.

Abstract: A wafer shape metrology system includes a wafer shape metrology sub-system configured to perform one or more stress-free shape measurements on a first wafer, a second wafer, and a post-bonding pair of the first and second wafers. The wafer shape metrology system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller is configured to receive stress-free shape measurements from the wafer shape sub-system; predict overlay between one or more features on the first wafer and the second wafer based on the stress-free shape measurements of the first wafer, the second wafer, and the post-bonding pair of the first wafer and the second wafer; and provide a feedback adjustment to one or more process tools based on the predicted overlay. Additionally, feedforward and feedback adjustments may be provided to one or more process tools.

Abstract: The present disclosure provides a new corrosion control chemistry for use in ruthenium (Ru) chemical-mechanical polishing (CMP) processes. More specifically, the present disclosure provides an improved CMP slurry chemistry and CMP process for planarizing a ruthenium surface. In the CMP process disclosed herein, a ruthenium surface (e.g., a post-etch ruthenium surface) is exposed to a CMP slurry containing a halogenation reagent, which reacts with the ruthenium surface to create a halogenated ruthenium surface, and a ligand for ligand-assisted reactive dissolution of the halogenated ruthenium surface. Relative amounts of the halogenation agent and the ligand can be controlled in the CMP slurry, so as to provide a diffusion-limited etch process that improves pos-etch surface morphology, while providing high material removal rates.

Abstract: A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view.

Abstract: A semiconductor device may include active pattern, a silicon liner, an insulation layer, an isolation pattern and a transistor. The active pattern may protrude from a substrate. The silicon liner having a crystalline structure may be formed conformally on surfaces of the active pattern and the substrate. The insulation layer may be formed on the silicon liner. The isolation pattern may be formed on the insulation layer to fill a trench adjacent to the active pattern. The transistor may include a gate structure and impurity regions. The gate structure may be disposed on the silicon liner, and the impurity regions may be formed at the silicon liner and the active pattern adjacent to both sides of the gate structure.

Abstract: An apparatus for chemical mechanical polishing includes a rotatable platen having a surface to support a polishing pad, a carrier head to hold a substrate in contact with the polishing pad, and a polishing liquid distribution system. The polishing liquid distribution system includes a dispenser positioned to deliver a polishing liquid to a portion of a polishing surface of the polishing pad, and a first barrier positioned before the portion of the polishing surface and configured to block used polishing liquid from reaching the portion of the polishing surface.

Abstract: An apparatus for marking a component by applying readable identifying information is provided. The identifying information has at least one identifying feature, in particular an identifying symbol. The apparatus includes a detection device which is designed to detect, on the basis of an eddy current measurement, identifying information applied or to be applied to a component by way of the apparatus.

Abstract: A composition is provided that comprises a calcium carbonate slurry. The calcium carbonate slurry comprises a plurality of calcium carbonate particles suspended in a solution, where the solution comprises a dispersant and an anionic surfactant. The concentration of the calcium carbonate particles in the calcium carbonate slurry is equal to or less than about 2.0 wt. %.

Abstract: The invention provides a chemical-mechanical polishing composition comprising: (a) a silica abrasive, (b) a surfactant, (c) an iron cation, (d) optionally a ligand, and (e) water, wherein the silica abrasive has a negative zeta potential in the chemical-mechanical polishing composition. The invention also provides a method of chemically-mechanically polishing a substrate, especially a substrate comprising a carbon-based film, using said composition.

Abstract: A method for producing a balloon for a balloon catheter includes providing the balloon that has an outer surface. A solution including a solvent and a polymer is used to deposit the polymer onto the surface and form a surface coating of the polymer.

Abstract: The present invention provides CMP polishing pads or layers having a unfilled Shore D (2 second) hardness of from 57-77 or a filled Shore D (2 second) hardness of from 18-50, made from a two-component reaction mixture of (i) a liquid aromatic isocyanate component comprising one or more aromatic diisocyanates or a linear aromatic isocyanate-terminated urethane prepolymer having an unreacted isocyanate (NCO) concentration of from 18 to 47 wt. %, based on the total solids weight of the aromatic isocyanate component, and (ii) a liquid polyol component including one or more curatives selected from the group of amines defined by Formulas (I) and (II).

Abstract: The present disclosure relates to a method for forming a semiconductor structure includes depositing a dielectric layer on a substrate and depositing a patterning layer on the dielectric layer. The method also includes performing a first etching process on the patterning layer to form a first region including a first plurality of blocks at a first pattern density and a second region including a second plurality of blocks at a second pattern density that is lower than the first pattern density. The method also includes performing a second etching process on the second plurality of blocks to decrease a width of each block of the second plurality of blocks and etching the dielectric layer and the substrate using the first and second pluralities of blocks to form a plurality of fin structures.

Abstract: An object of the present invention is to provide a polishing composition that can achieve both a high polishing removal rate and high surface quality. According to the present invention, provided is a polishing composition for polishing a material to be polished. The polishing composition contains sodium metavanadate, hydrogen peroxide, and silica abrasive. The content C1 of sodium metavanadate is 0.7% to 3.5% by weight, the content C2 of hydrogen peroxide is 0.3% to 3% by weight, and the content C3 of the silica abrasive is 12% to 50% by weight.

Abstract: A semiconductor manufacturing apparatus includes a sound measuring unit that measures a first polishing sound of a film formed on a wafer, a sound pressure prediction regression model generation unit that generates a first regression model for obtaining a first sound pressure prediction value of the first polishing sound, a sound pressure prediction value calculation unit that performs a first calculation of the first sound pressure prediction value by using the first regression model, a residual difference calculation unit that performs a second calculation of a first residual difference, the first residual difference being a difference between a first sound pressure actual measurement value of the first polishing sound and the first sound pressure prediction value, and an end point determination unit that determines a polishing end point of the film by using the first residual difference.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.

Abstract: Described herein are methods and systems for manufacturing composite stringers using independently movable pallets with independent vacuum controls. Specifically, a stringer forming system comprises a base plate and a plurality of sets of pallets (e.g., two or more sets of pallets), slidably coupled to the base plate and forming an adjustable cavity. Each pallet comprises a primary vacuum zone, fluidly connected to a separate vacuum port. The system allows for independent application of a reduced pressure to the primary vacuum zone of each pallet. For example, a reduced pressure is applied only to pallets that are already covered with a composite layup and to pallets that are being covered. Any pallets that are exposed are kept at an ambient pressure and decoupled from a vacuum source, thereby reducing the vacuum leakage through the overall system. As the composite layup is being formed over new pallets, these new pallets are subjected to the reduced pressure.

Abstract: Embodiments of the present disclosure generally provide methods, polishing systems with computer readable medium having the methods stored thereon, to facilitate consistent tensioning of a polishing article disposed on a web-based polishing system. In one embodiment, a substrate processing method includes winding a used portion of a polishing article onto a take-up roll of a polishing system by rotating a first spindle having the take-up roll disposed thereon; measuring, using an encoder wheel, a polishing article advancement length of the used portion of the polishing article wound onto the take-up roll; determining a tensioning torque to apply to a supply roll using the measured polishing article advancement length; and tensioning the polishing article by applying the tensioning torque to the supply roll.

Abstract: A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.

Abstract: An integrated circuit structure comprises a first and second conductive structures formed in an interlayer dielectric (ILD) of a metallization stack over a substrate. The first conductive structure comprises a first conductive line, and first dummy structures located adjacent to one or more sides of the first conductive line, wherein the first dummy structures comprise respective arrays of dielectric core segments having a Young's modulus larger than the Young's modulus of the ILD, the dielectric core segments being approximately 1-3 microns in width and spaced apart by approximately 1-3 microns. The second conductive structure formed in the ILD comprises a conductive surface and second dummy structures formed in the conductive surface, where the second dummy structures comprising an array of conductive pillars.

Abstract: A method for forming a semiconductor memory structure includes providing a semiconductor substrate; forming a hard mask layer on the semiconductor substrate; forming a contact opening corresponding to the pair of word lines through the hard mask layer and a portion of the semiconductor substrate; forming a pair of spacers on sidewalls of the contact opening; filling the contact opening with a conductive material to form a contact; forming a bit line directly above the contact and the pair of spacers, and forming a dielectric liner on sidewalls of the bit line. The pair of word lines is embedded in an active region of the semiconductor substrate and extends in a first direction. The bit line extends in a second direction. The first direction is perpendicular to the second direction.

Abstract: Crystal plane orientation enrichment compounds are applied to copper to modify copper grain orientation distribution to the favorable crystal plain orientation to enhance copper electroplating. Electroplating copper on the modified copper enables faster and selective electroplating.

Abstract: A system for performing a chemical mechanical polishing (CMP) process is provided. The system includes a CMP tool configured to polish a semiconductor wafer. The processing system further includes a wafer stage configured to support the semiconductor wafer for facilitating the insertion of the semiconductor wafer into, and its subsequent removal from, the CMP tool. The processing system also includes a number of spray nozzles positioned relative to the wafer stage. In addition, the processing system includes a spray generator connected to the spray nozzles and configured to convert a mixture to a mist spray. The processing system further includes a controller configured to activate flow of the mist spray from the spray generator to the spray nozzles to discharge the mist spray over the semiconductor wafer supported by the wafer stage.

Abstract: A ruthenium film forming method includes: causing chlorine to be adsorbed to an upper portion of a recess at a higher density than to a lower portion of the recess by supplying a chlorine-containing gas to a substrate including an insulating film and having the recess; and forming a ruthenium film in the recess by supplying a Ru-containing precursor to the recess to which the chlorine is adsorbed.

Abstract: Provided are a 3D flash memory and an array layout thereof. The 3D flash memory includes a gate stack structure, a annular channel pillar, a first source/drain pillar, a second source/drain pillar and a charge storage structure. The gate stack structure is disposed on a dielectric base and includes a plurality of gate layers electrically insulated from each other. The annular channel pillar is disposed on the dielectric base and penetrates through the gate stack structure. The first source/drain pillar and the second source/drain pillar are disposed on the dielectric base, are located within the channel pillar and penetrate through the gate stack structure. The first source/drain pillar and the second source/drain pillar are separated from each other and are each connected to the channel pillar. The charge storage structure is disposed between each of the plurality of gate layers and the channel pillar.

Abstract: Integrated circuits including selectable vias are disclosed. The techniques are particularly well-suited to back end of line (BEOL) processes. In accordance with some embodiments, a selectable via includes a vertically-oriented thin film transistor structure having a wrap around gate, which can be used to effectively select (or deselect) the selectable via ad hoc. When a selectable via is selected, a signal is allowed to pass through the selectable via. Conversely, when the selectable via is not selected, a signal is not allowed to pass through the selectable via. The selectable characteristic of the selectable via allows multiple vias to share a global interconnect. The global interconnect can be connected to any number of selectable vias, as well as standard vias.

Abstract: A substrate carrier configured to be attached to a polishing system for polishing a substrate is described herein. The substrate carrier includes a housing including a plurality of load couplings and a retaining ring coupled to the housing. The retaining ring can include an annular body having a central axis, an inner edge facing the central axis of the annular body, the inner edge having a diameter configured to surround a substrate, and an outer edge opposite the inner edge, wherein the plurality of load couplings contact the retaining ring at different radial distances measured from the central axis, and wherein the plurality of load couplings are configured to apply a radially differential force to the retaining ring.

Abstract: The present invention relates to methods of delayering a semiconductor integrated circuit die or wafer. In at least one aspect, the method includes exposing a die or wafer to plasma of an etching gas and detecting exposure of one or more metal layers within the die. In one aspect of the invention, the plasma of the etching gas is non-selective and removes all materials in a layer at about the same rate. In another aspect of the invention, two different plasmas of corresponding etching gases are employed with each plasma of the etching gas being selective, thus necessitating the sequential use of both plasmas of corresponding etching gases to remove all materials in a layer.

Abstract: Polishing liquid comprising abrasive grains, a phosphonic acid compound having a molecular weight of 210 or more, and at least one selected from the group consisting of amino acids and amino acid derivatives, in which a silanol group density of the abrasive grains is 6.5 groups/nm2 or less, and a degree of association of the abrasive grains is 1.5 or more.