Abstract: The present disclosure describes an apparatus and a method to detect a polishing pad profile during a polish process and adjust the polishing process based on the detected profile. The apparatus can include a polishing pad configured to polishing a substrate, a substrate carrier configured to hold the substrate against the polishing pad, and a detection module configured to detect a profile of the polishing pad. The detection module can include a probe configured to measure a thickness of one or more areas on the polishing pad, and a beam configured to support the probe, where the probe can be further configured to move along the beam.

Abstract: An electronic substrate may be fabricated having at least two glass layers separated by an etch stop layer, wherein a bridge is embedded within one of the glass layers. The depth of a cavity formed for embedding the bridge is control by the thickness of the glass layer rather than by controlling the etching process used to form the cavity, which allows for greater precision in the fabrication of the electronic substrate. In an embodiment of the present description, an integrated circuit package may be formed with the electronic substrate, wherein at least two integrated circuit devices may be attached to the electronic substrate, such that the bridge provides device-to-device interconnection between the at least two integrated circuit devices. In a further embodiment, the integrated circuit package may be electrically attached to an electronic board.

Abstract: A method of planarizing a device having a surface topography with at least one material at a surface of the device is described. The method comprises the steps of depositing a stop layer over at least a portion of the at least one material which substantially retains the surface topography of the device. A sacrificial layer is deposited over at least a portion of the stop layer. A planarization process is performed on the device. The planarization process includes the steps of performing a chemical mechanical polish (CMP) on the top surface of the sacrificial layer. A physical removal step is conducted on the remainder portion of the sacrificial layer to form a planarized surface. A second CMP step and a second physical removal step are conducted, to form a planarized device.

Abstract: An object of the invention is to provide a cleaning liquid for semiconductor substrates having undergone a chemical mechanical polishing process, the cleaning liquid being excellent in corrosion prevention properties and defect suppression performance with respect to a metal film. Another object of the invention is to provide a method of cleaning semiconductor substrates having undergone a chemical mechanical polishing process. A cleaning liquid of the invention is used for semiconductor substrates having undergone a chemical mechanical polishing process and includes: an amine oxide compound that is a compound having an amine oxide group, or its salt; and at least one hydroxylamine compound selected from the group consisting of a hydroxylamine, a hydroxylamine derivative, and their salts, and the amine oxide compound content is 0.00001 to 0.15 mass % based on the total mass of the cleaning liquid.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first metal layer over a substrate, forming a dielectric layer over the first metal layer. The method includes forming a trench in the dielectric layer, and performing a surface treatment process on a sidewall surface of the trench to form a hydrophobic layer. The hydrophobic layer is formed on a sidewall surface of the dielectric layer. The method further includes depositing a metal material in the trench and over the hydrophobic layer to form a via structure.

Abstract: Shallow Trench Isolation (STI) chemical mechanical planarization (CMP) polishing compositions, methods and systems of use therefore are provided. The CMP polishing composition comprises abrasives of ceria coated inorganic oxide particles, such as ceria-coated silica; and dual chemical additives for providing the tunable oxide film removal rates and tunable SiN film removal rates; low oxide trench dishing, and high oxide: SiN selectivity. Dual chemical additives comprise at least one silicone-containing compound comprising at least one of (1) ethylene oxide and propylene oxide (EO-PO) group, and at least one of substituted ethylene diamine group on the same molecule; and (2) at least one non-ionic organic molecule having at least two, preferably at least four hydroxyl functional groups.

Abstract: A ruthenium film forming method includes: causing chlorine to be adsorbed to an upper portion of a recess at a higher density than to a lower portion of the recess by supplying a chlorine-containing gas to a substrate including an insulating film and having the recess; and forming a ruthenium film in the recess by supplying a Ru-containing precursor to the recess to which the chlorine is adsorbed.

Abstract: Methods for forming a topographically selective silicon oxide film by a cyclical plasma-enhanced deposition process are provided. The methods may include: forming a topographically selective silicon oxide film by a plasma enhanced atomic layer deposition (PEALD) process or a cyclical plasma-enhanced chemical vapor deposition (cyclical PECVD) process. The methods may also include: forming a silicon oxide film either selectivity over the horizontal surfaces of a non-planar substrate or selectively over the vertical surfaces of a non-planar substrate.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a gate structure over the substrate. The semiconductor device structure also includes a spacer element covering a first sidewall of the gate structure. The semiconductor device structure further includes a source/drain portion in the substrate, and the spacer element is between the source/drain portion and the gate structure. In addition, the semiconductor device structure includes an etch stop layer covering the source/drain portion. The etch stop layer includes a first nitride layer covering the source/drain portion and having a second sidewall, and the second sidewall is in direct contact with the spacer element. The etch stop layer also includes a first silicon layer covering the first nitride layer and having a third sidewall, and the third sidewall is in direct contact with the spacer element.

Abstract: A substrate processing apparatus includes a chamber, a holding unit, a hydrophobizing agent nozzle, a first organic solvent nozzle, a second organic solvent nozzle, and an exhaust port. The chamber has a gastight space that is capable of accommodating the plurality of substrates. The holding unit lifts or lowers the plurality of substrates between a storage area where a liquid is stored in the gastight space and a drying area that is located above the storage area in the gastight space. The hydrophobizing agent nozzle supplies a vapor of a hydrophobizing agent to the drying area. The first organic solvent nozzle supplies an organic solvent from the drying area to the storage area. The second organic solvent nozzle supplies a vapor of an organic solvent to the drying area. The exhaust port discharges a gas in the gastight space.

Abstract: A polishing slurry composition is provided. The polishing slurry composition includes polishing particles, a first polishing inhibitor containing a hydrophobic amino acid, and a second polishing inhibitor containing a cyclic polymer, and the first polishing inhibitor and the second polishing inhibitor are different.

Abstract: A method of forming a memory device having magnetic tracks individually comprising a plurality of magnetic domains having domain walls, includes forming an elevationally outer substrate material of uniform chemical composition. The uniform composition material is partially etched into to form alternating regions of elevational depressions and elevational protrusions in the uniform composition material. A plurality of magnetic tracks is formed over and which angle relative to the alternating regions. Interfaces of immediately adjacent of the regions individually form a domain wall pinning site in individual of the magnetic tracks. Other methods, including memory devices independent of method, are disclosed.

Abstract: A manufacturing method for a semiconductor structure includes: patterning and etching a semiconductor substrate to form a concave region; forming a first protective layer on a surface of the semiconductor substrate, the surface of the semiconductor substrate being a surface of a non-etched region except the concave region; forming an isolation structure in the concave region; and removing the first protective layer on the surface of the semiconductor substrate.

Abstract: A binding capacity evaluation apparatus includes a first solution tank into which a first solution is input, the first solution including a hydrophobic substance and a hydrophilic substance; a second solution tank into which a second solution is input, the second solution including water as a major component; a light irradiation device irradiating light on a third solution including a mixture of the first and second solutions; a light-receiving device receiving light passing through the third solution; and a light transmittance measuring device measuring light transmittance by using an intensity of the light received by the light-receiving device. The apparatus uses the light transmittance to detect when the hydrophobic substance becomes supersaturated in the second solution.

Abstract: A curable composition on a substrate is cured in a state where a member is in contact with the curable composition. Thereafter, the member having adhered to the curable composition is separated from the substrate, whereby the curable composition and a particle are removed from the substrate.

Abstract: Provided is a polishing composition for semiconductor wiring providing an excellent polishing rate and preventing occurrence of dishing. The polishing composition for semiconductor wiring according to the present invention contains a compound represented by Formula (1) below: R1O—(C3H6O2)n—H??(1) where R1 represents a hydrogen atom, a hydrocarbon group that has from 1 to 24 carbon atoms and may include a hydroxyl group, or a group represented by R2CO, where the R2 represents a hydrocarbon group having from 1 to 24 carbon atoms; and n represents an average degree of polymerization of glycerol units shown in the parentheses and is from 2 to 60.

Abstract: Embodiments herein include carrier loading stations and methods related thereto which may be used to beneficially remove nano-scale and/or micron-scale particles adhered to a bevel edge of a substrate before polishing of the substrate. By removing such contaminates, e.g., loosely adhered particles of dielectric material, from the bevel edge, contamination of the polishing interface can be avoided thus preventing and/or substantially reducing scratch related defectivity associated therewith.

Abstract: A CMP slurry composition for polishing a tungsten pattern wafer and a method of polishing a tungsten pattern wafer, the CMP slurry composition including a solvent, the solvent being a polar solvent or a non-polar solvent; an abrasive agent; and a biocide, wherein the abrasive agent includes silica modified with a silane containing two nitrogen atoms or silica modified with a silane containing three nitrogen atoms, the biocide includes a compound of Formula 3:

Abstract: An interconnect structure is formed on a substrate in a semiconductor device. The interconnect structure includes a dielectric layer and a metal layer. The dielectric layer includes a region and a plurality of protrusions. The metal layer is disposed on the region and between the protrusions, wherein tops of the protrusions are exposed with respect to the metal layer. In a top view of the semiconductor device, the protrusions are distributed in the region. Any straight path crossing through a central region of the region is always intersected with a portion of the protrusions.

Abstract: A polishing slurry is disclosed which includes about 0.01 wt % to about 10 wt % of polishing particles, about 0.005 wt % to about 0.1 wt % of a dispersing agent, about 0.001 wt % to about 1 wt % of an oxide-polishing promoter including a pyridine compound, about 0.05 wt % to about 0.1 wt % of a nitride-polishing inhibitor including an amino acid or an anionic organic acid, and water. A method for manufacturing a display device including an active pattern disposed on a base substrate, a gate metal pattern including a gate electrode overlapping the active pattern, a planarized insulation layer disposed on the gate metal pattern, and a source metal pattern disposed on the planarized insulation layer is also disclosed.

Abstract: An imaging device includes a photoelectric conversion layer, a counter electrode provided above the photoelectric conversion layer, a pixel electrode that faces the counter electrode with the photoelectric conversion layer disposed between the counter electrode and the pixel electrode, and a contact plug covered with the pixel electrode and connected to the pixel electrode. The pixel electrode includes a first layer and a second layer provided on the first layer in contact with the first layer. A surface of the first layer that is in contact with the second layer has a protrusion that protrudes upward.

Abstract: The present disclosure relates to a method and apparatus for cleaning a substrate. The method includes rotating a substrate disposed on a substrate support and spraying a front side of the substrate using steam through a front side nozzle assembly. A back side of the substrate is sprayed using steam through a back side dispenser assembly. A heated chemical is dispensed over the front side of the substrate.

Abstract: The present application provides a detection method of metal impurity in wafer. The method comprises conducting a medium temperature thermal treatment for a first predicted time period to the wafer, cooling the wafer and conducting a low temperature thermal treatment for a second predicted time period, cooling the wafer to ambient temperature; providing a liquid of vapor phase decomposition on the wafer to collect metal impurities; atomizing the liquid containing the collected metal impurities, conducting an inductively coupled plasma mass spectrometry analysis and obtaining concentrations of the metal impurities. The present application applies the combination of various thermal treatment without an interrupt of cooling to ambient temperature to contemplate diffusions of various metal impurities to the wafer surface. Accordingly, the detection of metal impurities can be conducted with reduced time cost and enhanced efficiency.

Abstract: A semiconductor wafer dicing process is disclosed for dicing a wafer into individual dies, each die comprising one integrated circuit. The process comprises: disposing a coating upon the wafer; removing at least a portion of the coating to expose regions of the wafer, along which the wafer is to be diced, to form a workpiece; disposing the workpiece upon a platen within a processing chamber; plasma treating the workpiece with a set of plasma treatment conditions to etch a portion of the exposed regions of the wafer to form a wafer groove which extends laterally beneath the coating to form an undercut; and plasma etching the workpiece with a set of plasma etch conditions, which are different to the plasma treatment conditions, to etch through the wafer and dice the wafer along the wafer groove.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a wafer structure. The wafer structure has a normal region and a trimmed region adjacent to the normal region. A top surface of the trimmed region is lower than a top surface of the normal region. The semiconductor structure includes a dielectric layer and a conductive layer disposed on the wafer structure in the normal region and the trimmed region. The semiconductor structure includes a protective layer disposed on a portion of the dielectric layer in the trimmed region and a portion of the conductive layer in the trimmed region. The semiconductor structure includes another dielectric layer disposed on a portion of the dielectric layer in the normal region and a portion of the conductive layer in the normal region and on the protective layer.

Abstract: A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view.

Abstract: A method includes bonding a front side surface of a first wafer to a second wafer; performing a multi-trimming process on the first and second wafers from a back side surface of the first wafer, the multi-trimming process comprising: performing a first trimming step from the back side surface of the first wafer to cut through a periphery of the first wafer; performing a second trimming step on the second wafer to partially cut a periphery of the second wafer to form a first step-like structure; and performing a third trimming step on the second wafer to partially cut the periphery of the second wafer to form a second step-like structure connecting down from the first step-like structure; after performing the multi-trimming process, forming a coating material at least over the periphery of the second wafer.

Abstract: A method for manufacturing a semiconductor device is provided, including: preparing a first chip forming portion having a first semiconductor substrate, first metal pads provided at the substrate and a first circuit electrically connected to at least a part of the pads, and a second chip forming portion having a second semiconductor substrate, second metal pads provided at substrate and a second circuit electrically connected to at least a part of the pads; bonding the first and the second chip forming portions while joining the first and the second pads to form a bonding substrate having a non-bonded region between the first and the second chip forming portions at an outer peripheral portion thereof; and filling an insulating film into the non-bonded region, at least a part of the insulating film containing at least one selected from the group consisting of silicon nitride and nitrogen-containing silicon carbide.

Abstract: A method for manufacturing a structure, including photoelectrochemically etching an etching object, the photoelectrochemical etching of the etching object including: injecting an alkaline or acidic etching solution containing an oxidizing agent that receives electrons, into a rotatably held container in which an etching object at least whose surface is composed of group III nitride is held, and immersing the surface in the etching solution; irradiating the surface of the etching object held in the container with light in a stationary state of the etching object and the etching solution; and rotating the container to scatter the etching solution toward an outer peripheral side, thereby discharging the etching solution from the container, after the surface is irradiated with the light.

Abstract: Aspects of the disclosure provide semiconductor devices. For example, a semiconductor device includes a substrate having a first region and a second region along a first direction that is parallel to a main surface of the substrate. Then, the semiconductor device includes a memory stack that includes a first stack of alternating gate layers and insulating layers and a second stack of alternating gate layers and insulating layers along a second direction that is perpendicular to the main surface of the substrate. Further, the semiconductor device includes a joint insulating layer in the second region and a third stack of alternating gate layers and insulating layers in the first region between the first stack of alternating gate layers and insulating layers and the second stack of alternating gate layers and insulating layers.

Abstract: A overhanging device cavity structure comprises a substrate and a cavity disposed in or on the substrate. The cavity comprises a first cavity side wall and a second cavity side wall opposing the first cavity side wall on an opposite side of the cavity from the first cavity side wall. A support extends from the first cavity side wall to the second cavity side wall and at least partially divides the cavity. A device is disposed on, for example in direct contact with, the support and extends from the support into the cavity.

Abstract: The present disclosure provides a new corrosion control chemistry for use in ruthenium (Ru) chemical-mechanical polishing (CMP) processes. More specifically, the present disclosure provides an improved CMP slurry chemistry and CMP process for planarizing a ruthenium surface. In the CMP process disclosed herein, a ruthenium surface (e.g., a post-etch ruthenium surface) is exposed to a CMP slurry containing a halogenation reagent, which reacts with the ruthenium surface to create a halogenated ruthenium surface, and a ligand for ligand-assisted reactive dissolution of the halogenated ruthenium surface. Relative amounts of the halogenation agent and the ligand can be controlled in the CMP slurry, so as to provide a diffusion-limited etch process that improves pos-etch surface morphology, while providing high material removal rates.

Abstract: A quality control system in a battery manufacturing process includes two or more capacitive measurement apparatuses to obtain a capacitance measurement from two or more intermediate products generated during the battery manufacturing process. The system also includes processing circuitry to obtain the capacitive measurement from the two or more capacitive measurement apparatuses, to determine a characteristic of the corresponding intermediate product, and to control at least one process of the battery manufacturing process that produced at least one of the two or more intermediate products based on the characteristic.

Abstract: Methods of semiconductor processing may include contacting a substrate with a first slurry and a first platen. The substrate may include silicon oxide defining one or more features, a liner extending across the silicon oxide and within the one or more features, and a copper-containing layer deposited on the liner and extending within the one or more features. The first slurry and the first platen may remove a first portion of the copper-containing layer. The methods may include contacting the substrate with a second slurry and a second platen, which may remove at least a portion of the liner. The methods may include contacting the substrate with a third slurry and a third platen, which may remove a second portion of the copper-containing layer. The methods may include contacting the substrate with a fourth slurry and a fourth platen, which may remove at least a portion of the silicon oxide.

Abstract: A carrier head for holding a substrate in a polishing system has a housing including a carrier plate, a first flexible membrane secured to the housing, and a plurality of independently operable piezoelectric actuators secured to the carrier plate. The first flexible membrane has an upper surface and having a lower surface that provides a substrate mounting surface. The piezoelectric actuators are positioned above the first flexible membrane so as to independently adjust compressive pressure on the upper surface of the first flexible membrane.

Abstract: An aqueous alkaline chemical mechanical polishing composition includes a quaternary ammonium compound having a phenyl group which enables enhanced reduction of defects on silicon oxide substrates and enables good silicon oxide removal rates during chemical mechanical polishing.

Abstract: Described herein is a cleaning composition for post-etch or post-ash residue removal from the surface of a semiconductor substrate and a corresponding use of said cleaning composition. Further described is the use of said cleaning composition in combination with one or more oxidants, e.g. for oxidative etching or partial oxidative etching of a layer or mask, comprising or consisting of TiN, preferably in the presence of a tungsten material, on the surface of a semiconductor substrate, and/or for post-etch or post-ash residue removal from the surface of a semiconductor substrate.

Abstract: A method of manufacturing a semi-damascene structure of a semiconductor device includes: forming a 1st intermetal dielectric layer; forming a 1st hardmask layer and at least one 1st photoresist pattern on the 1st intermetal dielectric layer; patterning at least one via hole penetrating through the 1st hardmask layer and the 1st intermetal dielectric using the 1st photoresist pattern; removing the 1st photoresist pattern among the 1st photoresist pattern and the 1st hardmask layer; forming a metal structure in the via hole such that the metal structure fills in the vial hole and extends on the 1st hardmask layer; patterning the metal structure to form at least one 1st trench penetrating at least the metal structure at a portion where the metal structure extends on the 1st hardmask layer; and filling the 1st trench with a 2nd inter-metal layer.

Abstract: A tunnel field effect transistor includes a constant current formation layer, a source region and a drain region provided on the constant current formation layer, a channel layer provided between the source region and the drain region, a gate electrode provided on the channel layer, and a gate insulating film provided between the gate electrode and the channel layer, wherein the source region and the drain region have different conductivity types, and the constant current formation layer forms a constant current between the drain region and the constant current formation layer.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The method includes forming a stop layer over the first layer. The method includes forming a second layer over the stop layer. The second layer is in direct contact with the stop layer. The method includes partially removing the second layer. The method includes performing an etching process to partially remove the stop layer and an upper portion of the first layer, wherein protrusion structures are formed over a lower portion of the first layer after the etching process, and the protrusion structures include the stop layer and the upper portion of the first layer remaining after the etching process. The method includes removing the protrusion structures.

Abstract: The compositions of the present disclosure polish surfaces or substrates that at least partially include ruthenium. The composition includes a synergistic combination of ammonia and oxygenated halogen compound. The composition may further include abrasive and acid(s). A polishing composition for use on ruthenium materials may include ammonia, present in an amount of 0.01 wt % to 10 wt %, based on the total weight of the composition; hydrogen periodate, present in an amount of 0.01 wt % to 10 wt %, based on the total weight of the composition; silica, present in an amount of 0.01 wt % to 12 wt %, based on the total weight of the composition; and organic sulfonic acid, present in an amount of 0.01 wt % to 10 wt %, based on the total weight of the composition, wherein the pH of the composition is between 6 and 8.

Abstract: A method for CMP includes following operations. A metal stack is received. The metal layer stack includes at least a first metal layer and a second metal layer, and a top surface of the first metal layer and a top surface of the second metal layer are exposed. A protecting layer is formed over the second metal layer. A portion of the first metal layer is etched. The protecting layer protects the second metal layer during the etching of the portion of the first metal layer. A top surface of the etched first metal layer is lower than a top surface of the protecting layer. The protecting layer is removed from the second metal layer.

Abstract: There is provided a method for manufacturing a SiC device wafer comprising the steps: a) slicing and polishing a SiC boule to thicker substrates compared to the usual thickness in the prior art, b) creating a device wafer on the substrate, c) removing the device wafer from the remaining substrate, d) adding SiC to the remaining substrate so that the original thickness of the substrate is essentially restored, and repeating steps b)-d). The removal of the device wafer can be made for instance by laser slicing. Advantages include that the SiC material loss is significantly decreased and the boule material used for device wafers is considerably increased, the substrates become more stable especially during high temperature processes, the warp and bow is reduced, the risk of breakage is decreased.

Abstract: According to one embodiment, a polishing method includes supplying a polishing agent to be between a polishing pad and to-be-polished surface, then polishing the to-be-polished surface with the polishing agent while rotating at least one of the to-be-polished surface and the polishing pad. The polishing agent includes abrasive grains and an organic polymer. The organic polymer makes a reversible phase transition between a gel state and a sol state depending on temperature.

Abstract: A semiconductor device and method of manufacture are provided. After a patterning of a middle layer, the middle layer is removed. In order to reduce or prevent damage to other underlying layers exposed by the patterning of the middle layer and intervening layers, an inhibitor is included within an etching process in order to inhibit the amount of material removed from the underlying layers.

Abstract: A technique relates to an integrated circuit (IC). The IC includes a conductive line formed on a conductive via, the conductive line being formed though a dielectric material. The IC includes an etch stop layer having one or more extended portions intervening between one or more edge portions of the conductive line and the conductive via, the one or more edge portions being at a periphery of the conductive line and the conductive via, the etch stop layer including a higher dielectric breakdown than the dielectric material. The one or more extended portions of the etch stop layer cause the conductive line to be formed with a bottom part having a reduced dimension than an upper part of the conductive line.

Abstract: An apparatus for chemical mechanical polishing includes a rotatable platen having a surface to support a polishing pad, a carrier head to hold a substrate in contact with the polishing pad, and a polishing liquid distribution system. The polishing liquid distribution system includes a dispenser positioned to deliver a polishing liquid to a portion of a polishing surface of the polishing pad, and a curved barrier positioned after the dispenser to spread fresh polishing liquid from the dispenser.

Abstract: Provided is a polishing composition for semiconductor wiring providing an excellent polishing rate and preventing occurrence of dishing. The polishing composition for semiconductor wiring according to the present invention contains a compound represented by Formula (1) below: R1O—(C3H6O2)n—H??(1) where R1 represents a hydrogen atom, a hydrocarbon group that has from 1 to 24 carbon atoms and may include a hydroxyl group, or a group represented by R2CO, where the R2 represents a hydrocarbon group having from 1 to 24 carbon atoms; and n represents an average degree of polymerization of glycerol units shown in the parentheses and is from 2 to 60.

Abstract: A method of grinding a workpiece includes a first grinding step of adjusting the relative tilt of a chuck table and a grinding wheel to a first state and bringing grindstones into abrasive contact with the workpiece to grind the workpiece, and a second grinding step of adjusting the relative tilt of the chuck table and the grinding wheel to a second state that is different from the first state and bringing the grindstones into abrasive contact with the workpiece to grind the workpiece. In the second grinding step, the workpiece is ground under a condition for causing the workpiece to have a smaller surface roughness than that in the first grinding step.

Abstract: A silicon carbide wafer manufacturing method includes: a bending measuring step of measuring a first edge having the greatest degree of a bending at one surface of a silicon carbide ingot having one surface; a cutting start step of starting a cutting at a second edge having a distance of r×a along an edge of the one surface from the first edge in a direction parallel to or with a predetermined off angle with respect to the one surface through the wire saw, a cutting speed being decreased to a first cutting speed in the cutting start step; a cutting proceeding step in which the first cutting speed is substantially constant within a variation of about ±5% of the first cutting speed; and a finish step in which the cutting speed is increased from the first cutting speed and the cutting of the silicon carbide ingot is completed.