Combined With The Removal Of Material By Nonchemical Means (e.g., Ablating, Abrading, Etc.) Patents (Class 438/690)
  • Patent number: 11422096
    Abstract: Apparatus and methods for measuring surface topography are described. The analysis apparatus and methods detect light reflected from the reflective backside of a cantilever assembly including a tip, calculate a background level (BGL) value obtained from an optical scan of a reference sample using a power spectral density (PSD) value obtained from a topographical scan of a reference sample to generate a correlational coefficient between the BGL and the PSD values. The correlational coefficient between the BGL and PSD values is used to measure the BGL value of additional EUV mask blanks by a topographical scan of the EUV mask blanks using the same tip mounted to the cantilever.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: August 23, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Weimin Li, Wen Xiao, Vibhu Jindal, Sanjay Bhat
  • Patent number: 11376703
    Abstract: A {100} indium phosphide (InP) wafer has multiplies of olive-shaped etch pits on the back side surface of the wafer, wherein the olive shape refers to a shape with its both ends being narrow and its middle being wide, e.g., an oval shape. A method of manufacturing the {100} indium phosphide wafer comprises: etching the wafer by immersing it into an etching solution to produce etch pits; washing the wafer with deionized water; protecting the back side surface of the wafer; mechanical polishing and chemical polishing the front side surface of the wafer, and then washing it with deionized water; de-protecting the back side surface of the wafer; wherein the etching solution comprises an acidic substance, deionized water and an oxidizing agent. The wafer can be heated uniformly during the epitaxial growth and thus displays good application effect.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: July 5, 2022
    Inventors: Liugang Wang, Haimiao Li, Sung-Nee George Chu
  • Patent number: 11291948
    Abstract: The embodiments provide an acidic gas absorbent having low diffusibility, an acidic gas removal method, and an acidic gas removal apparatus. The acidic gas absorbent according to the embodiment comprises: an amine compound having a vapor pressure of 0.001 to 10 Pa at 20° C.; a water-soluble polymer compound having a mass-average molecular weight of 900 to 200000 and not containing a functional group having a pKa value greater than 7 except for hydroxy; and water.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: April 5, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ENERGY SYSTEMS & SOLUTIONS CORPORATION
    Inventors: Akiko Suzuki, Yoshihiko Nakano, Reiko Yoshimura, Toshihiro Imada, Takashi Kuboki, Kenji Sano, Mitsuru Udatsu
  • Patent number: 11227970
    Abstract: A method for manufacturing LED devices is provided. The method comprises forming an epitaxial layer on a starter substrate, the epitaxial layer having a first surface that interfaces with the starter substrate and a second surface opposite to the first surface; establishing an adhesive bond between the second surface of the epitaxial layer and a carrier substrate having a pre-determined light transmittance; etching away the starter substrate; etching away part of the epitaxial layer to form a plurality of light emitting diode (LED) dies on a third surface of the epitaxial layer opposite to the second surface; establishing one or more conductive bonds between selected one or more LED dies, from the plurality of LED dies, and a backplane; weakening the adhesive bond between the second surface of the epitaxial layer and the carrier substrate; and moving the carrier substrate away from the backplane.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: January 18, 2022
    Assignee: Facebook Technologies, LLC
    Inventors: Céline Claire Oyer, Allan Pourchet
  • Patent number: 11171048
    Abstract: Adaptive endpoint detection is applied to delayering of a multi-layer sample utilizing a combination of dynamic and predetermined parameters. Tuned predetermined parameters, varying between layers of the sample, allow automated operation across multiple sites of a device. A semiconductor logic device is described, having a zone of thick metal layers and a zone of thin metal layers. The described techniques can be integrated with analysis operations and can be applied across a wide range of device types and manufacturing processes.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: November 9, 2021
    Assignee: FEI Company
    Inventors: Sean O. Morgan-Jones, Sophia E. Weeks, Peter D. Carleson
  • Patent number: 11152255
    Abstract: A method of forming a semiconductor structure includes removing a top portion of a conductive feature disposed in a first dielectric layer and over a semiconductor substrate to form a first recess, depositing a second dielectric layer over the first dielectric layer, where the second dielectric layer includes a first region disposed vertically above the first recess and a second region disposed adjacent the first region, and forming a third dielectric layer over the second dielectric layer. The method further includes subsequently forming openings in the third dielectric layer that extend to expose the second dielectric layer, depositing a conductive material in the openings, and planarizing the conductive material to form conductive features in the first and the second regions, where the planarizing completely removes portions of the third dielectric layer disposed in the second region.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: October 19, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Kang Fu, Ming-Han Lee, Shau-Lin Shue
  • Patent number: 11051403
    Abstract: A component carrier with an electrically insulating layer having a front side and a back side, a first and a second electrically conductive layer covering the front side and the back side of the electrically insulating layer, respectively. A through hole extends through both electrically conductive layers and the electrically insulating layer. An overhang is formed along one of the electrically conductive layers and sidewalls of the electrically insulating layer structure delimiting the through hole. An annular plating layer covers the sidewalls and fills part of the overhang such that a horizontal extension of the overhang after plating is less than 20 ?m and/or such that a ratio between a horizontal extension of the overhang after plating and a width of a first window through the first electrically conductive layer and/or a width of a second window through the second electrically conductive layer is smaller than 20%.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: June 29, 2021
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventor: Abderrazzaq Ifis
  • Patent number: 11018017
    Abstract: A substrate in which a low dielectric constant film is formed on a front surface thereof is processed. A densification step of densifying a surface layer portion of the low dielectric constant film to change to a densified layer is executed. Then, after a densified layer forming step, a repair liquid supplying step of supplying a repair liquid, for repairing the densified layer, to a front surface of the low dielectric constant film is executed.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: May 25, 2021
    Inventors: Ayumi Higuchi, Akihisa Iwasaki
  • Patent number: 11015098
    Abstract: The present invention provides a polishing composition for use in polishing a material having a Vickers hardness of 1500 Hv or higher. The polishing composition has an oxidation-reduction potential ORPx mV and the material to be polishing has an oxidation-reduction potential ORPy mV, with their relation satisfying ORPx?ORPy?100 mV.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: May 25, 2021
    Inventors: Shuhei Takahashi, Masatoshi Tomatsu
  • Patent number: 10727801
    Abstract: A method for fabricating a piezoelectric quartz crystal resonator is disclosed, which comprises: arranging a plurality of design units on a circuit board, wherein each design unit includes a quartz crystal resonator and a thermistor, and a division clearance is preset between every two adjacent design units; in each design unit, arranging at least one extension welding pad and at least one resonator welding pad; arranging at least one thermistor welding pad corresponding to the thermistor at the circuit board; welding the quartz crystal resonator and the thermistor onto their corresponding welding pads respectively; using thermoplastic material to seal the welded quartz crystal resonator and thermistor; dividing the circuit board processed by the thermoplastic material according to the design units.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: July 28, 2020
    Assignee: INTERQUIP ELECTRONICS (SHENZHEN) CO., LTD.
    Inventors: William Dean Beaver, Huiping Liang, Xiaoming Sun, Guangyu Wu, Junchao Xie
  • Patent number: 10438798
    Abstract: A device and method is described for producing an electrically conductive direct bond between a bonding side of a first substrate and a bonding side of a second substrate. A workspace is included that can be closed, gas-tight, against the environment and can be supplied with a vacuum. The workspace includes a) at least one plasma chamber for modifying at least one of the bonding sides and at least one bonding chamber for bonding the bonding sides, and/or b) at least one combined bonding/plasma chamber for modifying at least one of the bonding sides and for bonding the bonding sides.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: October 8, 2019
    Assignee: EV GROUP E. THALLNER GMBH
    Inventors: Markus Wimplinger, Viorel Dragoi, Christoph Flotgen
  • Patent number: 10293459
    Abstract: Polishing pads having a polishing surface with continuous protrusions are described. Methods of fabricating polishing pads having a polishing surface with continuous protrusions are also described.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: May 21, 2019
    Assignee: Cabot Microelectronics Corporation
    Inventors: Paul Andre Lefevre, William C. Allison, Alexander William Simpson, Diane Scott, Ping Huang, Leslie M. Charns, James Richard Rinehart, Robert Kerprich
  • Patent number: 10242881
    Abstract: A method of forming a semiconductor device and resulting structures having a dummy semiconductor fin removed from within an array of tight pitch semiconductor fins by forming a first spacer including a first material on a substrate; forming a second spacer including a second material on the substrate, the second spacer adjacent to the first spacer; and applying an etch process to the first spacer and the second spacer; wherein the etch process removes the first spacer at a first etch rate; wherein the etch process removes the second spacer at a second etch rate; wherein the first etch rate is different than the second etch rate.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Cheng Chi, Chi-Chun Liu, Peng Xu
  • Patent number: 10022748
    Abstract: According to one embodiment, a stencil mask includes a first opening and a second opening, the first opening is provided corresponding to a mark region in a template, the second opening is provided adjacent to the first opening, and the diameter of a circle circumscribing the second opening is smaller than the diameter of a circle circumscribing the first opening.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: July 17, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Masato Suzuki, Akiko Mimotogi, Yohko Komatsu, Ryoichi Suzuki, Kazuya Fukuhara
  • Patent number: 10014181
    Abstract: Methods of forming patterns for semiconductor devices are provided. A method may include preparing a substrate including an etch target layer on a surface of the substrate; forming a mask pattern that includes a lower masking layer having a first density and an upper masking layer having a second density that is less than the first density, on the etch target layer; forming spacers that cover sidewalls of the lower masking layer and the upper masking layer; removing the mask pattern; and etching the etch target layer by using the spacers as an etching mask.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: July 3, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-soo Lee, Hong-rae Kim, Jeon-il Lee
  • Patent number: 9956663
    Abstract: A method of a polishing a wafer includes: a first polishing step of polishing a surface of the wafer while supplying a rough polishing liquid onto a polishing surface of a rough polishing cloth; subsequent to the first polishing step, a protection film formation step of supplying a protection film formation solution containing a water-soluble polymer to the rough polishing cloth after being used in the first polishing step and bringing the protection film formation solution into contact with the polished surface of the wafer to form a protection film on the polished surface; and a second polishing step of polishing the surface of the wafer where the protection film is formed while supplying a finish polishing liquid to a polishing surface of a finish polishing cloth different from the rough polishing cloth.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: May 1, 2018
    Assignee: SUMCO CORPORATION
    Inventors: Kazuaki Kozasa, Katsuhisa Sugimori, Syunya Kobuchi
  • Patent number: 9899223
    Abstract: A device and method for producing an electrically conductive direct bond between a bonding side of a first substrate and a bonding side of a second substrate with the following features: a workspace that can be closed, gas-tight, against the environment and can be supplied with a vacuum, the workspace comprises: a) at least one plasma chamber for modifying at least one of the bonding sides and at least one bonding chamber for bonding the bonding sides, and/or b) at least one combined bonding/plasma chamber for modifying at least one of the bonding sides and for bonding the bonding sides.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: February 20, 2018
    Assignee: EV GROUP E. THALLNER GMBH
    Inventors: Markus Wimplinger, Viorel Dragoi, Christoph Flotgen
  • Patent number: 9768057
    Abstract: A method for transferring a layer from a single-crystal substrate, called a donor substrate, onto a receiver substrate, includes supplying the single-crystal donor substrate, the substrate having a notch oriented in a first direction of the crystal and a weakness region bounding the layer to be transferred, bonding of the single-crystal donor substrate onto the receiver substrate, the main surface of the donor substrate opposite to the weakness region with respect to the layer to be transferred being at the bonding interface, and detachment of the donor substrate along the weakness region. In the method, the donor substrate has, on the main surface bonded to the receiver substrate, an array of atomic steps extending essentially in a second direction of the crystal different from the first direction.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: September 19, 2017
    Assignee: Soitec
    Inventors: Ludovic Ecarnot, Nicolas Daval, Nadia Ben Mohamed, Francois Boedt, Carole David, Isabelle Guerin
  • Patent number: 9761467
    Abstract: A method and system for improved planar deprocessing of semiconductor devices using a focused ion beam system. The method comprises defining a target area to be removed, the target area including at least a portion of a mixed copper and dielectric layer of a semiconductor device; directing a precursor gas toward the target area; and directing a focused ion beam toward the target area in the presence of the precursor gas, thereby removing at least a portion of a first mixed copper and dielectric layer and producing a uniformly smooth floor in the milled target area. The precursor gas causes the focused ion beam to mill the copper at substantially the same rate as the dielectric. In a preferred embodiment, the precursor gas comprises methyl nitroacetate. In alternative embodiments, the precursor gas is methyl acetate, ethyl acetate, ethyl nitroacetate, propyl acetate, propyl nitroacetate, nitro ethyl acetate, methyl methoxyacetate, or methoxy acetylchloride.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: September 12, 2017
    Assignee: FEI Company
    Inventors: Chad Rue, Clive D. Chandler
  • Patent number: 9650544
    Abstract: A polishing composition contains silicon dioxide, a water-soluble polymer, and water. An adsorbate containing at least part of the water-soluble polymer is adsorbed on the silicon dioxide. The adsorbate is contained in a concentration of 4 ppm by mass or more in terms of carbon. A percentage of the concentration of the adsorbate in terms of carbon relative to a total carbon concentration in the polishing composition is 15% or more.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: May 16, 2017
    Assignee: FUJIMI INCORPORATED
    Inventors: Kohsuke Tsuchiya, Maki Asada
  • Patent number: 9631122
    Abstract: Described are chemical mechanical polishing compositions and methods of using the compositions for planarizing a surface of a substrate that contains tungsten, the compositions containing silica abrasive particles and cationic surfactant.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: April 25, 2017
    Assignee: Cabot Microelectronics Corporation
    Inventors: Kevin Dockery, Helin Huang, Lin Fu
  • Patent number: 9553080
    Abstract: Methods for integrating MOL TSVs in 3D SoC devices including face-to-face bonded IC chips. Embodiments include providing a device layer in each of IC chips on upper surfaces of top and bottom silicon wafers; forming, subsequent to the device layer, through-silicon vias (TSVs) extending through an upper surface of the device layer in each of the IC chips and into the bottom Si wafer; forming, subsequent to the TSVs, a dielectric layer on the upper surface of the device layer in each of the IC chips of the top and bottom Si wafers; forming a back-end-of-line metal layer in the dielectric layer of each of the IC chips of the top and bottom Si wafers; face-to-face bonding of opposing IC chips of the top and bottom Si wafers; and dicing adjacent bonded IC chips through vertically aligned dicing lanes in the top and bottom Si wafers.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: January 24, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Luke England, Ramakanth Alapati
  • Patent number: 9457429
    Abstract: A method and apparatus for laser scribing coatings on glass sheet substrates.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: October 4, 2016
    Assignee: First Solar, Inc.
    Inventors: Frank A. Borgeson, Joseph J. Hanak, Ricky S. Harju, Karen M. Harju, Norman L. Helman, Kenneth R. Hecht
  • Patent number: 9349582
    Abstract: A liquid chemical for forming a water repellent protecting film on a wafer having at its surface an uneven pattern and containing at least one kind of element selected from the group consisting of titanium, tungsten, aluminum, copper, tin, tantalum and ruthenium at surfaces of recessed portions of the uneven pattern, the water repellent protecting film being formed at least on the surfaces of the recessed portions. The liquid chemical is characterized by including: a water repellent protecting film forming agent; and water, and characterized in that the water repellent protecting film forming agent is at least one selected from compounds represented by the following general formula [1] and salt compounds thereof and that the concentration of the water relative to the total quantity of a solvent contained in the liquid chemical is not smaller than 50 mass %.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: May 24, 2016
    Assignee: Central Glass Company, Limited
    Inventors: Soichi Kumon, Takashi Saio, Masanori Saito, Shinobu Arata
  • Patent number: 9330685
    Abstract: Recording media press systems and methods of operating such press systems. Embodiments of a press system include a first and second die at least one of which is configured to be coupled to an embossing foil. A stopper may be used to space the embossing foil apart from a magnetic recording disk disposed within the press system by a predetermined gap when the die set is in a closed position. In an embodiment, a piston disposed within at least one of the first and second die is moved relative to the first and second die to press the embossing foil against the magnetic recording disk after the die set stopped in the closed position by the stopper.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: May 3, 2016
    Assignee: WD Media, LLC
    Inventors: David Treves, Paul C. Dorsey
  • Patent number: 9312328
    Abstract: A method is provided for fabricating small pitch patterns. The method includes providing a semiconductor substrate, and forming a target material layer having a first region and a second region on the semiconductor substrate. The method also includes forming a plurality of discrete first sacrificial layers on the first region of the target material layer and a plurality of discrete second sacrificial layers on the second region of the target material layer, and forming first sidewall spacers on both sides of the discrete first sacrificial layers and the discrete second sacrificial layers. Further, the method includes removing the first sacrificial layers and the second sacrificial layers, and forming second sidewall spacers. Further, the method also includes forming discrete repeating patterns in the first region of the target material layer and a continuous pattern in the second region of the target material layer.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 12, 2016
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP.
    Inventor: Qiyang He
  • Patent number: 9163314
    Abstract: The present invention relates to a CMP slurry composition for polishing tungsten comprising a abrasive and a polishing chemical, wherein the abrasive comprises colloidal silica dispersed in ultra-pure water, and the polishing chemical comprises hydrogen peroxide, ammonium persulfate and iron nitrate. The slurry composition is not discolored and has good etching selectivity, so as to be applied to a CMP process.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: October 20, 2015
    Assignee: INDUSTRIAL BANK OF KOREA
    Inventors: Jea-Gun Park, Jin-Hyung Park, Jae-Hyung Lim, Jong-Young Cho, Ho Choi, Hee-Sub Hwang
  • Patent number: 9039925
    Abstract: Provided is a polishing slurry composition, including a non-ionic surfactant represented by the following formula (1) R—(OCH2CH2)x—OH??formula (1) wherein x is an integer from 1 to 50, and R is selected from a group consisting of a C3-C50 alkyl group, a C6-C55 benzylalkyl group and a C6-C55 phenylalkyl group.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: May 26, 2015
    Assignee: UWIZ Technology Co., Ltd.
    Inventors: Wei-Jung Chen, Wen-Tsai Tsai, Ho-Ying Wu, Song-Yuan Chang, Ming-Hui Lu
  • Publication number: 20150140817
    Abstract: A method for removing material from surfaces of at least a portion of at least one recess or at least one aperture extending into a surface of a substrate includes pressurizing fluid so as to cause the fluid to flow into the at least one recess or the at least one aperture. The fluid may be pressurized by generating a pressure differential across the substrate, which causes the fluid to flow into or through the at least one aperture or recess. Apparatus for pressurizing fluid so as to cause it to flow into or through recesses or apertures in a substrate are also disclosed.
    Type: Application
    Filed: January 28, 2015
    Publication date: May 21, 2015
    Inventor: Ross S. Dando
  • Patent number: 9029261
    Abstract: There is provided a method of fabricating a semiconductor device, the method including: forming a semiconductor component portion at a first surface of a substrate; applying a grinding treatment to a second surface of the substrate that is opposite from the first surface to form a fracture surface; applying a fracture surface removal treatment to predetermined positions of the fracture surface of the second surface; and forming an electrode at the second surface.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: May 12, 2015
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventor: Yuichi Kaneko
  • Patent number: 9023734
    Abstract: A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents combine with a nitrogen-and-hydrogen-containing precursor. Reactants thereby produced etch the patterned heterogeneous structures with high silicon oxide selectivity while the substrate is at high temperature compared to typical Siconi™ processes. The etch proceeds without producing residue on the substrate surface. The methods may be used to remove silicon oxide while removing little or no silicon, polysilicon, silicon nitride or titanium nitride.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 5, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Zhijun Chen, Jingchun Zhang, Ching-Mei Hsu, Seung Park, Anchuan Wang, Nitin K. Ingle
  • Patent number: 9005472
    Abstract: An aqueous polishing agent, comprising, as the abrasive, at least one kind of polymer particles (A) finely dispersed in the aqueous phase and having at their surface a plurality of at least one kind of functional groups (a1) capable of interacting with the metals and/or the metal oxides on top of the surfaces to be polished and forming complexes with the said metals and metal cations, the said polymer particles (A) being preparable by the emulsion or suspension polymerization of at least one monomer containing at least one radically polymerizable double bond in the presence of at least one oligomer or polymer containing a plurality of functional groups (a1); graft copolymers preparable by the emulsion or suspension polymerization of at least one monomer containing at least one radically polymerizable double bond in the presence of at least one oligomeric or polymeric aminotriazine-polyamine condensate; and a process for the chemical and mechanical polishing of patterned and unstructured metal surfaces making
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: April 14, 2015
    Assignee: BASF SE
    Inventors: Vijay Immanuel Raman, Ilshat Gubaydullin, Mario Brands, Yuzhuo Li, Maxim Peretolchin
  • Publication number: 20150099360
    Abstract: Embodiments described herein generally relate to methods for forming gate structures. Various processes may be performed on a gate dielectric material to reduce the K value of the dielectric material. The gate dielectric having a reduced K value may provide for reduced parasitic capacitance and an overall reduced capacitance. The gate dielectric may be modified without thermodynamic constraint.
    Type: Application
    Filed: October 2, 2014
    Publication date: April 9, 2015
    Inventors: Ellie Y. YIEH, Ludovic GODET, Srinivas D. NEMANI
  • Patent number: 8999839
    Abstract: A method of manufacturing a semiconductor structure, the method includes removing a portion of a dielectric filler from a first metal-containing layer formed over a semiconductor substrate to define an air-gap region according to a predetermined air-gap pattern. The method further includes filling the air-gap region with a decomposable filler and forming a dielectric capping layer over the first metal-containing layer. The method further includes decomposing the decomposable filler.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Hui Su, Cheng-Lin Huang, Jiing-Feng Yang, Zhen-Cheng Wu, Ren-Guei Wu, Dian-Hau Chen, Yuh-Jier Mii
  • Patent number: 8993444
    Abstract: Embodiments of the present invention generally relate to methods for lowering the dielectric constant of low-k dielectric films used in semiconductor fabrication. In one embodiment, a method for lowering the dielectric constant (k) of a low-k silicon-containing dielectric film, comprising exposing a porous low-k silicon-containing dielectric film to a hydrofluoric acid solution and subsequently exposing the low-k silicon-containing dielectric film to a silylation agent. The silylation agent reacts with Si—OH functional groups in the porous low-k dielectric film to increase the concentration of carbon in the low-k dielectric film.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: March 31, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Kelvin Chan, Jin Xu, Kang Sub Yim, Alexandros T. Demos
  • Patent number: 8993443
    Abstract: Selective removal of specified layers of thin film structures and devices, such as solar cells, electrochromics, and thin film batteries, by laser direct patterning is achieved by including heat and light blocking layers in the device/structure stack immediately adjacent to the specified layers which are to be removed by laser ablation. The light blocking layer is a layer of metal that absorbs or reflects a portion of the laser energy penetrating through the dielectric/semiconductor layers and the heat blocking layer is a conductive layer with thermal diffusivity low enough to reduce heat flow into underlying metal layer(s), such that the temperature of the underlying metal layer(s) does not reach the melting temperature, Tm, or in some embodiments does not reach (Tm)/3, of the underlying metal layer(s) during laser direct patterning.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: March 31, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Daoying Song, Chong Jiang, Byung-Sung Leo Kwak, Joseph G. Gordon, II
  • Patent number: 8987122
    Abstract: A method of manufacturing a semiconductor device, includes a wafer grinding step of, by means of a revolving grinding stone, forming a thinned portion in a wafer while at the same time forming a slope surrounding said thinned portion, wherein during said formation of said slope, said grinding stone is positioned so that there is always a space between said slope and the facing side of said grinding stone, wherein said thinned portion is thinner than a peripheral portion of said wafer, and wherein said slope extends along and defines an inner circumferential side of said peripheral portion and forms an angle of 75° or more but less than 90° with respect to a main surface of said wafer. The method of manufacturing a semiconductor device further includes a step of forming a semiconductor device in said thinned portion.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: March 24, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazunari Nakata, Tamio Matsumura
  • Patent number: 8980763
    Abstract: Methods of selectively etching tungsten relative to silicon-containing films (e.g. silicon oxide, silicon carbon nitride and (poly)silicon) as well as tungsten oxide are described. The methods include a remote plasma etch formed from a fluorine-containing precursor and/or hydrogen (H2). Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the tungsten. The plasma effluents react with exposed surfaces and selectively remove tungsten while very slowly removing other exposed materials. Sequential and simultaneous methods are included to remove thin tungsten oxide which may, for example, result from exposure to the atmosphere.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 17, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Xikun Wang, Ching-Mei Hsu, Nitin K. Ingle, Zihui Li, Anchuan Wang
  • Patent number: 8980750
    Abstract: A chemical mechanical polishing (CMP) composition (Q) comprising (A) Inorganic particles, organic particles, or a mixture or composite thereof, wherein the particles are cocoon-shaped (B) a non-ionic surfactant, (C) a carbonate or hydrogen carbonate salt, (D) an alcohol, and (M) an aqueous medium.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: March 17, 2015
    Assignee: BASF SE
    Inventors: Robert Reichardt, Yuzhuo Li, Michael Lauter, Wei Lan William Chiu
  • Patent number: 8980113
    Abstract: A method for chemical mechanical polishing of a substrate includes polishing the substrate at a stock removal rate of greater than about 2.5 ?/min to achieve a Ra of not greater than about 5.0 ?. The substrate can be a III-V substrate or a SiC substrate. The polishing utilizes a chemical mechanical polishing slurry comprising ultra-dispersed diamonds and at least 80 wt % water.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: March 17, 2015
    Assignee: Saint-Gobain Ceramics & Plastics, Inc.
    Inventors: Jun Wang, Ronald W. Laconto, Andrew G. Haerle
  • Patent number: 8974680
    Abstract: A pattern forming method includes forming a coating film containing a hydrophilic first homopolymer having a first bonding group and a hydrophobic second homopolymer having a second bonding group capable of bonding with the first bonding group, forming a bond between the first and second bonding group to produce a block copolymer of the first and second homopolymers, and heating the coating film to microphase-separating the copolymer into a hydrophilic domain and a hydrophobic domain. The hydrophilic and hydrophobic domains are arranged alternately. The bond is broken, then selectively dissolving-removing either domain by a solvent to provide a polymer pattern of a remainder domain.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: March 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroki Tanaka, Ryosuke Yamamoto, Naoko Kihara
  • Patent number: 8974692
    Abstract: Provided are novel chemical mechanical polishing (CMP) slurry compositions for polishing copper substrates and method of using the CMP compositions. The CMP slurry compositions deliver superior planarization with high and tunable removal rates and low defects when polishing bulk copper layers of the nanostructures of IC chips. The CMP slurry compositions also offer the high selectivity for polishing copper relative to the other materials (such as Ti, TiN, Ta, TaN, and Si), suitable for through-silicon via (TSV) CMP process which demands high copper film removal rates.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: March 10, 2015
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Xiaobo Shi, Krishna Murella, James Allen Schlueter, Jae Ouk Choo
  • Patent number: 8969216
    Abstract: A method for single side texturing of a crystalline semiconductor substrate (10) comprises: providing a substrate (10), for example a semiconductor substrate, comprising a first surface (12) and a second surface (14) opposite to one another with respect to the substrate (10); providing a masking layer (21) with a random pattern on the first surface (12) of the substrate (10); and etching the substrate (10) in a polishing solution, thereby texturing the first surface (12) of the substrate (10) and polishing the second surface (14) in a single wet etching step.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: March 3, 2015
    Assignees: IMEC, Katholieke Universiteit Leuven, K.U. Leuven R&D
    Inventors: Victor Prajapati, Joachim John
  • Patent number: 8969204
    Abstract: The present invention relates to a CMP slurry that is able to reduce dishing generation, when it is applied to polishing or planarization of silicon oxide layer, for example, and a polishing method. The CMP slurry includes a polishing abrasive, a linear anionic polymer, a compound including a phosphoric acid group, and water, and the ratio of CMP polishing speed to a silicon oxide layer: CMP polishing speed to a silicon nitride layer is 30:1 to 50:1.
    Type: Grant
    Filed: March 3, 2009
    Date of Patent: March 3, 2015
    Assignee: LG Chem, Ltd.
    Inventors: Jong-Pil Kim, Seung-Beom Cho, Jun-Seok Noh, Jang-Yul Kim
  • Patent number: 8968583
    Abstract: A method for cleaning a dielectric and metal structure within a microelectronic structure uses an oxygen containing plasma treatment, followed by an alcohol treatment, in turn followed by an aqueous organic acid treatment. Another method for cleaning a dielectric and metal structure within a microelectronic structure uses an aqueous surfactant treatment followed by an alcohol treatment and finally followed by an aqueous organic acid treatment. The former method may be used to clean a plasma etch residue from a dual damascene aperture. The second method may be used to clean a chemical mechanical polish planarizing residue from a dual damascene structure. The two methods may be used sequentially, absent any intervening or subsequent sputtering method, to provide a dual damascene structure within a microelectronic structure.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mary Beth Rothwell, Roy Rongqing Yu
  • Patent number: 8961807
    Abstract: Disclosed are a polishing composition and method of polishing a substrate. The composition has low-load (e.g., up to about 0.1 wt. %) of abrasive particles. The polishing composition also contains water and at least one anionic surfactant. In some embodiments, the abrasive particles are alpha alumina particles (e.g., coated with organic polymer). The polishing composition can be used, e.g., to polish a substrate of weak strength such as an organic polymer. An agent for oxidizing at least one of silicon and organic polymer is included in the composition in some embodiments.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 24, 2015
    Assignee: Cabot Microelectronics Corporation
    Inventors: Lin Fu, Steven Grumbine
  • Patent number: 8945403
    Abstract: Material test structures having cantilever portions and methods of forming the same are described herein. As an example, a method of forming a material test structure includes forming a number of electrode portions in a first dielectric material, forming a second dielectric material on the first dielectric material, wherein the second dielectric material includes a first cantilever portion and a second cantilever portion, and forming a test material on the number of electrode portions, the first dielectric material, and the second dielectric material.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Fabio Pellizzer, Innocenzo Tortorelli, Christina Papagianni, Gianpaolo Spadini, Jong Won Lee
  • Patent number: 8942842
    Abstract: A method of generating a library of reference spectra includes storing an optical model for a layer stack having at a plurality of layers, receiving user input identifying a set of one or more refractive index functions and a set of one or more extinction coefficient functions a first layer from the plurality of layers, wherein the set of one or more refractive index functions includes a plurality of different refractive index functions or the set of one or more extinction coefficient functions includes a plurality of different extinction coefficient functions, and for each combination of a refractive index function from the set of refractive index functions and an extinction coefficient function from the set of extinction coefficient functions, calculating a reference spectrum using the optical model based on the refractive index function, the extinction coefficient function and a first thickness of the first layer.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: January 27, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Jeffrey Drue David, Dominic J. Benvegnu, Xiaoyuan Hu
  • Patent number: 8932958
    Abstract: A method of manufacturing is disclosed. An exemplary method includes providing a substrate and forming one or more layers over the substrate. The method further includes forming a surface layer over the one or more layers. The method further includes performing a patterning process on the surface layer thereby forming a pattern on the surface layer. The method further includes performing a cleaning process using a cleaning solution to clean a top surface of the substrate. The cleaning solution includes tetra methyl ammonium hydroxide (TMAH), hydrogen peroxide (H2O2) and water (H2O).
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: January 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Lun Lu, Kuan-Wen Lin, Ching-Wei Shen, Ting-Hao Hsu, Sheng-Chi Chin
  • Patent number: 8932952
    Abstract: Disclosed is a method for polishing a silicon wafer, wherein a surface to be polished of a silicon wafer is rough polished, while supplying a polishing liquid, which is obtained by adding a water-soluble polymer to an aqueous alkaline solution that contains no free abrasive grains, to a polishing cloth. Consequently, the surface to be polished can be polished at high polishing rate and the flatness of the edge portion including roll-off and roll-up can be controlled.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: January 13, 2015
    Assignee: Sumco Corporation
    Inventors: Shinichi Ogata, Ryuichi Tanimoto, Ichiro Yamasaki, Shunsuke Mikuriya