Abstract: A method of manufacturing an electronic device (10) provides a substrate (20) that has a plastic material. A particulate material (16) is embedded in at least one surface of the substrate. A layer of thin-film semiconductor material is deposited onto the substrate (20).

Abstract: An objective of the present invention is to provide a polishing pad for a semiconductor wafer and a laminated body for polishing of a semiconductor wafer equipped with the same which can perform optical endpoints detection without lowering the polishing performance as well as methods for polishing of a semiconductor wafer using them. The polishing pad of the present invention comprises a substrate 11 for a polishing pad provided with a through hole penetrating from surface to back, a light transmitting part 12 fitted in the through hole, the light transmitting part comprises a water-insoluble matrix material (1,2-polybutadiene) and a water-soluble particle (?-cyclodextrin) dispersed in the water-insoluble matrix material, and the water-soluble particle is less than 5% by volume based on 100% by volume of the total amount of the water-insoluble matrix material and the water-soluble particle.

Abstract: According to one aspect of the invention, an improved process for preparing a surface of substrate is provided wherein the surface of the substrate is prepared for a chemical mechanical polishing (CMP) process, the CMP process is performed on the surface of the substrate, and the surface of the substrate is finished to clear the substrate surface of any active ingredients from the CMP process. Also, an improved substrate produced by the method is provided. According to one aspect of the invention, particular polishing materials and procedures may be used that allow for increased quality of AlN substrate surfaces.

Abstract: An apparatus and a method for stripping silicon nitride are disclosed that facilitate automatic, real-time, and exact measurement of etch rate and an ending time of the etching process when silicon nitride is stripped with phosphoric acid solution. The method for stripping silicon nitride includes the steps of: a) measuring initial concentration of a specific ion in a phosphoric acid solution contained in a reactor, b) dipping a silicon nitride-formed substrate into the phosphoric acid solution in the reactor, c) measuring instantaneous concentration of the specific ion in stripping solution extracted from the reactor when silicon nitride stripping is processed in the reactor, and d) finishing the silicon nitride stripping process if variation rate of the measured instantaneous concentration is not exceeding a predetermined standard, or returning to the step c) if the variation rate is more than the predetermined standard.

Abstract: Embodiments relate to a method of forming a polysilicon pattern, which may be able to form a minute pattern. In embodiments, the method may in clued forming a first polysilicon pattern by selectively etching a polysilicon layer using a photoresist pattern at a fixed interval, forming an oxide layer having a concavo-convex pattern in the first polysilicon pattern, so as to form a second polysilicon pattern covered with the oxide layer, grinding the oxide layer in such an extent that exposes the upper surface of the second polysilicon pattern, etching the second polysilicon pattern exposed in state of using the oxide layer as a mask, forming an oxide-layer pattern used for a mask of a final polysilicon pattern being completed, by etching the oxide layer to a predetermined depth, and forming the final polysilicon pattern by selectively etching the polysilicon layer in state the oxide-layer pattern is used as a mask.

Abstract: This invention provides a polishing medium for chemical-mechanical polishing, comprising an oxidizing agent for a conductor, a protective-film-forming agent for protecting a metal surface, an acid, and. water; (1) the polishing medium having a pH of 3 or less, and the oxidizing agent being in a concentration of from 0.01 to 3% by weight, or (2) the polishing medium containing abrasive grains having an average particle diameter of 50 nm or less, and the abrasive grains having standard deviation of particle size distribution in a value of more than 5 nm.

Abstract: A cleaning method for a semiconductor substrate including placing the semiconductor substrate into a cleaning chamber and injecting ozone gas (O3) into the cleaning chamber. This process operates to cleanse the semiconductor substrate without corrosion or etching of the semiconductor substrate; even when the substrate has metal layer made of tungsten.

Abstract: The present invention relates generally to compositions and associated methods for chemical-mechanical polishing of substrate surfaces having at least one feature thereon comprising tungsten and at least one feature thereon comprising a dielectric material. The compositions and associated methods of the invention result in similar removal rates of both the tungsten and the dielectric material. Compositions used in the methods of the present invention typically have a pH from about 1.5 to about 3.5 and comprise periodic acid and colloidal silica.

Abstract: A method of polishing a semiconductor layer formed on a transparent substrate is described, the method including measuring the thickness of the semiconductor from the substrate side of the semiconductor layer simultaneously with the polishing, and using the thickness measurement to modify the polishing.

Abstract: A method of forming a semiconductor device, and the device so formed. Depositing a low dielectric constant material on a substrate. Depositing a hard mask on the low dielectric constant material. Forming an at least one first feature within the low dielectric constant material and the hard mask. Depositing a conformal liner over the hard mask and within the at least one feature, wherein the liner occupies more than at least 2% of a volume of the at least one feature, and wherein a thickness of the liner is at least approximately ? a minimum width of the at least one feature. Metallizing the at least one feature.

Abstract: A layer of required material, such as polysilicon, is planarized by first forming a sacrificial layer of material, such as an oxide, on the layer of required material. The combined layers of required and sacrificial materials are then planarized using chemical-mechanical polishing until the sacrificial material has been substantially, completely removed.

Abstract: A method of enhancing gate lithography performance by polysilicon chemical-mechanical polishing includes depositing a gate polysilicon layer on a semiconductor substrate which has a field oxide isolation structure, and then performing a polysilicon chemical-mechanical polishing after a gate polysilicon layer is deposited in order to smooth the uneven polysilicon surface resulting from the field oxide isolation structure so as to lessen the next lithography process fault because of the non-flatness.

Abstract: A method for chemical mechanical polishing of semiconductor substrates containing a metal layer requiring removal and metal interconnects utilizing a composition containing engineered copolymer molecules comprising hydrophilic functional groups and relatively less hydrophilic functional groups; the engineered copolymer molecules enabling contact-mediated reactions between the polishing pad surface and the substrate surface during CMP resulting in minimal dishing of the metal interconnects in the substrate.

Abstract: A method for forming a semiconductor device utilizing a chemical-mechanical polishing (CMP) process is provided. In one example, the method includes sequentially performing a first CMP process for removing a first portion of an oxide surface of a semiconductor device using a high selectivity slurry (HSS) and a first polish pad, interrupting the first CMP process, cleaning the semiconductor device and the first polish pad, and performing a second CMP process for removing a second portion of the oxide surface.

Abstract: A shallow trench isolation (STI) multistage chemical mechanical polishing (CMP) method for forming a shallow trench isolation structure is provided. The substrate comprising a dense region and an isolation region, a silicon nitride layer formed over the substrate, a plurality of trenches formed in the silicon nitride layer and the substrate, an oxide layer formed over the substrate, filling the trenches, wherein a width of the trenches in the dense region is smaller than that in the isolation region. A first polishing step is performed to remove a portion of the silicon oxide layer until a thickness of the remaining portion of the oxide layer reaches a predetermined thickness. A second polishing step is performed to remove a portion of the remaining portion of the silicon oxide layer until the silicon nitride layer is exposed.

Abstract: A polishing-rate distribution of a target film is compared with a desired post-polishing film-thickness distribution of the target film, thereby obtaining a pre-polishing film-thickness distribution of the target film by a reverse calculation, so that film growing conditions can be controlled in advance so as to allow the target film to have, after polishing, a film-thickness distribution that is the same as the desired film-thickness distribution. Therefore, even if there is a possibility that variation in the step height of the wafer surface might be produced by polishing, the finally obtained target film's film-thickness distribution can be the desired film-thickness distribution. Accordingly, semiconductors in which device-to-device variation in characteristic is reduced can be provided.

Abstract: The present invention relates to a chip package that includes a semiconductor device and at least one micro electromechanical structure (MEMS) such that the semiconductor device and the MEMS form an integrated package. One embodiment of the present invention includes a semiconductor device, a first MEMS device disposed in a conveyance such as a film, and a second MEMS device disposed upon the semiconductor device through a via in the conveyance. The present invention also relates to a process of forming a chip package that includes providing a conveyance such as a tape automated bonding (TAB) structure, that may hold at least one MEMS device. The method is further carried out by disposing the conveyance over the active surface of the device in a manner that causes the at least one MEMS to communicate electrically to the active surface. Where appropriate, a sealing structure such as a solder ring may be used to protect the MEMS.

Abstract: A Chemical Mechanical Polish (CMP) process and slurry therefore slurry that is capable of removing NiFe, SiO2, Photoresist, Ta, alumina and Cu at substantially the same rate. The slurry is useful for obtaining a substantially planar surface of several materials while avoiding corrosion of Cu coil and NiFe structure.

Abstract: A high-purity alkali etching solution for silicon wafers results in silicon wafers with extremely low metal impurity contamination, and excellent surface flatness. The alkali etching solution contains sodium hydroxide containing 1 ppb or less of the elements Cu, Ni, Mg, and Cr, 5 ppb or less of the elements Pb and Fe, 10 ppb or less of the elements Al, Ca, and Zn, and 1 ppm or less of chloride, sulfate, phosphate, and nitrogen compounds other than nitrate and nitrite, and containing 0.01 to 10 wt % of nitrate and/or nitrite.

Abstract: Embodiments of the invention include a method for electro chemical mechanical polishing of a substrate. The process includes flowing an electro chemical mechanical polishing (ECMP) slurry having a high viscosity with a polishing agent over a portion of the substrate. Electrical current is passed through the slurry and substrate. The electrical current, in conjunction with the abrading action of the slurry as it flows over the surface of the substrate, serves to remove at least a portion of the metal layer from the substrate. The invention also includes various slurry embodiments.

Abstract: A method for reducing the topography from CMP of metal layers during the semiconductor manufacturing process is described. Small amounts of solute are introduced into the conductive metal layer before polishing, resulting in a material with electrical conductivity and electromigration properties that are very similar or superior to that of the pure metal, while having hardness that is more closely matched to that of the surrounding oxide dielectric layers. This may allow for better control of the CMP process, with less dishing and oxide erosion a result. A secondary benefit of this invention may be the elimination of superficial damage and embedded particles in the conductive layers caused by the abrasive particles in the slurries.

Abstract: A processing method for a wafer includes: preparing a wafer which has a device region having plural devices formed on a surface of the wafer; and a peripheral reinforcing portion which is integrally formed around the device region and has a projection projecting outwardly on a rear surface of the wafer. The processing method further includes: removing at least the projection of the peripheral reinforcing portion of the wafer; and transferring the wafer after the removing. In the removing, while the wafer is held on a holding table such that the rear surface of the wafer is exposed and the surface of the wafer closely contacts the holding table, at least the projection of the peripheral reinforcing portion is removed. After the removing of at least the projection, while the wafer is held on the holding table, a holding tape is applied to the rear surface of the wafer and the holding tape is supported by a frame.

Abstract: In a method for processing a semiconductor wafer, having a plurality of solder bumps bonded on a front surface thereof, a fluid-like layer is formed on the front surface of the semiconductor wafer. A holder sheet is prepared, and has a support layer, and an adhesive layer formed on a surface of the support layer and exhibiting a fluidness. The fluid-like layer is covered with the holder sheet such that the adhesive layer of the holder sheet is rested on a surface of the fluid-like layer, and the adhesive layer of the holder sheet is transformable so as to conform with a configuration of the surface of the fluid-like layer due to the fluidness of the adhesive layer of the holder sheet. A rear surface of the semiconductor wafer is mechanically ground so that the thickness of the semiconductor wafer is reduced to a target value. The holder sheet is peeled from the surface of the fluid-like layer.

Abstract: Planarizing solutions, planarizing machines and methods for planarizing microelectronic-device substrate assemblies using mechanical and/or chemical-mechanical planarizing processes. In one aspect of the invention, a microelectronic-device substrate assembly is planarized by abrading material from the substrate assembly using a plurality of first abrasive particles and removing material from the substrate assembly using a plurality second abrasive particles. The first abrasive particles have a first planarizing attribute, and the second abrasive particles have a second planarizing attribute. The first and second planarizing attributes are different from one another to preferably selectively remove topographical features from substrate assembly and/or selectively remove different types of material at the substrate surface.

Abstract: A method for forming a pattern is provided that includes: providing a cliché having a plurality of convex patterns; applying an adhesive force reinforcing agent onto each surface of the convex patterns; forming an etching object layer on a substrate and then applying ink onto an upper portion of the etching object layer; attaching the cliché and the substrate to each other such that the convex patterns onto which the adhesive force reinforcing agent is applied can come in contact with the ink applied onto the etching object layer; and forming ink patterns which selectively remain on the etching object layer by separating the substrate and the cliché from each other.

Abstract: A slurry composition includes about 4.25 to about 18.5 weight percent of an abrasive, about 80 to about 95 weight percent of deionized water, and about 0.05 to about 1.5 weight percent of an additive. The slurry composition may further include a surfactant. In a polishing method using the slurry composition, a polysilicon layer may be rapidly polished, and also dishing and erosion of the polysilicon layer may be suppressed.

Abstract: The substrate polishing method of the present invention can be used, in a substrate polishing apparatus having multiple carriers for one polishing pad, for determining a polishing time necessary to obtain a specific amount of polishing in polishing substrates using only some of the carriers among multiple carriers. In the present method, a correction coefficient indicating the correlation between the polishing time in polishing substrates using all the carriers and the polishing time in polishing substrates using only a part of the carriers is obtained in advance. The polishing time necessary for the specific amount of polishing in polishing substrates using only a part of the carriers is calculated based on the correction coefficient and the polishing time necessary for polishing the specific amount of polishing in polishing substrates using all of the carriers.

Abstract: In a hydrophilicity treatment method including the step of rotating, on a polishing cloth, a mirror surface of a silicon wafer subjected to mirror-polishing followed by rinsing treatment while the mirror surface is pushed onto the cloth under the application of a small load with the contact of the mirror surface with a hydrophilicity treatment liquid, thereby making the mirror surface hydrophilic, the hydrophilicity treatment liquid is an aqueous liquid which comprises an organic compound having at least one hydrophilic group and having a molecular weight of 100 or more, a basic nitrogen-containing organic compound and a surfactant, and which has a pH of 9.5 to 10.5.

Abstract: Disclosed herein is a chemical mechanical polishing (CMP) method for manufacturing a semiconductor device, comprising performing partial ion implantation of dopants at different concentrations into a plurality of at least two divided regions of a wafer having a planarization-target film, and subjecting the partially ion implanted-wafer to a chemical mechanical polishing process. In accordance with the present invention, non-uniformity of the removal rate in a chemical mechanical polishing process is countervailed by dopants which are implanted at different concentrations via partial ion implantation, and thereby it is possible to polish the target film at a uniform removal rate.

Abstract: Provided is a method of manufacturing a semiconductor device in which, when a polyimide resin film is formed as a protective film on a front surface of a semiconductor chip, the polyimide resin film disposed on scribe lines is removed and the polyimide resin film disposed on a circumferential portion of the semiconductor wafer is also removed. Thus, when a rear surface of the semiconductor wafer is ground, the outer circumferential portion of the semiconductor wafer and the surface protective tape can be completely bonded to each other, thereby making it possible to fill a gap between the surface protective tape and each scribe line formed on the front surface of the semiconductor wafer, prevent grinding wafer from penetrating into the gap when the rear surface of the semiconductor wafer is ground, and prevent the scribe lines and the front surface of the semiconductor chip from being contaminated with grinding swarf.

Abstract: The polishing solution is useful for preferentially removing barrier materials in the presence of nonferrous interconnect metals with limited erosion of dielectrics. The polishing solution comprises 0 to 20 weight percent oxidizer, at least 0.001 weight percent inhibitor for reducing removal rate of the nonferrous interconnect metals, 10 ppb to 4 weight percent complexing agent, 0 to 50 weight percent abrasive and balance water; and the solution having a pH of less than 7.

Abstract: The invention provides a process for forming a planar copper structure on a wafer surface in a first module and a second module of a system. During the process, a copper layer is formed on the wafer surface by utilizing an electrochemical deposition process in the first module. After the deposition, the wafer is moved to the second module of the system and an electrochemical mechanical polishing process is applied to planarize the copper layer to a predetermined thickness. The first and second modules can be positioned in a cluster tool. The wafer is subsequently processed by selective copper CMP and selective barrier layer CMP, which are conducted in another cluster tool.

Abstract: The invention relates to chemical mechanical polishing of substrates using an abrasive and a fluid composition, wherein certain organosulfonic acid compounds are used as oxidizers, and particularly relates to a method of polishing substrates comprising copper, tungsten, titanium, and/or polysilicon using a chemical-mechanical polishing system comprising organosulfonic acids having an electrochemical oxidation potential greater than 0.2V as an oxidizer.

Abstract: A planarization method includes providing a second and/or third row Group VIII metal-containing surface (preferably, a platinum-containing surface) and positioning it for contact with a polishing surface in the presence of a planarization composition that includes a complexing agent.

Abstract: Methods for fabricating a copper interconnect of a semiconductor device are disclosed. An example method for fabricating a copper interconnect of a semiconductor device deposits a first insulating layer on a substrate having at least one predetermined structure, forms a trench and via hole through the first insulating layer by using a dual damascene process, and deposits a barrier layer along the bottom and the sidewalls of the trench and via hole.

Abstract: Chemical-mechanical planarization (CMP) apparatus and methods for detecting polishing pad properties using ultrasonic imaging is presented. An ultrasonic probe assembly transmits ultrasonic signals onto the surface of a polishing pad during a CMP process. Reflected ultrasonic signals are collected and analyzed to monitor polishing pad properties in real-time. This allows CMP process adjustments to be made during the CMP process.

Abstract: The present invention provides inspection methods and structures for facilitating the visualization and/or detection of specific chip structures. Optical or fluorescent labeling techniques are used to “stain” a specific chip structure for easier detection of the structure. Also, a temporary/sacrificial illuminating (e.g., fluorescent) film is added to the semiconductor process to facilitate the detection of a specific chip structure. Further, a specific chip structure is doped with a fluorescent material during the semiconductor process. A method of the present invention comprises: providing a first and a second material; processing the first material to form a portion of a semiconductor structure; and detecting a condition of the second material to determine whether processing of the first material is complete.

Abstract: In an independent GaN film manufactured by creating a GaN layer on a base heterosubstrate using vapor-phase deposition and then removing the base substrate, owing to layer-base discrepancy in thermal expansion coefficient and lattice constant, warp will be a large ±40 ?m to ±100 ?m. Since with that warp device fabrication by photolithography is challenging, reducing the warp to +30 ?m to ?20 ?m is the goal. The surface deflected concavely is ground to impart to it a damaged layer that has a stretching effect, making the surface become convex. The damaged layer on the surface having become convex is removed by etching, which curtails the warp. Alternatively, the convex surface on the side opposite the surface having become convex is ground to generate a damaged layer. With the concave surface having become convex due to the damaged layer, suitably etching off the damaged layer curtails the warp.

Abstract: Provided is an improved method for producing a silicon wafer whose surfaces exhibit precise flatness and minute surface roughness, and which allows one to visually discriminate between the front and rear surfaces, the method comprising a slicing step of slicing a single-crystal ingot into thin disc-like wafers, a chamfering step of chamfering the wafer, a lapping step for flattening the wafer, an etching step for removing processing distortions on the wafer surfaces, a mirror-polishing step for mirror-polishing the surface of the wafer, and a cleaning step for cleaning the wafer. The etching step further comprises a first acid-etching phase and a second alkali-etching phase, and a rear surface mild polishing step is introduced between the first and second etching phases in order to abrade part of roughness formed on the rear surface of the wafer as a result of the first etching phase.

Abstract: The present application discloses process comprising providing a wafer, the wafer comprising an inter-layer dielectric (ILD) having a feature therein, an under-layer deposited on the ILD, and a barrier layer deposited on the under-layer, and a conductive layer deposited in the feature, placing the wafer in an electrolyte, such that at least the barrier layer is immersed in the electrolyte, and applying an electrical potential between the electrode and the wafer.

Abstract: A method for fabricating an electrical interconnect between two or more electrical components. A conductive layer is provided on a substarte and a thin, patterned catalyst array is deposited on an exposed surface of the conductive layer. A gas or vapor of a metallic precursor of a metal nanowire (MeNW) is provided around the catalyst array, and MeNWs grow between the conductive layer and the catalyst array. The catalyst array and a portion of each of the MeNWs are removed to provide exposed ends of the MeNWs.

Abstract: Disclosed herein are a system and method of polishing a layer of a substrate. The disclosed method includes providing a polishing apparatus adapted to impart relative movement between a polishing pad and a substrate having a first layer to be polished; providing a liquid medium having a pH between 4 and 11 to an interface between the substrate and the polishing pad, the liquid medium including a pH controlling substance including at least one of an acid and a base, a carbonate and a stabilizer additive comprising at least one selected from the group consisting of amino acids and polyacrylic acid; and moving at least one of the substrate and the polishing pad relative to the other to polish the layer of the substrate.

Abstract: A chemical supplying apparatus includes first and second mixing tanks for mixing and supplying chemical slurries used in a semiconductor fabrication process. The slurries are alternately provided from the first and second mixing tanks such that the slurry is continuously available to a precessing apparatus for maximum efficiency. While one of the tanks is supplying the slurry, the other tank is cleaned and then used to prepare a new batch of the slurry.

Abstract: According to one aspect of the present invention, a method of electrochemically polishing a semiconductor substrate may be provided. A semiconductor substrate processing fluid, having a plurality of abrasive particles therein, may be placed between the surface of the semiconductor substrate and the polish head. The polish head may be moved relative to the surface of the semiconductor substrate to cause the abrasive particles to polish the surface of the semiconductor substrate. According to a second aspect of the present invention, a method for electro-polishing a semiconductor substrate may be provided. A semiconductor substrate may be placed in an electrolytic solution. A surface of the semiconductor substrate may be contacted with at least one conductive member. A voltage may be applied across the electrolytic solution and the at least one conductive member. The at least one conductive member may be moved across the surface of the semiconductor substrate.

Abstract: A method of fabricating a CMR layer in a CMOS device using CMP to pattern the CMR layer includes preparing a silicon substrate, including fabrication of a bottom electrode in the silicon substrate; depositing a layer of SiNx on the substrate; patterning and etching the SiNx layer to form a damascene trench over the bottom electrode; depositing a layer CMR material over the SiNx and in the damascene trench; removing the CMR material overlying the SiNx layer by CMP, leaving the CMR material in the damascene trench; and completing the CMOS structure.

Abstract: According to a method of manufacturing a semiconductor wafer and a semiconductor device, a rear surface of the semiconductor wafer is ground, and is dry- or wet-etched so that rear surfaces of semiconductor chips on the segmented semiconductor wafer have substantially equal surface roughness. The semiconductor chips are bonded onto a lead frame via bumps using thermo-compression and ultrasonic vibrations.

Abstract: A semiconductor memory device comprises a silicon layer having a first diffused region and a second diffused region formed therein, a gate electrode formed through an insulating film on one side of the silicon layer between the first and the second diffused regions, a capacitor formed on said one side of the silicon layer and having a storage electrode connected to the first diffused region, and a bit line formed on the other side of the silicon layer and connected to the second diffused region, whereby a semiconductor memory device of SOI structure can be easily fabricated. The bit line connected to the second diffused region is formed on the other side of the semiconductor layer, whereby the bit line can be arranged without restriction by the structure, etc. of the capacitor. Short circuit between the capacitor and the bit line can be prevented.

Abstract: A method of fabricating a lapping carrier is provided that includes the steps of defining at least one opening extending through a workpiece that is sized to receive a wafer, and cryogenically tempering the workpiece to produce a lapping carrier. By cryogenically tempering the workpiece, the conversion of the crystalline structure of the workpiece to a martensite crystalline structure is enhanced, thereby improving the hardness of the lapping carrier. A lapping carrier is also provided that has a crystalline structure, of which at least 70% is a martensite crystalline structure. An apparatus for lapping a wafer is further provided that includes a hardened lapping carrier and at least one lapping plate proximate the lapping carrier for lapping wafer(s) disposed within the at least one opening defined by the lapping carrier.

Abstract: The present invention relates to a polishing apparatus for polishing a workpiece such as a semiconductor wafer to a flat mirror finish, and more particularly to a polishing apparatus having a workpiece transfer robot for transferring a workpiece from one operation to the next. The polishing apparatus according to the present invention comprises a polishing section including a top ring for holding a workpiece to be polished and a turntable having a polishing surface for polishing a surface of the workpiece held by the top ring; a cleaning section including a cleaning device for cleaning the workpiece that has been polished in the polishing section; and a workpiece transfer robot for transferring the workpiece to be polished to the polishing section or for transferring the workpiece that has been polished to the cleaning section.

Abstract: A stopper for chemical mechanical planarization comprising an organosilicon polymer, in particular a polycarbosilane, is provided. The stopper used for polishing wafers with a wiring pattern in the manufacture of semiconductor devices to protect interlayer dielectric films made of a material such as SiO2, fluorine dope SiO2, or organic or inorganic SOG (Spin-on glass) from damages during the chemical mechanical planarization process.