Abstract: A polishing slurry for silicon, a method of polishing polysilicon, and a method of manufacturing a thin film transistor substrate, the slurry including a polishing particle; a dispersing agent including an anionic polymer, a hydroxyl acid, or an amino acid; a stabilizing agent including an organic acid, the organic acid including a carboxyl group; a hydrophilic agent including a hydrophilic group and a hydrophobic group, and water, wherein the polishing particle is included in the polishing slurry in an amount of about 0.1% by weight to about 10% by weight, based on a total weight of the slurry, a weight ratio of the polishing particle and the dispersing agent is about 1:0.01 to about 1:0.2, a weight ratio of the polishing particle and the stabilizing agent is about 1:0.001 to about 1:0.1, and a weight ratio of the polishing particle and the hydrophilic agent is about 1:0.01 to about 1:3.

Abstract: A manufacturing method of an electronic device processes a surface of a first wafer, bonds a surface of a second wafer to the processed surface of the first wafer, thins the first wafer by polishing a back surface of the first wafer, the back surface being located on an opposite side of the processed surface, forms a groove along a periphery of the back surface of the thinned first wafer by using a dicing blade, attaches a protective layer to the back surface of the first wafer having the groove, via a bonding layer, and polishes a back surface of the second wafer, the back surface being located on an opposite side of the surface attached to the protective layer.

Abstract: An silicon photonics device of hybrid waveguides having a coupling interlayer with an accurately controlled thickness and a method of making the same. The device includes a first plurality of Si waveguides formed in a SOI substrate and a first layer of SiO2 overlying the first plurality of Si waveguides and a second plurality of Si3N4 waveguides formed on the first layer of SiO2. At least one Si3N4 waveguide is disposed partially overlapping with at least one of the first plurality Si waveguides in vertical direction separated by the first layer of SiO2 with a thickness controlled no greater than 90 nm. The device includes a second layer of SiO2 overlying the second plurality of Si3N4 waveguides. The method of accurately controlling the coupling interlayer SiO2 thickness includes a multilayer SiO2/Si3N4/SiO2 hard mask process for SiO2 etching and polishing as stopping and buffering layer as well as Si waveguide etching mask.

Abstract: Embodiments of the invention provide a polishing composition including colloidal silica, pulverized wet-process silica particles, and a water-soluble polymer compound, wherein the water-soluble polymer compound is a polymer or copolymer having a constituent unit derived from an unsaturated aliphatic carboxylic acid. Various embodiments achieve a high polishing rate and obtain a good surface smoothness and end-face shape without the use of alumina particles.

Abstract: A thermal mixing process is employed to convert a portion of a silicon germanium alloy fin having a first germanium content and an overlying non-doped epitaxial silicon source material into a silicon germanium alloy source structure having a second germanium content that is less than the first germanium content, to convert another portion of the silicon germanium alloy fin and an overlying non-doped epitaxial silicon drain material into a silicon germanium alloy drain structure having the second germanium content, and to provide a tensile strained silicon germanium alloy fin portion having the first germanium content. A dopant is then introduced into the silicon germanium alloy source structure and into the silicon germanium alloy drain structure.

Abstract: Provided are a pressure-sensitive adhesive tape, a polishing pad, a method of manufacturing the same, a polishing device and a method of manufacturing a glass substrate. The illustrative pressure-sensitive adhesive tape may be a pressure-sensitive adhesive tape for a polishing material. The pressure-sensitive adhesive tape may be effectively fixed to a surface plate without bubbles, and have excellent resistance to water and a polishing solution and shear strength applied in a polishing process. In addition, the pressure-sensitive adhesive tape may be easily removed from a carrier or surface plate for a polishing pad without residues after polishing.

Abstract: First and second semiconductor structures, a CESL, and an ILD layer are formed on a substrate. The first semiconductor structure includes first dummy gate, first nitride mask, and first oxide mask. The second semiconductor structure includes second dummy gate, second nitride mask, and second oxide mask. A first planarization is performed to remove a portion of the ILD layer, exposing CESL. A portion of the CESL, a portion of the ILD layer, the first and the second oxide masks are removed. A hard mask layer is formed on the first and the second nitride masks, and in a recess of the ILD layer. A second planarization is performed to remove a portion of the hard mask layer, the first and the second nitride masks, exposing first and second dummy gates. A remaining portion of the hard mask layer covers the ILD layer.

Abstract: Forming a dummy gate on a semiconductor device is disclosed. A first sacrificial layer is formed on a fin, and a second sacrificial layer is formed on the first sacrificial layer. A first hardmask layer is formed on the second sacrificial layer, and a second hardmask layer is formed on the first hardmask layer and patterned. The first hardmask layer is laterally recessed in a lateral direction under the second hardmask layer. The first and second sacrificial layers are etched to a corresponding width of the first hardmask layer. A spacer layer is formed on the fin, the first sacrificial layer, second sacrificial layer, the first hardmask layer and the second hardmask layer. The spacer layer is etched until it remains on a sidewall of the first sacrificial layer, the second sacrificial layer and the first hardmask layer, wherein the first and second sacrificial layers form the dummy gate.

Abstract: A polishing composition is used to polish a polishing subject having a phase change alloy. The polishing composition includes abrasive grains and a brittle film formation agent. The brittle film formation agent is at least one or more selected from a saturated monocarboxylic acid and an organophosphorus compound.

Abstract: Embodiments of methods for forming features in a silicon containing layer of a substrate disposed on a substrate support are provided herein. In some embodiments, a method for forming features in a silicon containing layer of a substrate disposed on a substrate support in a processing volume of a process chamber includes: exposing the substrate to a first plasma formed from a first process gas while providing a bias power to the substrate support, wherein the first process gas comprises one or more of a chlorine-containing gas or a bromine containing gas; and exposing the substrate to a second plasma formed from a second process gas while no bias power is provided to the substrate support, wherein the second process gas comprises one or more of an oxygen-containing gas or nitrogen gas, and wherein a source power provided to form the first plasma and the second plasma is continuously provided.

Abstract: Methods of forming high etch selectivity, low stress ashable hard masks using plasma enhanced chemical vapor deposition are provided. In certain embodiments, the methods involve pulsing low frequency radio frequency power while keeping high frequency radio frequency power constant during deposition of the ashable hard mask using a dual radio frequency plasma source. According to various embodiments, the low frequency radio frequency power can be pulsed between non-zero levels or by switching the power on and off. The resulting deposited highly selective ashable hard mask may have decreased stress due to one or more factors including decreased ion and atom impinging on the ashable hard mask and lower levels of hydrogen trapped in the ashable hard mask.

Abstract: Provided is a memory device. The memory device includes a substrate including a cell area and a peripheral area; gate line stacks and bit line stacks configured to vertically cross in the cell area; buried contacts disposed in areas, which are simultaneously shared by neighboring gate line stacks and neighboring bit line stacks; expanded landing pads including expanded portions connected to the buried contacts and expanded over adjacent bit line stacks, and disposed in a row; landing pads spaced apart from the expanded landing pads as a column, connected to the buried contacts, and having horizontal widths smaller than those of the expanded landing pads; and first storage nodes connected to the expanded portions of the expanded landing pads, and second storage nodes connected to the landing pads.

Abstract: Methods for nanoimprint lithography using a deformable mold. Generally, the method includes a deformable mold fixed firmly onto a hollow mold holder around its full periphery is attached to top inner surface of the chamber and positioned underneath the transparent section. The central area of the mold is freely accessible from underneath through the opening of the mold holder. At beginning of the imprinting, the substrate with a layer of resist is positioned underneath the mold at a predetermined gap between them and a substrate is moved up to contact with the mold either under vacuum or under atmosphere. After consolidating the resist, the substrate is separated from the mold by either direct pull-down enabled by stage movement or deforming the mold enabled by differential pressure between the mold mini-chamber and the bulk volume of the chamber, or mixing of both.

Abstract: A semiconductor process for forming gates with different pitches includes the following steps. A gate layer is formed on a substrate. A first mandrel and a second mandrel are respectively formed on the gate layer. A first spacer material is formed to conformally cover the first mandrel but exposing the second mandrel. A second spacer material is formed to conformally cover the first spacer material and the second mandrel. The first spacer material and the second spacer material are etched to form a first spacer beside the first mandrel and a second spacer beside the second mandrel simultaneously. The first mandrel and the second mandrel are removed. Layouts of the first spacer and the second spacer are transferred to the gate layer, thereby a first gate and a second gate being formed. Moreover, a semiconductor process, which forms the first spacer and the second spacer separately, is also provided.

Abstract: A method and a device for determining the pressure distribution for bonding of a first substrate to a second substrate, with the following steps, especially with the following sequence: placing a measurement layer between a first tool for holding the first substrate and an opposite second tool which is aligned to the first tool for bonding of the substrate, deformation of the measurement layer by bringing the tools closer to one another, measurement of the deformation of the measurement layer and computation of the pressure distribution.

Abstract: An electrochemical process for applying a conductive film onto a substrate having a seed layer includes placing the substrate into contact with an electrochemical plating bath containing cobalt or nickel, with the plating bath having pH of 4.0 to 9.0. Electric current is conducted through the bath to the substrate. The cobalt or nickel ions in the bath deposit onto the seed layer. The plating bath may contain cobalt chloride and glycine. The electric current may range from 1-50 milli-ampere per square cm. After completion of the electrochemical process, the substrate may be removed from the plating bath, rinsed and dried, and then annealed at a temperature of 200 to 400 C to improve the material properties and reduce seam line defects. The plating and anneal process may be performed through multiple cycles.

Abstract: A chemical mechanical polishing method is provided comprising: providing a substrate, wherein the substrate comprises a silicon oxide and a silicon nitride; providing a polishing slurry; providing polishing pad, comprising: a polishing layer having a composition that is a reaction product of ingredients, comprising: a polyfunctional isocyanate and an amine initiated polyol curative; wherein the stoichiometric ratio of the amine initiated polyol curative to the polyfunctional isocyanate is selected to tune the removal rate selectivity of the polishing layer; creating dynamic contact between the polishing surface and the substrate; dispensing the polishing slurry on the polishing pad at or near the interface between the polishing surface and the substrate; and, removing at least some of the silicon oxide and the silicon nitride from the substrate.

Abstract: The invention provides a chemical-mechanical polishing composition containing (a) an abrasive selected from wet-process silica, alpha alumina, fumed alumina, ceria, zirconia, titania, and combinations thereof, (b) an oxidation catalyst, (c) a non-transition metal sulfate salt, (d) a complexing agent, (e) hydrogen peroxide, (f) a nonionic surfactant, (g) an anionic surfactant, and (h) water. The polishing composition has a pH of about 1 to about 5, and the polishing composition is substantially free of a peroxydisulfate salt. The invention also provides a method of chemically-mechanically polishing a substrate, especially a nickel-phosphorous substrate, by contacting a substrate with a polishing pad and the chemical-mechanical polishing composition, moving the polishing pad and the polishing composition relative to the substrate, and abrading at least a portion of the substrate to polish the substrate.

Abstract: A method of forming a semiconductor device including a semiconductor substrate having a first surface and a second surface, and having a gallium nitride-containing layer provided on the first surface of the semiconductor substrate includes grinding, polishing, and etching the second surface of the semiconductor substrate of which a thickness is d1, and reducing the thickness of the semiconductor substrate to one-fifth or less of d1.

Abstract: A method of controlling polishing includes storing a desired ratio representing a ratio for a clearance time of a first zone of a substrate to a clearance time of a second zone of the substrate. During polishing of a first substrate, an overlying layer is monitored, a sequence of measurements is generated, and the measurements are sorted a first group associated with the first zone of the substrate and a second group associated with the second zone on the substrate. A first time and a second time at which the overlying layer is cleared is determined based on the measurements from the first group and the second group, respectively. At least one adjusted polishing pressure is calculated for the first zone based on a first pressure applied in the first zone during polishing the first substrate, the first time, the second time, and the desired ratio.

Abstract: A patterning method is provided. Mask structures including first mask layers and first photoresist layers are formed sequentially on a material layer. A second mask layer covering the mask structures is conformally formed on the material layer. First sacrificed layers are formed between the mask structures. Parts of the second mask layer are removed to expose the first photoresist layers and form first U-shape mask layers. The first photoresist layers and the first sacrificed layers are removed. A third mask layer having first surfaces and second surfaces lower than the first surfaces is conformally formed on the material layer. Second sacrificed layers are formed on the second surfaces. Parts of the third mask layer are removed to expose protrusions of the first U-shape mask layers and form second U-shape mask layers. The material layer is patterned by using protrusions of the second U-shape mask layers as masks.

Abstract: The present disclosure describes methods of an interface adhesion improvement methods used on a transparent substrate for OLED or thin film transistor applications. In one embodiment, a method of forming a buffer layer on a surface of a substrate includes providing a substrate having an planarization material disposed thereon in a processing chamber, supplying a buffer layer gas mixture including a silicon containing gas into the processing chamber, controlling a substrate temperature less than about 100 degrees Celsius, forming a buffer layer on the planarization material, supplying an encapsulating barrier layer deposition gas mixture including a silicon containing gas and a nitrogen containing gas into the processing chamber, and forming an encapsulating barrier layer on the buffer layer.

Abstract: A device and methods for forming a device are disclosed. A substrate is provided and a TSV is formed in the substrate through a top surface of the substrate. The TSV and top surface of the substrate is lined with an insulation stack having a first insulation layer, a polish stop layer and a second insulation layer. A conductive layer is formed on the substrate. The TSV is filled with conductive material of the conductive layer. The substrate is planarized to remove excess conductive material of the conductive layer. The planarizing stops on the polish stop layer to form a planar top surface.

Abstract: A trilayer stack that can be used as a block mask for forming patterning features in semiconductor structures with high aspect ratio topography is provided. The trilayer stack includes an organic planarization (OPL) layer, a titanium-containing antireflective coating (TiARC) layer on the OPL layer and a photoresist layer on the TiARC layer. Employing a combination of an OPL having a high etch rate and a TiARC layer that can be easily removed by a mild chemical etchant solution in the trilayer stack can significantly minimize substrate damage during lithographic patterning processes.

Abstract: A method of fabricating a fin field effect transistor (FinFET) device and the device are described. The method includes forming a deep STI region adjacent to a first side of an end fin among a plurality of fins and lining the deep STI region, including the first side of the end fin, with a passivation layer. The method also includes depositing an STI oxide into the deep STI region, the passivation layer separating the STI oxide and the first side of the end fin, etching back the passivation layer separating the STI oxide and the first side of the end fin to a specified depth to create a gap, and depositing gate material, the gate material covering the gap.

Abstract: The present invention provides an etching solution for silver or silver alloy comprising one at least ammonium compound represented by the formula (1), (2) or (3) below and an oxidant: wherein each of the variables is as defined herein.

Abstract: A method includes forming an n-FET device and a p-FET device on a substrate, each of the n-FET device and the p-FET device include a metal gate stack consisting of a titanium-aluminum carbide (TiAlC) layer above and in direct contact with a titanium nitride (TiN) cap, and removing, from the p-FET device, the TiAlC layer selective to the TiN cap. The removal of the TiAlC layer includes using a selective TiAlC to TiN wet etch chemistry solution with a substantially high TiAlC to TiN etch ratio such that the TiN cap remains in the p-FET device.

Abstract: Disclosed is a plasma etching method which suppresses the narrowing of the line-width of the line formed by etching and maintain the height of a remaining photoresist. The plasma etching method includes a modification process and an etching process. The modification process modifies a photoresist having a predetermined pattern by plasma of HBr/Ar gas while applying a negative DC voltage to an upper electrode containing silicon disposed to face a target object in which an organic film and the photoresist are sequentially laminated. The etching process etches the organic film by plasma of a processing gas which contains a CF-based gas and a CHF-based gas.

Abstract: Two-step process sequences uniformly etch both tungsten-based and titanium-based structures on a substrate. A sequence of wet etches using peroxide and heated nitric acid uniformly recesses a metal stack that includes W, TiN, and TiAl. W, TiN and TiC are uniformly recessed by a peroxide etch at ˜25 C followed by an acid solution with a very small amount of added peroxide at ˜60 C. TiC is etched without etching trench oxides or other metals in a work-function metal stack by either (1) highly-dilute of ultra-dilute HF at 25-35 C, (2) dilute HCl at 25-60 C, (3) dilute NH4OH at 25-60 C, or (4) solution (2) or (3) with small amounts of peroxide. Other metals in the stack may then be plasma-etched without being blocked by TiC residues.

Abstract: One or more techniques or systems for determining double patterning technology (DPT) layout routing compliance are provided herein. For example, a layout routing component of a system is configured to assign a pin loop value to a pin loop. In some embodiments, the pin loop value is assigned based on a mask assignment of a pin of the pin loop. In some embodiments, the pin loop value is assigned based on a number of nodes associated with the pin loop. DPT compliance or a DPT violation is determined for the pin loop based on the pin loop value. In this manner, odd loop detection associated with DPT layout routing is provided because a DPT violation results in generation of an additional instance of a net, for example. Detecting an odd loop allows a design to be redesigned before fabrication, where the odd loop would present undesired issues.

Abstract: Disclosed herein is a method for fabricating an optical device that includes depositing an etch stop material to form an etch stop layer, wherein the etch stop material has a refractive index in the infrared wavelength range, n1; depositing a core material to form a core layer, wherein the core material has a refractive index in the infrared wavelength range, n2; and etching the core layer using a halide based etch process, wherein the etch stop material has an etch rate in the halide based etch process and the core material has an etch rate in the halide based etch process, wherein the etch rate of the core material is at least about five times higher than the etch rate of the etch stop material, and wherein n1 is not greater than n2.

Abstract: A substrate processing apparatus includes first and second polishing units for polishing a peripheral portion of a substrate, a primary cleaning unit for cleaning the substrate, a secondary cleaning and drying unit for drying the substrate cleaned in the primary cleaning unit, and a measurement unit for measuring the peripheral portion of the substrate. The measurement unit includes a mechanism for measurement required for polishing in the first and second polishing units, such as a diameter measurement mechanism, a cross-sectional shape measurement mechanism, or a surface condition measurement mechanism.

Abstract: An integrated circuit contains a high precision capacitor having a bottom plate, a dielectric layer over the bottom plate, a capacitor opening in the dielectric layer exposing, and not overlapping, the bottom plate, a capacitor dielectric layer covering sidewalls and a bottom of the capacitor opening, a top plate covering the capacitor dielectric layer in the capacitor opening, and a capacitor planarizing dielectric layer covering the capacitor top plate in the capacitor opening. A top surface of the capacitor planarizing dielectric layer and a top edge of the capacitor top plate are substantially coplanar. The top plate does not extend laterally beyond the capacitor opening. A method of forming the integrated circuit the high precision capacitor is also disclosed.

Abstract: Methods for planarizing layers of a material, such as a dielectric, and interconnect structures formed by the planarization methods. The method includes depositing a first dielectric layer on a top surface of multiple conductive features and on a top surface of a substrate between the conductive features. A portion of the first dielectric layer is selectively removed from the top surface of at least one of the conductive features without removing a portion the first dielectric layer that is between the conductive features. A second dielectric layer is formed on the top surface of the at least one of the conductive features and on a top surface of the first dielectric layer, and a top surface of the second dielectric layer is planarized. A layer operating as an etch stop is located between the top surface of at least one of the conductive features and the second dielectric layer.

Abstract: A chemical mechanical polishing pad is provided containing: a polyurethane polishing layer having a composition and a polishing surface; wherein the polyurethane polishing layer composition exhibits an acid number of ?0.5 mg (KOH)/g; wherein the polishing surface is adapted for polishing a substrate; and, wherein the polishing surface exhibits a conditioning tolerance of ?80%.

Abstract: A polishing apparatus polishes a surface of a substrate by pressing the substrate against a polishing pad on a polishing table. The polishing apparatus includes a polishing liquid supply nozzle for supplying a polishing liquid onto the polishing pad, a polishing liquid storage mechanism disposed on the polishing pad for storing the polishing liquid on the polishing pad by damming the polishing liquid, and a polishing liquid sensor for measuring a physical quantity representing the freshness of the polishing liquid stored by the polishing liquid storage mechanism. The polishing apparatus further includes a freshness measuring instrument for calculating the freshness of the stored polishing liquid from the physical quantity measured by the polishing liquid sensor, and a freshness controller for controlling supply conditions of the polishing liquid or storage state of the polishing liquid, based on the freshness of the polishing liquid that is determined by the freshness measuring instrument.

Abstract: A method and apparatus for providing a substantially uniform pressure to a polishing surface from a conditioning element is provided. The method includes urging a conditioning disk against a polishing surface of a rotating polishing pad, moving the conditioning disk across the polishing surface in a sweep pattern that includes at least a portion of the conditioning disk extending over a peripheral edge of the polishing surface, and maintaining a substantially uniform pressure to the polishing surface from the conditioning disk across the sweep pattern.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In accordance with an exemplary embodiment, a method for fabricating an integrated circuit includes exposing a portion of a surface of a semiconductor substrate between a first spacer and a second spacer. The method further includes selectively forming a dielectric layer on the portion of the surface. A metal gate is formed over the dielectric layer and between the first spacer and the second spacer. The metal gate contacts the first spacer and the second spacer.

Abstract: Integrated circuits with reduced shorting and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes depositing a gap fill dielectric overlying a semiconductor substrate. The gap fill dielectric is formed with an upper surface having a height differential. The method includes reducing the height differential of the upper surface of the gap fill dielectric. Further, the method includes depositing an interlayer dielectric overlying the gap fill dielectric. Also, the method forms an electrical contact to a selected location overlying the semiconductor substrate.

Abstract: A substrate surface comprises at least partially at least one elongated structure, wherein each elongated structure comprises a plurality of channels, said channels extending in the direction of the longitudinal axis of the elongated structure, wherein said at least one elongated structure comprises silicon dioxide. The structures are manufactured by: a) providing a reaction solution comprising a silicate, a micelle forming agent, an alkane, a salt, and at least 1.5 M HCl, having a pH of 2 or lower, b) stirring not more than 10 minutes, c) bringing the reaction solution into contact with a substrate surface and d) treating the obtained material with one method selected from a) heat treating the material above 300° C., b) treating the material with at least one selected from H2O2, and H2SO4, c) treating the material with microwaves to digest the micelle forming agent.

Abstract: A method is provided for fabricating an interconnection structure. The method includes providing a substrate having certain semiconductor devices, a metal layer electrically connecting with the semiconductor devices, and a barrier layer on the metal layer. The method also includes forming a dielectric layer on the substrate; and forming an antireflective coating on the dielectric layer. Further, the method includes forming a second mask having a first pattern corresponding to a through hole in the dielectric layer, wherein the antireflective coating significantly reduces lithographic light reflection to avoid photoresist residue in the first pattern; and forming a through hole by etching the dielectric layer and the antireflective coating covering the dielectric layer using the second mask as an etching mask. Further, the method also includes forming a via by filling the through hole with a conductive material.

Abstract: A system for measuring a mass property of an object is provided. The system includes a first shaft having a first end and a second end and a table disposed in a first plane and coupled to the first shaft at a predetermined angle to support the object. The table is configured to pivot about an axis perpendicular to the first plane between at least a first pivot position and a second pivot position. The system further includes a torque sensor configured to collect a first torque measurement on the first shaft when the table is in the first pivot position and a second torque measurement on the first shaft when the table in the second pivot position.

Abstract: The invention provides a chemical-mechanical polishing composition containing a ceria abrasive and a polymer of formula I: wherein X1 and X2, Y1 and Y2, Z1 and Z2, R1, R2, R3, and R4, and m are as defined herein, and water, wherein the polishing composition has a pH of about 1 to about 4.5. The invention further provides a method of chemically-mechanically polishing a substrate with the inventive chemical-mechanical polishing composition. Typically, the substrate contains silicon oxide, silicon nitride, and/or polysilicon.

Abstract: A chemical-mechanical polishing machine includes a work table, polishing platen mounted onto the work table, pad conditioner and slurry-delivery device mounted on the work table and disposed near the polishing platen, and polishing-head support mounted on the work table and including a base plate and supporting side plates. The base plate is formed with a groove in a “thickness” direction. A loading and unloading table is mounted on the work table, disposed below the base plate, and opposed to the polishing platen. A polishing head is rotatably disposed on the polishing-head support, movable in the longitudinal direction, and passes through the groove to extend downwardly. A robotic manipulator is disposed near the work table for placing a wafer on the loading and unloading table and taking the wafer away from it. A chemical-mechanical polishing apparatus includes an array of a plurality of the machine.

Abstract: A chemical mechanical polishing composition includes a water based liquid carrier and first and second silica abrasives dispersed in the liquid carrier. The first silica abrasive is a colloidal silica abrasive having a permanent positive charge of at least 10 mV. The second silica abrasive has a neutral charge or a non-permanent positive charge. A method for chemical mechanical polishing a substrate including a tungsten layer includes contacting the substrate with the above described polishing composition, moving the polishing composition relative to the substrate, and abrading the substrate to remove a portion of the tungsten from the substrate and thereby polish the substrate.

Abstract: According to one embodiment, a semiconductor device manufacturing method includes: bonding a first wafer and a second wafer to each other, to form a stack; rubbing a film attached with a fill material in a thin-film shape into a gap located between a bevel of the first wafer and a bevel of the second wafer, to fill the gap with the fill material; and thinning the first wafer.

Abstract: Photo mask sets and methods of fabricating fine patterns are provided. The method includes forming a first layer having a first main pattern part and a first dummy pattern part on a base layer, forming a second layer on the first layer, etching the first layer using the second layer as an etch mask to form a third main pattern part composed of a remaining portion of the first main pattern part and to remove the first dummy pattern part, and removing the second layer. The second layer is formed to have a second main pattern part exposing portions of the first main pattern part and to have a second dummy pattern part exposing the first dummy pattern part.

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) includes a semiconductor substrate and an interlayer dielectric (ILD) over the semiconductor substrate. A gate structure is formed within the ILD and disposed on the semiconductor substrate, wherein the gate structure includes a high-k dielectric material layer and a metal gate stack. One or more portions of a protection layer are formed over the gate stack, and a contact etch stop layer is formed over the ILD and over the one or more portions of the protection layer. The metal gate stack includes aluminum and the protection layer includes aluminum oxide.

Abstract: Disclosed herein is a method of forming a structure, comprising forming a mandrel layer over a substrate, masking the mandrel layer with a first mask and performing a first etch on the mandrel layer, the first etch forming a first opening exposing a first portion of the substrate. The mandrel layer is masked with a second mask and a second etch is performed on the mandrel layer. The second etch forms a second opening exposing a second portion of the substrate, and also forms a protective layer on the first portion of the substrate and in the first opening.

Abstract: An active matrix substrate (20a) includes a gate electrode (25) formed on an insulating substrate (10a), and a planarizing film (26) formed on the gate electrode (25) and made of a baked SOG material. The gate electrode (25) is a multilayer film including a first conductive film (27) formed on the insulating substrate (10a) and made of a metal except copper, a second conductive film (28) formed on the first conductive film (27) and made of copper, and a third conductive film (29) formed on the second conductive film (28) and made of the metal except copper.