Abstract: A photovoltaic cell is provided, including a substrate; a marked region on a surface of the substrate, configured to mark product information of the photovoltaic cell; a first texture structure in the marked region on the surface of the substrate, including at least one first protrusion structure and at least one second protrusion structure, a respective first protrusion structure of the at least one first protrusion structure has a recessed top surface recessing toward a bottom surface of the respective first protrusion structure, and a respective second protrusion structure of the at least one second protrusion structure includes a pyramid structure; and a second texture structure disposed on a part of the surface of the substrate outside the marked region, where the second texture structure includes at least one third protrusion structure, and a respective third protrusion structure of the at least one third protrusion structure includes a pyramid structure.

Abstract: A method of transferring a micro light emitting diode (LED) to a pixel array panel includes transferring the micro LED by spraying using an inkjet method, wherein the micro LED includes an active layer including a first portion emitting light in a first direction and a second portion emitting the light in a second direction different from the first direction.

Abstract: A method of aligning light-emitting elements, a method of fabricating a display device, and a display device are provided. The method of aligning light-emitting elements comprises providing a base substrate and a plurality of conductive patterns on the base substrate and spaced apart from one another, spraying ink in which a plurality of light-emitting elements are dispersed on the base substrate, positioning the plurality of light-emitting elements on the conductive pattern and orienting one end of each of the plurality of light-emitting elements in a first direction.

Abstract: A polishing composition according to the present invention contains silica, a nitrogen-containing alkaline compound, and hydrogen peroxide, in which a content of the hydrogen peroxide is more than 0% by mass and less than 0.03% by mass with respect to the total mass of the polishing composition, and a pH exceeds 9.

Abstract: A method of producing a silicon wafer includes: a laser mark printing step of printing a laser mark having a plurality of dots on a silicon wafer; an etching step of performing etching on at least a laser-mark printed region in a surface of the silicon wafer; and a polishing step of performing polishing on both surfaces of the silicon wafer having been subjected to the etching step. In the laser mark printing step, each of the plurality of dots is formed by a first step of irradiating a predetermined position on a periphery of the silicon wafer with laser light of a first beam diameter thereby forming a first portion of the dot and a second step of irradiating the predetermined position with laser light of a second beam diameter that is smaller than the first beam diameter thereby forming a second portion of the dot.

Abstract: A semiconductor wafer of monocrystalline silicon. The semiconductor wafer having: a substrate wafer of monocrystalline silicon; and a layer of monocrystalline silicon that lies on a front side of the substrate wafer. The substrate wafer has a crystal orientation. An averaged front side-based ZDD of the semiconductor wafer, with a division of a surface of an epitaxial layer into 16 sectors and an edge exclusion of 1 mm, is not less than ?30 nm/mm2 and not more than 0 nm/mm2. An ESFQRmax of the semiconductor wafer, with an edge exclusion of 1 mm and 72 sectors each with a length of 30 mm, is at most 10 nm.

Abstract: A polishing composition includes an abrasive; a pH adjuster; a barrier film removal rate enhancer; a low-k removal rate inhibitor; an azole-containing corrosion inhibitor; and a hard mask removal rate enhancer. A method of polishing a substrate includes the steps of: applying the polishing composition described herein to a surface of a substrate, wherein the surface comprises ruthenium or a hard mask material; and bringing a pad into contact with the surface of the substrate and moving the pad in relation to the substrate.

Abstract: Shortcomings associated with insufficient control of a conventional CMP-process are obviated by providing an CMP-apparatus configured to complement a constant force (to which a workpiece that is being polished is conventionally exposed) with a time-alternating force and/or means for measuring an electrical characteristic of the CMP-process. The time-alternating force is applied with the use of a system component that is electrically isolated from the workpiece and that is disposed in the carrier-chick in which the workpiece is affixed for CMP-process, while the electrical characteristic is measured with the use of a judiciously-configured reservoir in which the used fluid is collected. The use of such CMP-apparatus.

Abstract: A base support plate includes a support plate body. A support surface of the support plate body is configured to support a flexible base of a flexible display panel. The base support plate further includes a plurality of micro-structures disposed on the support surface of the support plate body, and the plurality of micro-structures are configured to diffuse incident light and transmit the incident light to the flexible base.

Abstract: Integrated chips and methods of forming conductive lines thereon include forming parallel lines from alternating first and second dummy materials. Portions of the parallel lines are etched, using respective selective etches for the first and second dummy materials, to form gaps. The gaps are filled with a dielectric material. The first and second dummy materials are etched away to form trenches. The trenches are filled with conductive material.

Abstract: Techniques for dynamically generating self-aligned double patterning (SADP) gate regions based on gate distribution and the relocation of the gates to their matched region are provided. In one aspect, a method for generating SADP gate regions in a circuit design includes: obtaining a circuit design having SADP gates, and a placement solution for the SADP gates that, while non-overlapping, violates SADP track routing matching requirements; determining approximate locations of SADP regions in the circuit design; assigning the SADP gates to the SADP regions using a minimum-cost maximum-flow (min-cost max-flow) process; and identifying, once all of the SADP gates have been assigned to the SADP regions, non-overlapping locations for the SADP gates in the SADP regions.

Abstract: Provided herein are compositions and methods for polishing surfaces comprising cobalt and optionally a low-K material, e.g., in semiconductor device fabrication. Embodiments include a slurry for chemical mechanical polishing a surface comprising cobalt and low-K materials, such as Black Diamond (BD) or SiN, comprising a complexor, an oxidizer, an abrasive, a Co corrosion inhibitor and an ILD suppressor.

Abstract: A semiconductor device includes a substrate, two gate structures, an interlayer dielectric layer and a material layer. The substrate has at least two device regions separated by at least one isolation structure disposed in the substrate. Each device region includes two doped regions in the substrate. The gate structures are respectively disposed on the device regions. In each device region, the doped regions are respectively disposed at two opposite sides of the gate structure. The interlayer dielectric layer is disposed over the substrate and peripherally surrounds the gate structures. A top of the interlayer dielectric layer has at least one concave. The material layer fills the concave and has a top surface elevated at the same level with top surfaces of the gate structures. A ratio of a thickness of a thickest portion of the material layer to a pitch of the gate structures ranges from 1/30 to 1/80.

Abstract: A device with improved device performance, and method of manufacturing the same, are disclosed. An exemplary device includes a group III-V compound semiconductor substrate that includes a surface having a (110) crystallographic orientation, and a gate stack disposed over the group III-V compound semiconductor substrate. The gate stack includes a high-k dielectric layer disposed on the surface having the (110) crystallographic orientation, and a gate electrode disposed over the high-k dielectric layer.

Abstract: A method of processing a wafer includes a grinding step of grinding a wafer that has first insulating films covering via electrodes, from a reverse side thereof, an electrode protruding step of protruding the via electrodes covered with the first insulating films from the reverse side by way of etching, a distorted layer forming step of forming a distorted layer on the reverse side of the wafer, an insulating film forming step of forming a second insulating film on the reverse side of the wafer, and an electrode forming step of removing the first insulating films and the second insulating film from the regions where they overlap the via electrodes, and forming reverse-side electrodes connected to the via electrodes.

Abstract: A method of processing a wafer includes a grinding step of grinding a reverse side of a wafer that has first insulating films covering via electrodes, an electrode protruding step of protruding the via electrodes covered with the first insulating films from the reverse side by supplying a first etching gas turned to a plasma, an insulating film forming step of covering the reverse side with a second insulating film, a via electrode exposing step of supplying a second etching gas turned to a plasma to expose the via electrodes after having formed a resist film having openings overlapping the via electrodes, and an electrode forming step of forming electrodes connected to the via electrodes.

Abstract: A retaining ring for a chemical mechanical polishing carrier head having a mounting surface for a substrate is provided herein. In some embodiments, the retaining ring may include an annular body have a central opening, a channel formed in the body, wherein a first end of the channel is proximate the central opening, and a sensor disposed within the channel and proximate the first end, wherein the sensor is configured to detect acoustic and/or vibration emissions from processes performed on the substrate.

Abstract: A polishing agent for polishing a resin comprises abrasive grains, a water-soluble polymer having an ether bond, an organic solvent and water, wherein the abrasive grains have a positive charge in the polishing agent and an average particle diameter of the abrasive grains is larger than 20 nm.

Abstract: A substrate processing apparatus according to an embodiment includes a substrate processing tank, a temperature adjustment unit, and a controller. The substrate processing tank is configured to perform an etching processing by immersing a substrate in a phosphoric acid processing liquid therein. The temperature adjustment unit is configured to adjust the temperature of the phosphoric acid processing liquid. The controller is configured to control the temperature adjustment unit to lower the temperature of the phosphoric acid processing liquid as the etching processing proceeds.

Abstract: A method for manufacturing a non-volatile memory device is provided. The method includes the following steps. A plurality of isolation structures are formed in a substrate, and a depression region is formed between two adjacent isolation structures. A conductive layer and a sacrificial layer are conformally formed on the isolation structures and the substrate. The sacrificial layer in the depression region defines a recess part. A first CMP process is performed to partially remove the sacrificial layer and to expose the conductive layer on the isolation structures. A second CMP process is performed to partially remove conductive layer, and to expose top surfaces of the isolation structures. A third CMP process is performed to remove the sacrificial layer completely. A top surface of the conductive layer is level with a top surface of the isolation structure after the third CMP process.

Abstract: A system, a control method and an apparatus for chemical mechanical polishing (CMP) are introduced in the present application. The CMP apparatus may include a polishing pad, a first sensor, a polishing head and a condition. The polishing pad has a plurality of groves arranged randomly or in a specific pattern. The first sensor is configured to measure the pad profile of the polishing pad, where the pad profile includes the depth of each of the grooves on the polishing pad. The polishing head and the conditioner are operated according to at least one polishing condition, and the at least one polishing condition is tuned according to the pad profile.

Abstract: The present disclosure provides chemical mechanical polishing compositions that achieve minimal dishing at reduced dishing reducer (DR) levels when compared to known CMP compositions. The compositions of the disclosure include a dynamic surface tension reducer (DSTR) which allows for lower levels of dishing reducer in the compositions. Indeed, the compositions of the disclosure allow for lower levels of dishing reducer to achieve the same dishing as known compositions having higher levels of dishing reducer. Deleterious effects of high DR levels are thereby avoided or minimized when employing the compositions of the disclosure.

Abstract: A chemical-mechanical polishing (CMP) composition is provided comprising (A) one or more compounds selected from the group of benzotriazole derivatives which act as corrosion inhibitors and (B) inorganic particles, organic particles, or a composite or mixture thereof. The invention also relates to the use of certain compounds selected from the group of benzotriazole derivatives as corrosion inhibitors, especially for increasing the selectivity of a chemical mechanical polishing (CMP) composition for the removal of tantalum or tantalum nitride from a substrate for the manufacture of a semiconductor device in the presence of copper on said substrate.

Abstract: In some embodiments, a method of forming an integrated circuit includes providing a semiconductor substrate having an electronic circuit formed on a front side, and having a first material layer located over a second side of the substrate and a second material layer located between the first material layer and the second side. At least a portion of the first material layer is removed using a first chemical etching process, thereby exposing the second material layer. At least a portion of the second material layer is removed using a second chemical etching process. A portion of the substrate is then mechanically removed from the second side.

Abstract: The system described herein relates to an object preparation device for preparing an object in a particle beam apparatus. By way of example, the particle beam apparatus is an electron beam apparatus and/or an ion beam apparatus. The system described herein moreover relates to a particle beam apparatus having such an object preparation device and to a method for operating the particle beam apparatus. The object preparation device may have an object receptacle device for receiving the object, a cutting device and a cutting bevel for cutting the object, wherein the cutting bevel may be arranged at the cutting device. The cutting bevel may lay in a cutting plane. Further, an axis of rotation may lay in the cutting plane. The cutting bevel may be embodied to be rotatable about the axis of rotation.

Abstract: A dry etching method includes performing at least two etching steps, and further includes injecting protective gas into an etch chamber for processing between any two successive etching steps, wherein the protective gas generates plasma to neutralize electrons accumulated on a side wall of an etching trench. According to the present disclosure, hydrogen plasma is added in an etching process to remove the electrons accumulated on the side wall of the etching trench so as to reduce the microetching effect in multiple etching. In this way, process stability and reliability of a display substrate are improved.

Abstract: A process for removing a bulk material layer from a substrate and planarizing the exposed surface by CMP by (1) providing an CMP agent exhibiting at the end of the chemical mechanical polishing, without the addition of supplementary materials, the same SER as at its start and a lower MRR than at its start, —an SER which is lower than the initial SER and an MRR which is the same or essentially the same as the initial MRR or a lower SER and a lower MRR than at its start; (2) contacting the surface of the bulk material layer with the CMP agent; (3) the CMP of the bulk material layer with the CMP agent; and (4) continuing the CMP until all material residuals are removed from the exposed surface; and a CMP agent and their use for manufacturing electrical and optical devices.

Abstract: Formation methods of a semiconductor device structure are provided. A method includes forming a dielectric layer over a first conductive feature and a second conductive feature. The method also includes depositing a conformal layer in a first via hole and a second via hole in the dielectric layer. The method further includes removing the conformal layer in the second via hole. The dielectric layer remains covered by the conformal layer in the first via hole. In addition, the method includes etching the conformal layer in the first via hole and the dielectric layer until the first conductive feature and the second conductive feature become exposed through the first via hole and the second via hole, respectively. The method also includes forming a third conductive feature in the first via hole and a fourth conductive feature in the second via hole.

Abstract: A method includes forming a metal hard mask over a low-k dielectric layer. The step of forming the metal hard mask includes depositing a sub-layer of the metal hard mask, and performing a plasma treatment on the sub-layer of the metal hard mask. The metal hard mask is patterned to form an opening. The low-k dielectric layer is etched to form a trench, wherein the step of etching is performed using the metal hard mask as an etching mask.

Abstract: An example film forming device is provided with: a chamber for forming a film on a substrate; a supply tube for supplying a cleaning gas to the chamber; and a plasma generating unit, which is provided to the supply tube, and which generates plasma from the cleaning gas. The film forming device is characterized by being provided with: a temperature control unit that controls the temperature of the supply tube to temperature equal to or higher than a predetermined temperature; and a supply unit which supplies, each time when a previously set time equal to or shorter than 36 hours elapses, the chamber with the plasma thus generated by the plasma generating unit.

Abstract: In some embodiments, a method includes wet-etching a first film layer of a plurality of film layers stacked on a semiconductor substrate, the wet-etching of the first film layer performed using a first chemical, where the first film layer is an outermost film layer stacked on the semiconductor substrate. The method further includes wet-etching a second film layer of the plurality of film layers using a second chemical. The method also includes using a mechanical grinding wheel to grind the semiconductor substrate to reduce a thickness of the semiconductor substrate.

Abstract: Provided herein are abrasive compositions that use surfactants containing block copolymers of both propylene oxide and ethylene oxide moieties. Abrasive compositions derived from these copolymers were capable of providing both superior levels of cut rate while preserving a high quality surface finish on gelcoat surfaces comparable to those achieved using conventional rubbing compounds.

Abstract: A process for chemical mechanical polishing a substrate containing cobalt and TiN to at least improve cobalt: TiN removal rate selectivity. The process includes providing a substrate containing cobalt and TiN; providing a polishing composition, containing, as initial components: water; an oxidizing agent; alanine or salts thereof; and, colloidal silica abrasives with diameters of ?25 nm; and, providing a chemical mechanical polishing pad, having a polishing surface; creating dynamic contact at an interface between the polishing pad and the substrate; and dispensing the polishing composition onto the polishing surface at or near the interface between the polishing pad and the substrate; wherein some of the cobalt is polished away such that there is an improvement in the cobalt: TiN removal rate selectivity.

Abstract: A method for partially filling an open feature on a substrate includes receiving a substrate having a layer with at least one open feature formed therein, wherein the open feature penetrates into the layer from an upper surface and includes sidewalls extending to a bottom of the open feature. The open feature is overfilled with an organic coating that covers the upper surface of the layer and extends to the bottom of the open feature. The method further includes removing a portion of the organic coating to expose the upper surface of the layer and recessing the organic coating to a pre-determined depth from the upper surface to create an organic coating plug of pre-determined thickness at the bottom of the open feature, and converting the chemical composition of the organic coating plug to create an inorganic plug.

Abstract: Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a conductive material in the trench and over a top surface of the material layer and polishing the conductive material with a slurry to expose the top surface of the material layer and to form a conductive structure in the trench. The method for forming a semiconductor structure further includes forming a material layer over a substrate and forming a trench in the material layer. The method for forming a semiconductor structure further includes removing the slurry with a reducing solution. In addition, the reducing solution includes a reducing agent, and a standard electrode voltage of the conductive material is greater than a standard electrode voltage of the reducing agent.

Abstract: Disclosed herein is a wet paper friction material for vehicles. The wet paper friction material comprises: a matrix containing a hardwood pulp in an amount of about 40 to 50% by weight; a spherical silica in an amount of about 16 to 21% by weight; a friction modifier in an amount of about 5% by weight or less but greater than 0% by weight; and a filler constituting the remaining balance of the wet paper friction material, and all the % by weights are based on the total weight of the wet paper friction material.

Abstract: Methods for mounting and dismounting thin and/or bowed semiconductor-on-diamond wafers (401) to a carrier (407) are disclosed that flatten said wafers and provide mechanical support to enable efficient semiconductor device processing on said semiconductor-on-diamond wafers.

Abstract: Methodologies and a device for SRAM patterning are provided. Embodiments include forming a spacer layer over a fin channel, the fin channel being formed in four different device regions; forming a bottom mandrel over the spacer layer; forming a top mandrel directly over the bottom mandrel, wherein the top and bottom mandrels including different materials; forming a buffer oxide layer over the top mandrel; forming an anti-reflective coating (ARC) over the first OPL; forming a photoresist (PR) over the ARC and patterning the PR; and etching the first OPL, ARC, buffer oxide, and top mandrel with the pattern of the PR, wherein a pitch of the PR as patterned is different in each of the four device regions.

Abstract: An optical component includes an optical device comprising a bonding face and an optically polished end face, and a metal film formed on the bonding face of the optical device and for bonding the optical device onto a substrate. The metal film includes a main covering portion covering a region except an end part of the bonding face on the side of the end face and an end part-covering portion covering the bonding face in the end part. A non-covered part, which is not covered by the metal film, is provided between the main covering portion and end part-covering portion.

Abstract: An etching composition includes about 1 wt % to about 7 wt % of hydrogen peroxide, about 20 wt % to about 80 wt % of phosphoric acid, about 0.001 wt % to about 1 wt % of an amine or amide polymer, 0 wt % to about 55 wt % of sulfuric acid, and about 10 wt % to about 45 wt % of deionized water.

Abstract: Provided is a polishing composition, which comprises abrasive grains, a water-soluble polymer, an aggregation inhibitor and water. The ratio R1/R2 is 1.3 or less, where R1 represents the average particle diameter of the particles present in the polishing composition and R2 represents the average particle diameter of the abrasive grains when the abrasive grains are dispersed in water at the same concentration as that of the abrasive grains in the polishing composition. The polishing composition can be used mainly for polishing the surface of a silicon substrate.

Abstract: Provided is a polishing liquid including cerium oxide particles, an organic acid A, a polymer compound B having a carboxyl acid group or a carboxylate group, and water, wherein the organic acid A has at least one group selected from the group consisting of —COOM group, -Ph-OM group, —SO3M group and —PO3M2 group, pKa of the organic acid A is less than 9, a content of the organic acid A is 0.001 to 1 mass % with respect to the total mass of the polishing liquid, and a content of the polymer compound B is 0.01 to 0.50 mass % with respect to the total mass of the polishing liquid, and pH is in the range of 4.0 to 7.0.

Abstract: The present disclosure provides a substrate structure for a micro electro mechanical system (MEMS) device. The substrate structure includes a cap and a micro electro mechanical system (MEMS) substrate. The cap has a cavity, and the MEMS substrate is disposed on the cap. The MEMS substrate has a plurality of through holes exposing the cavity, and an aspect ratio of the through hole is greater than 30.

Abstract: The invention provides a polishing composition that contains (a) ?-alumina particles that have an average particle size of about 250 nm to about 300 nm, (b) a per-type oxidizing agent, (c) a complexing agent, wherein the complexing agent is an amino acid or an organic acid, and (d) water. The invention also provides a method of polishing a substrate, especially a nickel-phosphorous substrate, with the polishing composition.

Abstract: A polish apparatus including a rotatable table configured to receive a polish pad having a polish surface; a polish head configured to hold a polish object and configured to be capable of placing the polish object in contact with the polish surface while holding the polish object; at least one contact portion being provided with a contact surface and configured to be capable of contacting the polish surface when the table is in rotation; and a measurement portion configured to measure a state of the contact surface of the contact portion being configured to contact the polish surface of the polish pad.

Abstract: The present disclosure provides a chemical mechanical polishing (CMP) system. The CMP system includes a pad designed for wafer polishing, a motor driver coupled with the pad and designed to drive the pad during the wafer polishing, and a controller coupled with the motor driver and designed to control the motor driver. The CMP system further includes an in-situ rate monitor designed to collect polishing data from a wafer on the pad, determine CMP endpoint based on a life stage of the pad, and provide the CMP endpoint to the controller.

Abstract: Implementations and techniques for applying a film to a semiconductor wafer and for processing a semiconductor wafer are generally disclosed.

Abstract: In a method for processing a plate object, etching is performed for a flat plate object by a predetermined etching method and the shape of the plate object after the etching is grasped in advance. In a grinding step, the plate object is ground into a grinding-finished shape that is a non-flat shape obtained by inverting the shape of the plate object after the etching to the reverse shape. When subsequent etching by the predetermined etching method is performed for a grinding-target surface, the plate object is formed into a flat shape with a uniform thickness.

Abstract: Provided are fine abrasive particles which have a high rate of polishing and generate few polishing flaws. A process for producing then abrasive particles is also provided in which the fine abrasive particles have a reduced coefficient of fluctuation in particle diameter, the production steps are simple, and the production cost is low. The fine abrasive particles comprise cerium oxide, at least one element selected from La, Pr, Nd, Sm, and Eu, and one or more element selected from Y, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu, and are characterized in that the cerium oxide has a Ce content of 20 mol % or higher and that the sum (mol %) of the content of the at least one element selected from La, Pr, Nd, Sm, Nd Eu and the content of Ce in the cerium oxide is greater than the sum (mol %) of the contents of the one or more elements selected from Y, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu.

Abstract: A composition and associated method for chemical mechanical planarization (or other polishing) are described. The composition contains an abrasive, benzenesulfonic acid compound, a per-compound oxidizing agent, and water. The composition affords tunability of removal rates for metal, barrier layer materials, and dielectric layer materials in metal CMP processes. The composition is particularly useful in conjunction with the associated method for metal CMP applications (e.g., step 2 copper CMP processes).