Abstract: Disclosed are a polishing composition and method of polishing a substrate. The composition has low-load (e.g., up to about 0.1 wt. %) of abrasive particles. The polishing composition also contains water and at least one anionic surfactant. In some embodiments, the abrasive particles are alpha alumina particles (e.g., coated with organic polymer). The polishing composition can be used, e.g., to polish a substrate of weak strength such as an organic polymer. An agent for oxidizing at least one of silicon and organic polymer is included in the composition in some embodiments.

Abstract: A method and associated composition for CMP processing of noble metal-containing substrates (such as ruthenium-containing substrates) afford both high removal rates of the noble metal and are tunable with respect to rate of noble metal removal in relation to removal of other films. Low levels of an oxidizing agent containing one or more peroxy-functional group(s) can be used along with a novel ligand to effectively polish noble metal substrates.

Abstract: A substrate processing method for removing an Si-based film on a surface of a substrate accommodated in a processing chamber includes a first step in which the Si-based film on the surface of the substrate is transformed into a reaction product by a gas containing a halogen element and an alkaline gas in the processing chamber and a second step in which the reaction product is vaporized in the processing chamber which is depressurized to a pressure lower than a pressure during the first step. The first step and the second step are repeated two or more times.

Abstract: In a semiconductor device including a transistor in which an oxide semiconductor layer, a gate insulating layer, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor layer and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive layer and an interlayer insulating layer are stacked to cover the oxide semiconductor layer, the sidewall insulating layers, and the gate electrode layer. Then, parts of the interlayer insulating layer and the conductive layer over the gate electrode layer are removed by a chemical mechanical polishing method, so that a source electrode layer and a drain electrode layer are formed. Before formation of the gate insulating layer, cleaning treatment is performed on the oxide semiconductor layer.

Abstract: A method of forming a forming a semiconductor device comprises forming at least one semiconductor device structure over a surface of a wafer. An opposing surface of the wafer is subjected to at least one chemical-mechanical polishing process to form a modified opposing surface of the wafer comprising at least one recessed region and at least one elevated region. Additional methods of forming a semiconductor device, and methods of reducing stress on a wafer are also described.

Abstract: It is an object of the present invention to provide a method for manufacturing an SOI substrate having an SOI layer that can be used in practical applications with high yield even when a flexible substrate such as a glass substrate or a plastic substrate is used. Further, it is another object of the present invention to provide a method for manufacturing a thin semiconductor device using such an SOI substrate with high yield. When a single-crystal semiconductor substrate is bonded to a flexible substrate having an insulating surface and the single-crystal semiconductor substrate is separated to manufacture an SOI substrate, one or both of bonding surfaces are activated, and then the flexible substrate having an insulating surface and the single-crystal semiconductor substrate are attached to each other.

Abstract: Various embodiments of a semiconductor processing fluid delivery system and a method delivering a semiconductor processing fluid are provided. In aspect, a system for delivering a liquid for performing a process is provided that includes a first flow controller that has a first fluid input coupled to a first source of fluid and a second flow controller that has a second fluid input coupled to a second source of fluid. A controller is provided for generating an output signal to and thereby controlling discharges from the first and second flow controllers. A variable resistor is coupled between an output of the controller and an input of the second flow controller whereby the output signal of the controller and the resistance of the variable resistor may be selected to selectively control discharge of fluid from the first and second flow controllers.

Abstract: A method for manufacturing semiconductor device includes preparing a structure including a substrate, an insulating layer on the substrate and having a recess, a barrier film on the insulating layer, and a copper film on the barrier such that the copper film is filling the recess with the barrier between the insulating layer and copper film, removing the copper film down to interface with the barrier such that copper wiring is formed in the recess, etching the wiring such that surface of the wiring is recessed from surface of the insulating layer, and removing the barrier from the surface of the insulating layer such that the surface of the insulating layer is exposed. The etching includes positioning the structure removed down to the barrier in organic compound atmosphere having vacuum state, and irradiating oxygen gas cluster ion beam on the surface of the wiring to anisotropically etch the wiring.

Abstract: Native oxides and associated residue are removed from surfaces of a substrate by sequentially performing two plasma cleaning processes on the substrate in a single processing chamber. The first plasma cleaning process removes native oxide formed on a substrate surface by generating a cleaning plasma from a mixture of ammonia (NH3) and nitrogen trifluoride (NF3) gases, condensing products of the cleaning plasma on the native oxide to form a thin film that contains ammonium hexafluorosilicate ((NH4)2SiF6), and subliming the thin film off of the substrate surface. The second plasma cleaning process removes remaining residues of the thin film by generating a second cleaning plasma from nitrogen trifluoride gas. Products of the second cleaning plasma react with a few angstroms of the bare silicon present on the surface, forming silicon tetrafluoride (SiF4) and lifting off residues of the thin film.

Abstract: A method of configuring a polishing monitoring system includes receiving user input selecting a plurality of libraries, each library of the plurality of libraries comprising a plurality of reference spectra for use in matching to measured spectra during polishing, each reference spectrum of the plurality of reference spectra having an associated index value, for a first zone of a substrate, receiving user input selecting a first subset of the plurality of libraries, and for a second zone of the substrate, receiving user input selecting a second subset of the plurality of libraries.

Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.

Abstract: Material test structures having cantilever portions and methods of forming the same are described herein. As an example, a method of forming a material test structure includes forming a number of electrode portions in a first dielectric material, forming a second dielectric material on the first dielectric material, wherein the second dielectric material includes a first cantilever portion and a second cantilever portion, and forming a test material on the number of electrode portions, the first dielectric material, and the second dielectric material.

Abstract: Embodiments of mechanisms for cleaning a surface of a semiconductor wafer for a hybrid bonding are provided. The method for cleaning a surface of a semiconductor wafer for a hybrid bonding includes providing a semiconductor wafer, and the semiconductor wafer has a conductive pad embedded in an insulating layer. The method also includes performing a plasma process to a surface of the semiconductor wafer, and metal oxide is formed on a surface of the conductive structure. The method further includes performing a cleaning process using a cleaning solution to perform a reduction reaction with the metal oxide, such that metal-hydrogen bonds are formed on the surface of the conductive structure. The method further includes transferring the semiconductor wafer to a bonding chamber under vacuum for hybrid bonding. Embodiments of mechanisms for a hybrid bonding and a integrated system are also provided.

Abstract: A method for creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness includes: measuring a thickness of a semiconductor-on-insulator (SOI) layer at a plurality of locations; determining a removal thickness at each of the plurality of locations; and implanting ions at the plurality of locations. The implanting is dynamically based on the removal thickness at each of the plurality of locations. The method further includes oxidizing the SOI layer to form an oxide layer, and removing the oxide layer.

Abstract: The present disclosure relates to a bump processing method and/or resulting MEMS-CMOS structure, in which one or more anti-stiction bumps are formed within a substrate prior to the formation of a cavity in which the one or more anti-stiction bumps reside. By forming the one or more anti-stiction bumps prior to a cavity, the sidewall angle and the top critical dimension (i.e., surface area) of the one or more anti-stiction bumps are reduced. The reduction in sidewall angle and critical dimension reduces stiction between a substrate and a moveable part of a MEMS device. By reducing the size of the anti-stiction bumps through a processing sequence change, lithographic problems such as reduction of the lithographic processing window and bump photoresist collapse are avoided.

Abstract: According to one embodiment, a planarizing method is proposed. In the planarizing method, a surface to be processed of an object to be processed including a silicon oxide film is planarized in a processing solution by bringing the surface to be processed into contact with or close proximity with the surface of a solid-state plate on which fluorine is adsorbed. The bonding energy between fluorine and the solid-state plate is lower than that between fluorine and silicon.

Abstract: Provided is a method for treating a group III nitride substrate capable of obtaining, in the case where a group III nitride layer is laminated thereon, a group III nitride substrate that can form an electronic device having excellent characteristics. The method for treating a group III nitride substrate includes the steps of CMPing a surface of a substrate, elevating a temperature of the group III nitride substrate after the CMP process to a predetermined annealing temperature under a nitrogen gas atmosphere, and holding the group III nitride substrate whose temperature has been elevated to the annealing temperature for four minutes or more and eight minutes or less in a first mixed atmosphere of a hydrogen gas and a nitrogen gas or a second mixed atmosphere of a hydrogen gas and an ammonia gas.

Abstract: The present invention relates to a method of measuring surface properties of a polishing pad which measures surface properties such as surface topography or surface condition of a polishing pad used for polishing a substrate such as a semiconductor wafer. The method of measuring surface properties of a polishing pad includes applying a laser beam to the polishing pad, detecting scattered light that is reflected and scattered by the polishing pad with a photodetector and performing an optical Fourier transform on the detected scattered light to produce an intensity distribution corresponding to a spatial wavelength spectrum based on surface topography of the polishing pad, and calculating a numerical value representing surface properties of the polishing pad based on the intensity distribution corresponding to two different prescribed spatial wavelength ranges.

Abstract: Disclosed is a method for polishing a silicon wafer, wherein a surface to be polished of a silicon wafer is rough polished, while supplying a polishing liquid, which is obtained by adding a water-soluble polymer to an aqueous alkaline solution that contains no free abrasive grains, to a polishing cloth. Consequently, the surface to be polished can be polished at high polishing rate and the flatness of the edge portion including roll-off and roll-up can be controlled.

Abstract: A polishing composition for a silicon wafer includes a macromolecular compound, an abrasive, and an aqueous medium. The macromolecular compound includes a constitutional unit (a1) represented by the following general formula (1), a constitutional unit (a2) represented by the following general formula (2), and a constitutional unit (a3) represented by the following general formula (3). The total of the constitutional unit (a3) is 0.001 to 1.5 mol % of all the constitutional units of the macromolecular compound.

Abstract: Wire-bonded semiconductor structures using organic insulating material and methods of manufacture are disclosed. The method includes forming a metal wiring layer in an organic insulator layer. The method further includes forming a protective layer over the organic insulator layer. The method further includes forming a via in the organic insulator layer over the metal wiring layer. The method further includes depositing a metal layer in the via and on the protective layer. The method further includes patterning the metal layer with an etch chemistry that is damaging to the organic insulator layer.

Abstract: A chemical mechanical polishing (CMP) composition comprising a specific heteropolyacid Abstract A chemical-mechanical polishing (CMP) composition comprising: (A) inorganic particles, organic particles, or a mixture thereof, (B) a heteropolyacid of the formula HaXbPsMOyVzOc wherein X=any cation other than H 8<y<18 8<z<14 56<c<105 a+b=2c?6y?5(3+z) b>0 and a>0 (formula I) or a salt thereof, and, (C) an aqueous medium.

Abstract: A sapphire pad conditioner includes a sapphire substrate having multiple protrusions on a surface and a holder arranged to hold the sapphire substrate. The sapphire substrate is used for conditioning a chemical mechanical planarization (CMP) pad.

Abstract: The present invention includes methods and materials for cleaning materials, particles, or chemicals from a substrate with a brush or pad. The method comprising: engaging a surface of a rotating wafer with an outer circumferential surface of a rotating cylindrical foam roller, the cylindrical foam roller having a plurality of circumferentially and outwardly extending spaced apart nodules extending from the outer surface, each nodule defining a height extending from the outer surface of the cylindrical foam roller to a substrate engagement surface of the nodule, the substrate engagement surface of one or more of the nodules having a rounded configuration; and positioning the cylindrical foam roller on the substrate such that the one or more nodules are positioned to have only the rounded substrate engagement surface contact the substrate such that no linear surface of the one or more nodules contacts the substrate.

Abstract: A method for fabricating an integrated circuit includes the following steps of: providing a substrate with at least one isolation structure formed therein so as to separate the substrate into a first active region with a first stacked structure formed thereon and a second active region with a second stacked structure formed thereon; forming an interlayer dielectric layer covering the first stacked structure and the second stacked structure; and planarizing the interlayer dielectric layer to expose the top surface of the first stacked structure, wherein the second stacked structure is still covered by the interlayer dielectric layer after planarizing.

Abstract: A method of polishing copper wiring surfaces of in ultra large scale integrated circuit, the method including: a) preparing a polishing solution including between 35 and 80 w. % of a nano SiO2 abrasive, between 12 and 60 w. % of deionized water, between 1 and 3 w. % of an oxidant, between 1 and 4 w. % of an active agent, and between 0.5 and 1.5 w. % of a chelating agent; and b) polishing using the polishing solution under following conditions: between 2 and 5 kPa pressure; between 20 and 50° C.; between 120 and 250 mL/min slurry flow rate; and at between 30 and 60 rpm/min rotational speed.

Abstract: A chip includes a number a plurality of functional areas of a layer and a number of dummy structures within the layer. The dummy structures are spaced from the functional areas. Each dummy structure has a size that is a function of the size and density of the functional areas.

Abstract: An etchant composition includes about 25 percent by weight to about 35 percent by weight of phosphoric acid, about 3 percent by weight to about 9 percent by weight of nitric acid, about 10 percent by weight to about 20 percent by weight of acetic acid, about 5 percent by weight to about 10 percent by weight of a nitrate, about 6 percent by weight to about 15 percent by weight of a sulfonic acid, about 1 percent by weight to about 5 percent by weight of an amine compound including a carboxyl group, about 0.1 percent by weight to about 1 percent by weight of a water-soluble amino acid, about 0.01 percent by weight to about 1 percent by weight of an azole compound, and water.

Abstract: A method and apparatus for simultaneously removing conductive materials from a microelectronic substrate. A method in accordance with one embodiment of the invention includes contacting a surface of a microelectronic substrate with an electrolytic liquid, the microelectronic substrate having first and second different conductive materials. The method can further include controlling a difference between a first open circuit potential of the first conducive material and a second open circuit potential of the second conductive material by selecting a pH of the electrolytic liquid. The method can further include simultaneously removing at least portions of the first and second conductive materials by passing a varying electrical signal through the electrolytic liquid and the conductive materials. Accordingly, the effects of galvanic interactions between the two conductive materials can be reduced and/or eliminated.

Abstract: When forming high-k metal gate electrode structures in an early manufacturing stage, integrity of an encapsulation and, thus, integrity of sensitive gate materials may be improved by reducing the surface topography of the isolation regions. To this end, a dielectric cap layer of superior etch resistivity is provided in combination with the conventional silicon dioxide material.

Abstract: Greater planarity is achieved between surfaces of a conductive structure and a layer within which the conductive structure resides. A portion of the conductive structure protruding above the surface of the layer is selectively oxidized, at least in part, to form an oxidized portion. The oxidized portion is then removed, at least partially, to facilitate achieving greater planarity. The protruding portions may optionally be formed by selectively disposing conductive material over the conductive structure, when that the conductive structure is initially recessed below the surface of the layer. A further embodiment includes selectively oxidizing a portion of the conductive structure below the surface of the layer, removing at least some of the oxidized portion so that an upper surface of the conductive structure is below the upper surface of the layer, and planarizing the upper surface of the layer to the upper surface of the conductive structure.

Abstract: A polishing method and a polishing apparatus finish a surface of a substrate of a compound semiconductor containing an element such as Ga or the like to a desired level of flatness, so that the surface can be flattened with high surface accuracy within a practical processing time. In the presence of water, such as weak acid water, water with air dissolved therein, or electrolytic ion water, the surface of the substrate made of a compound semiconductor containing either one of Ga, Al, and In and a surface of a polishing pad having an electrically conductive member in an area of the surface which is held in contact with the substrate) are relatively moved while being held in contact with each other, thereby polishing the surface of the substrate.

Abstract: A method and associated composition for CMP processing of noble metal-containing substrates (such as ruthenium-containing substrates) afford both high removal rates of the noble metal and are tunable with respect to rate of noble metal removal in relation to removal of other films. Low levels of an oxidizing agent containing one or more peroxy-functional group(s) can be used along with a novel ligand to effectively polish noble metal substrates.

Abstract: A polishing method of a semiconductor device is disclosed. A substrate having a first side and a second side opposite to the first side is provided. The substrate has a device layer formed on the first side and a plurality of trench isolation structures therein extending from the first side to the second side. A main polishing step is performed to the second side of the substrate until a surface of at least one of the trench isolation structures is exposed. An auxiliary polishing step is then performed to the second side of the substrate. Besides, a silicon-to-oxide selectivity of the main polishing step is different from a silicon-to-oxide selectivity of the auxiliary step.

Abstract: The CMP polishing liquid of the present invention contains 1,2,4-triazole, a phosphoric acid, an oxidant, and abrasive particles. The polishing method of the present invention is a substrate polishing method for polishing a substrate with a polishing cloth while supplying a CMP polishing liquid between the substrate and the polishing cloth, in which the substrate is a substrate having a palladium layer, and the CMP polishing liquid is a CMP polishing liquid containing 1,2,4-triazole, a phosphoric acid, an oxidant, and abrasive particles.

Abstract: Provided are a metal-polishing liquid that comprises an oxidizing agent, an oxidized-metal etchant, a protective film-forming agent, a dissolution promoter for the protective film-forming agent, and water; a method for producing it; and a polishing method of using it. Also provided are materials for the metal-polishing liquid, which include an oxidized-metal etchant, a protective film-forming agent, and a dissolution promoter for the protective film-forming agent.

Abstract: A semiconductor device includes: a substrate; a transistor that has a ring-shaped gate electrode formed on the substrate; a plurality of external dummy electrodes that are arranged outside the gate electrode and are formed in the same layer as the gate electrode; and at least one internal dummy electrode that is arranged inside the gate electrode and is formed in the same layer as the gate electrode.

Abstract: A CMP polishing slurry of the present invention contains cerium oxide particles, water, and a polymer of at least one of a methacrylic acid and the salt thereof, and/or a polymer of at least one of a methacrylic acid and the salt thereof and a monomer having an unsaturated double bond, preferably contains furthermore a dispersant or a polymer of monomers containing at least one of an acrylic acid and the salt thereof. The present invention provides a CMP polishing slurry and a polishing method that, after polishing, give a polished film having a smaller difference in residual film thickness due to a pattern density difference.

Abstract: Provided are a polishing slurry for metal films and a polishing method which restrain the generation of erosion and seams, and makes the flatness of a surface polished therewith or thereby high. The slurry and the method are a polishing slurry, for metal films, comprising abrasive grains, a methacrylic acid based polymer and water, and a polishing method using the slurry, respectively.

Abstract: An approach for polishing-based hard mask removal during FinFET device formation is provided. In a typical embodiment, an initial device will be provided with a set of fins (e.g., silicon (Si)), a set of fin caps (e.g., silicon nitride (SiN)), and an oxide layer. A post-oxide planarizing and thinning polishing will first be performed (e.g., using a Silica-based slurry) to thin/reduce the oxide layer. A stop-on-nitride polishing will then be performed (e.g., using a Ceria-based slurry) to reduce the oxide layer to a top surface of the fin caps. Still yet, a stop-on-silicon polishing will be performed (e.g., using a Ceria-based slurry) to remove the set of fin caps and to reduce the oxide layer to a top surface to the set of fins.

Abstract: A polishing composition of the present invention is to be used for polishing an object including a portion containing a group III-V compound material. The polishing composition contains an oxidizing agent and an anticorrosive agent. The anticorrosive agent is preferably a nitrogen-containing organic compound, such as 1H-1,2,4-triazole and benzotriazole, or an organic compound having a carboxyl group, for example, dicarboxylic acid, such as malonic acid, succinic acid, glutaric acid, adipic acid, pimelic acid, maleic acid, phthalic acid, malic acid, and tartaric acid, or tricarboxylic acid, such as citric acid.

Abstract: The present disclosure pertains to a method of forming a spacer patterning mask. The method entails: providing a substrate; depositing, on the substrate, an interface layer, a core film and a first hard mask; patterning the core film and the first hard mask to form strips; depositing a spacer patterning layer to cover the core film and the first hard mask in the intermediate pattern; planarizing the spacer patterning layer by using the first hard mask in the intermediate pattern as a stop layer; etching the planarized spacer patterning layer; dry etching the second hard mask to expose the partially-etched spacer patterning layer; dry etching the exposed spacer patterning layer to form a spacer pattern; and removing the remaining first hard mask and second hard mask and the core film to obtain the final spacer patterning mask.

Abstract: A method for polishing Through-Silicon Via (TSV) wafers is provided. The method comprises a step of subjecting the surface of a TSV wafer to a polishing treatment with a polishing composition containing an organic alkaline compound, an oxidizing agent selected from sodium chlorite and/or potassium bromate, silicon oxide abrasive particles, and a solvent to simultaneously remove Si and conductive materials at their respective removal rates. By using the method of this invention, Si and conductive materials can be simultaneously polished at higher removal rates to significantly save the necessary working-hour costs for polishing TSV wafers. A polishing composition used in the above method is also provided.

Abstract: The present invention provides a method for manufacturing a semiconductor structure, comprising: forming a first contact layer on an exposed active region of a first spacer; forming a second spacer at a region of the first contact layer close to a gate stack to partially cover the exposed active region; forming a second contact layer in the uncovered exposed active region, wherein when a diffusion coefficient of the first contact layer is the same as that of the second contact layer, the first contact layer has a thickness less than that of the second contact layer; and when the diffusion coefficient of the first contact layer is different from that of the second contact layer, the diffusion coefficient of the first contact layer is smaller than that of the second contact layer. Correspondingly, the present invention also provides a semiconductor structure.

Abstract: Greater planarity is achieved between surfaces of a conductive structure and a layer within which the conductive structure resides. A portion of the conductive structure protruding above the surface of the layer is selectively oxidized, at least in part, to form an oxidized portion. The oxidized portion is then removed, at least partially, to facilitate achieving greater planarity. The protruding portions may optionally be formed by selectively disposing conductive material over the conductive structure, when that the conductive structure is initially recessed below the surface of the layer. A further embodiment includes selectively oxidizing a portion of the conductive structure below the surface of the layer, removing at least some of the oxidized portion so that an upper surface of the conductive structure is below the upper surface of the layer, and planarizing the upper surface of the layer to the upper surface of the conductive structure.

Abstract: The CMP polishing liquid containing a medium and silica particles as an abrasive grain dispersed into the medium. The silica particles have a silanol group density of 5.0/nm2 or less and the biaxial average primary particle diameter when arbitrary 20 silica particles are selected from an image obtained by scanning electron microscope observation is 25 to 55 nm. The association degree of the silica particles is 1.1 or more. The CMP polishing liquid has the high barrier film polishing speed, the favorable abrasive grain dispersion stability, and the high interlayer dielectric polishing speed. The CMP polishing liquid can provide a method of producing semiconductor substrates or the like, that have excellent microfabrication, thin film formation, dimension accuracy, electric property and high reliability with low cost.

Abstract: The invention provides a polishing composition comprising (a) silica, (b) one or more compounds that increases the removal rate of silicon, (c) one or more tetraalkylammonium salts, and (d) water, wherein the polishing composition has a pH of about 7 to about 11. The invention further provides a method of polishing a substrate with the polishing composition.

Abstract: In accordance with an embodiment of the present invention, a method of polishing a device includes providing a layer having a non-uniform top surface. The non-uniform top surface includes a plurality of protrusions. The method further includes removing the plurality of protrusions by exposing the layer to a fluid that has gas bubbles and a liquid.

Abstract: This invention is to provide a method of polishing a silicon wafer wherein a high flatness can be attained likewise the conventional polishing method and further the occurrence of defects due to the remaining of substances included in the polishing solution on the surface of the wafer can be suppressed as well as a polished silicon wafer. The method of polishing a silicon wafer by supplying a polishing solution containing abrasive grains onto a surface of a polishing pad and then relatively sliding the polishing pad to a silicon wafer to polish the surface of the silicon wafer, is characterized in that the number of abrasive grains included in the polishing solution is controlled to not more than 5×1013 grains/cm3.

Abstract: The object of the present invention is to embed an insulating film in a hole having a high aspect ratio and a small width without the occurrence of a void. The thickness of a polishing stopper layer is reduced by making separate layers respectively serve as a mask during forming the hole in a semiconductor substrate, and a stopper during removing the insulating film filled in the hole.