Optical Characteristic Sensed Patents (Class 438/7)
  • Patent number: 10192793
    Abstract: According to one embodiment, a pattern formation method includes correcting, based on a relationship between a residual film thickness of an imprint pattern and a dimension of an etching pattern that is formed using an imprint pattern as a mask, the residual film thickness of the imprint pattern; and using the imprint pattern with the corrected residual film thickness as a mask to form an etching pattern with the corrected dimension.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: January 29, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Yusaku Izawa
  • Patent number: 10115925
    Abstract: The present invention relates to an organic optoelectronic device and a display apparatus comprising same, the organic optoelectronic device comprising: an anode and a cathode facing each other; a light-emitting layer located between the anode and cathode; a hole transport layer located between the anode and light-emitting layer; an auxiliary hole transport layer located between the hole transport layer and light-emitting layer; an electron transport layer located between the cathode and light-emitting layer; and an auxiliary electron transport layer between the electron transport layer and light-emitting layer, wherein the auxiliary electron transport layer comprises at least one type of a first compound expressed by a particular Chemical Formula, and the auxiliary hole transport layer comprises at least one type of a second compound expressed by a particular Chemical Formula.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: October 30, 2018
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Jae-Han Park, Young-Kwon Kim, Jin-Hyun Lui, Eun-Sun Yu, Han-Ill Lee, Ho-Kuk Jung
  • Patent number: 10068903
    Abstract: Methods and apparatus for artificial exciton devices. An artificial exciton device includes a semiconductor substrate; at least one well region doped to a first conductivity type in a portion of the semiconductor substrate; a channel region in a central portion of the well region; a cathode region in the well region doped to a second conductivity type; an anode region in the well region doped to the first conductivity type; a first lightly doped drain region disposed between the cathode region and the channel region doped to the first conductivity type; a second lightly doped drain region disposed between the anode region and the channel region doped to the second conductivity type; and a gate structure overlying the channel region, the gate structure comprising a gate dielectric layer lying over the channel region and a gate conductor material overlying the gate dielectric. Methods are disclosed.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: September 4, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Henry Litzmann Edwards, Greg Charles Baldwin
  • Patent number: 10061211
    Abstract: A method for layoutless overlay control is provided. In some embodiments, a target layer covering a workpiece is patterned using a reticle. The patterning forms a plurality of exposure fields arranged according to a first exposure field layout. Alignment of the exposure fields relative to the workpiece is measured to generate displacement vectors. An inter-field model and an intra-field model are trained using the displacement vectors and a reference field layout. The intra-field model is transformed for use with a second exposure field layout, where the second exposure field layout is different than the first exposure field layout. Overlay corrections are generated based on the trained inter-field model and the transformed intra-field model.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: August 28, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Yao Lee, Yi-Ping Hsieh
  • Patent number: 9972704
    Abstract: A method for forming a semiconductor device comprises implanting a defined dose of protons into a semiconductor substrate and tempering the semiconductor substrate according to a defined temperature profile. At least one of the defined dose of protons and the defined temperature profile is selected depending on a carbon-related parameter indicating information on a carbon concentration within at least a part of the semiconductor substrate.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: May 15, 2018
    Assignee: Infineon Technologies AG
    Inventors: Moriz Jelinek, Johannes Georg Laven, Helmut Oefner, Hans-Joachim Schulze, Werner Schustereder
  • Patent number: 9964497
    Abstract: There is provided an inspection apparatus which inspects a substrate supporting portion configured to support a substrate during an exposure performed by an exposure apparatus. The apparatus includes: a irradiation unit configured to irradiate, with an illumination light beam, a surface of the substrate on which a pattern has been formed by an exposure by the exposure device; a detecting unit configured to detect reflected light from a pattern in the irradiated surface; a focusing state computation unit connected to the detection unit and configured to determine a focusing state of the pattern of the substrate, based on a detection result of the reflected light beam detected by the detection unit; and an inspection unit connected to the focusing state computation unit and configured to inspect the substrate supporting portion based on the focusing state determined by the focusing state computation unit.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: May 8, 2018
    Assignee: NIKON CORPORATION
    Inventor: Kazuhiko Fukazawa
  • Patent number: 9939742
    Abstract: A lithographic apparatus includes a sensor, such as an alignment sensor including a self-referencing interferometer, configured to determine the position of an alignment target including a periodic structure. An illumination optical system focuses radiation of different colors and polarizations into a spot which scans the structure. Multiple position-dependent signals are detected and processed to obtain multiple candidate position measurements. Asymmetry of the structure is calculated by comparing the multiple position-dependent signals. The asymmetry measurement is used to improve accuracy of the position read by the sensor. Additional information on asymmetry may be obtained by an asymmetry sensor receiving a share of positive and negative orders of radiation diffracted by the periodic structure to produce a measurement of asymmetry in the periodic structure.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: April 10, 2018
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Patricius Aloysius Jacobus Tinnemans, Arie Jeffrey Den Boef, Simon Gijsbert Josephus Mathijssen
  • Patent number: 9897553
    Abstract: A method and system are presented for use in optical measurements on patterned structures. The method comprises performing a number of optical measurements on a structure with a measurement spot configured to provide detection of light reflected from an illuminating spot at least partially covering at least two different regions of the structure. The measurements include detection of light reflected from said at least part of the at least two different regions comprising interference of at least two complex electric fields reflected from said at least part of the at least two different regions, and being therefore indicative of a phase response of the structure, carrying information about properties of the structure.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: February 20, 2018
    Assignee: NOVA MEASURING INSTRUMENTS LTD.
    Inventors: Gilad Barak, Dror Shafir, Yanir Hainick, Shahar Gov
  • Patent number: 9870961
    Abstract: Disclosed herein is a wafer processing method including a processed position measuring step of imaging an area including a beam plasma generated by applying a pulsed laser beam to a wafer, by using an imaging unit during the formation of a laser processed groove on the wafer, and next measuring the positional relation between the position of the beam plasma and a preset processing position. Accordingly, it is possible to check whether or not the laser processed groove is formed at a desired position, in real time during laser processing. If the position of the laser processed groove is deviated, the processed position can be immediately corrected.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: January 16, 2018
    Assignee: DISCO CORPORATION
    Inventors: Taku Iwamoto, Hironari Ohkubo, Junichi Kuki, Kentaro Odanaka
  • Patent number: 9862072
    Abstract: The invention provides a double-side polishing method including first polishing at a high polishing rate, second polishing at a low polishing rate, dividing a straight line extending between the outermost circumferences of the wafer through the center into prescribed sections, and optically measuring a cross-sectional shape of the sections; applying a weight predetermined for each section to the cross-sectional shape to quantify flatness of each section; and determining polishing conditions of the first and second polishing in subsequent polishing on a basis of the quantified flatness, wherein a beam diameter of a measurement apparatus used to measure the cross-sectional shape of outermost sections is smaller than that used to measure the cross-sectional shape of the other section. The method can measure the shape of the wafer up to its outermost circumference with high precision without reducing productivity, and improve the flatness of the entire wafer including its outermost circumference.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: January 9, 2018
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Kazumasa Asai
  • Patent number: 9853137
    Abstract: A method for forming a semiconductor device comprises implanting a defined dose of protons into a semiconductor substrate and tempering the semiconductor substrate according to a defined temperature profile. At least one of the defined dose of protons and the defined temperature profile is selected depending on a carbon-related parameter indicating information on a carbon concentration within at least a part of the semiconductor substrate.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: December 26, 2017
    Assignee: Infineon Technologies AG
    Inventors: Moriz Jelinek, Johannes Georg Laven, Helmut Oefner, Hans-Joachim Schulze, Werner Schustereder
  • Patent number: 9728627
    Abstract: A method for forming a semiconductor device comprises implanting a defined dose of protons into a semiconductor substrate and tempering the semiconductor substrate according to a defined temperature profile. At least one of the defined dose of protons and the defined temperature profile is selected depending on a carbon-related parameter indicating information on a carbon concentration within at least a part of the semiconductor substrate.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: August 8, 2017
    Assignee: Infineon Technologies AG
    Inventors: Moriz Jelinek, Johannes Georg Laven, Helmut Oefner, Hans-Joachim Schulze, Werner Schustereder
  • Patent number: 9564322
    Abstract: A method of excimer laser annealing includes generating a focused long line beam with a laser beam output from at least one laser source; and scanning the long line beam in a direction perpendicular to a long axis of the long line beam along a surface of an amorphous semiconductor film on a substrate. The long line beam has a normalized beam angular divergence half-width ?=arctan(tan ?y/sin ?) that is less than a critical value ?c, where ?y represents a beam angular divergence half-width measured along the long axis of the long line beam on the surface of the amorphous semiconductor film, ? represents a mean incidence angle of the long line beam on the surface of the amorphous semiconductor film, and ?c is approximately 30°.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: February 7, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Gyoo Wan Han, Vladimir Tokarev, Je Kil Ryu
  • Patent number: 9341962
    Abstract: In a method for patterning a workpiece provided with dies in a direct write machine, pattern data associated with a selected die, or group of dies, is transformed into adjusted circuit pattern data dependent both on the original pattern data and the transformed positions, wherein the adjusted circuit pattern data represents the circuit pattern of the plurality of dies, or group of dies, such that the adjusted circuit pattern is fitted to a plurality of sub-areas of the workpiece area, and wherein each sub-area is associated with a die, or group of dies, among the plurality of dies distributed on the workpiece. A pattern is then written on the workpiece according to the adjusted circuit pattern data.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: May 17, 2016
    Assignee: MYCRONIC AB
    Inventors: Mikael Wahlsten, Per-Erik Gustafsson
  • Patent number: 9323103
    Abstract: The liquid crystal display device (100) of the present invention includes a liquid crystal panel (10) having a plurality of pixels (P), and a backlight (20) having at least one light source (22) that emits light to the liquid crystal panel (10). Each of the plurality of pixels (P) includes four or more sub-pixels (R, G, B, Ye), and the light source unit (22) includes a red light source (22R), a green light source (22G), and a blue light source (22B). According to the present invention, a liquid crystal display device which can perform display of wide color reproduction range with low power consumption is provided.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: April 26, 2016
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tomohiko Mori, Kazunari Tomizawa, Makoto Hasegawa, Yuichi Yoshida
  • Patent number: 9318722
    Abstract: A method of efficiently manufacturing an organic light-emitting element with excellent light-emitting characteristics is provided. The method includes: preparing ink and filling an inkjet device having an ink ejection nozzle with the ink; preparing a substrate having a base layer including a first electrode; positioning the inkjet device above the substrate; and causing the inkjet device to eject a drop of the ink onto the base layer. In the preparation of the ink, a value Z denoting a reciprocal of the Ohnesorge number Oh determined by density ? (g/dm3), surface tension ? (mN/m), and viscosity ? (mPa·s) of the ink and a diameter r (mm) of the ink ejection nozzle satisfies Formula 1, in the ejection of the drop of the ink, speed V (m/s) of the ejected drop satisfies Formula 2, and the value Z and the speed V (m/s) satisfy Formula 3.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: April 19, 2016
    Assignee: JOLED INC.
    Inventors: Hirotaka Nanno, Shinichiro Ishino, Tomoki Masuda, Yuko Kawanami, Noriyuki Matsusue
  • Patent number: 9276166
    Abstract: A method for forming a light-emitting device of the present application comprises providing a wafer; forming a first plurality of light-emitting elements on the wafer; providing a first connection structure to connect each of the first plurality of light-emitting elements; and applying a current flow to one of the first plurality of light-emitting elements for testing at least one electrical property of the light-emitting element while no current flow is applied to the remaining of the first plurality of light-emitting elements.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: March 1, 2016
    Assignee: EPISTAR CORPORATION
    Inventors: Chia-Liang Hsu, Chih-Chiang Lu
  • Patent number: 9246067
    Abstract: A semiconductor light emitting device which produces mixed light of a desired emission color by a combination of a semiconductor light emitting element and a wavelength converting layer containing a fluorescent substance, and a vehicle lamp including the semiconductor light emitting device. The wavelength converting layer has different wavelength conversion characteristics respectively at its portion covering an area of relatively high current density at light emission operation of the semiconductor light emitting element and at its portion covering an area of relatively low current density so as to reduce chromaticity difference over the light extraction surface of the mixed light due to non-uniformity of current density in the light emitting layer at light emission operation.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: January 26, 2016
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventor: Yusuke Yokobayashi
  • Patent number: 9200950
    Abstract: Monitoring of a pulsed plasma is described using an optical sensor. In one example, the invention includes receiving light emitted by a pulsed plasma in a semiconductor plasma processing chamber, sampling the received light at a sampling rate higher than a pulse rate of the pulsed plasma, wherein the sampled light has a periodic amplitude waveform and the sampling rate is higher than the period of the amplitude waveform, accumulating multiple sampled waveforms to form a mean waveform, and transmitting characteristics of the mean waveform to a chamber control tool.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: December 1, 2015
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Lei Lian, Quentin Walker, Dermot Cantwell
  • Patent number: 9153502
    Abstract: A semiconductor chip testing method includes: (a) testing the electrical characteristics of each of semiconductor chips in the form of wafers or in the form of chips formed on a predetermined number of semiconductor wafers having certain relationship, and determining if the semiconductor chip is non-defective or defective; (b) calculating a percentage of semiconductor chips determined to be defective as a fraction defective for each of wafer addresses based on determination results about the semiconductor chips on the predetermined number of semiconductor wafers, the wafer addresses indicating the respective positions of the semiconductor chips on the semiconductor wafers; and (c) changing a determination result about a semiconductor chip determined to be non-defective to defective, the semiconductor chip being at a wafer address determined to have a fraction defective at a threshold or higher than the threshold.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: October 6, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takuya Hamaguchi, Tetsujiro Tsunoda, Shoko Kanazawa
  • Patent number: 9091667
    Abstract: A method of the detection of particle contamination on a semiconductor wafer is provides which includes examining an area of the semiconductor wafer by a metrology system comprising a scatterometry or ellipsometry/reflectometry tool to obtain measured metrology data, comparing the measured metrology data with reference metrology data and determining the presence of particle contamination in the examined area of the semiconductor wafer based on the comparison of the measured metrology data with the reference metrology data.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: July 28, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Adam Michal Urbanowicz, Carsten Hartig, Daniel Fischer
  • Patent number: 9082661
    Abstract: A method includes performing a semiconductor fabrication process on a plurality of substrates. The plurality of substrates are divided into a first subset and a second subset. A rework process is performed on the second subset of the plurality of substrates but not on the first subset. A respective mean value of at least one exposure parameter for a lithography process is computed for each respective one of the first and second subsets of the plurality of substrates. A scanner overlay correction and a mean correction are applied to expose a second plurality of substrates on which the rework process has been performed. The mean correction is based on the computed mean values.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: July 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Di Tsen, Shin-Rung Lu, Jong-I Mou
  • Patent number: 9070591
    Abstract: Among other things, a system and method for adjusting the intensity of a laser beam applied to a semiconductor device are provided for herein. A sensor is configured to measure the intensity of a laser beam reflected from the semiconductor device. Based upon the reflection intensity, an intensity of the laser beam that is applied to the semiconductor device is adjusted, such as to alter an annealing operation performed on the semiconductor device, for example.
    Type: Grant
    Filed: December 24, 2012
    Date of Patent: June 30, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Lee-Te Tseng, Chih-Hsien Ou, Kun-Hsiang Lin, Yi-Hann Chen, Ming-Te Chen
  • Publication number: 20150145440
    Abstract: An organic EL panel with less variation in an emission luminance thereof and a method for manufacturing a light-emitting device using the same are provided. The organic EL panel of the present invention includes: a substrate; a light-emitting section of the organic EL panel provided on the substrate; a current supply terminal provided on the substrate for supplying a current to the light-emitting section; and a current density adjusting section electrically connected to the current supply terminal in parallel to the light-emitting section and provided on the substrate. A current density of the light-emitting section is adjusted by processing of the current density adjusting section. Moreover, in the method for manufacturing a light-emitting device according to the present invention, after a light-emitting characteristic is adjusted by processing a post-processing region of the above-described organic EL panel, a light-emitting device including the processed organic EL panel is manufactured.
    Type: Application
    Filed: May 22, 2012
    Publication date: May 28, 2015
    Applicant: PIONEER CORPORATION
    Inventor: Shinichi Ishizuka
  • Publication number: 20150147827
    Abstract: Techniques herein include systems and methods that provide a spatially-controlled or pixel-based projection of light onto a substrate to tune various substrate properties. A given pixel-based image projected on to a substrate surface can be based on a substrate signature. The substrate signature can spatially represent non-uniformities across the surface of the substrate. Such non-uniformities can include energy, heat, critical dimensions, photolithographic exposure dosages, etc. Such pixel-based light projection can be used to tune various properties of substrates, including tuning of critical dimensions, heating uniformity, evaporative cooling, and generation of photo-sensitive agents. Combining such pixel-based light projection with photolithographic patterning processes and/or heating processes improves processing uniformity and decreases defectivity. Embodiments can include using a digital light processing (DLP) chip, grating light valve (GLV), or other grid-based micro projection technology.
    Type: Application
    Filed: November 26, 2014
    Publication date: May 28, 2015
    Inventors: Anton J. deVilliers, Daniel Fulford, Gerrit J. Leusink
  • Publication number: 20150147828
    Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, a fluorescent material layer and a scattering layer. The semiconductor layer has a first surface and a second surface on an opposite side to the first surface and includes a light emitting layer. The p-side electrode and the n-side electrode are provided on the semiconductor layer on a side of the second surface. The fluorescent material layer is provided on a side of the first surface and includes a plurality of fluorescent materials and a first bonding material. The first bonding material integrates the fluorescent materials. The scattering layer is provided on the fluorescent material layer and includes scattering materials and a second bonding material. The scattering materials are configured to scatter radiated light of the light emitting layer. The second bonding material integrates the scattering materials.
    Type: Application
    Filed: December 4, 2014
    Publication date: May 28, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yosuke AKIMOTO, Akihiro KOJIMA, Miyoko SHIMADA, Hideyuki TOMIZAWA, Yoshiaki SUGIZAKI, Hideto FURUYAMA
  • Publication number: 20150147826
    Abstract: An integrated system operation method is disclosed that includes the following steps: the film of a substrate is measured by a metrology apparatus to obtain a film information. The substrate is moved from the metrology apparatus to a process apparatus adjacent to the transfer apparatus. The film information is sent to the process apparatus. A film treatment is applied to the substrate in accordance with the film information.
    Type: Application
    Filed: November 27, 2013
    Publication date: May 28, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Weibo Yu, Wen-Yu Ku, Kuo-Sheng Chuang, Chin-Hsiang Lin
  • Publication number: 20150147024
    Abstract: Sacrificial optical test structures are constructed upon a wafer of pre-cleaved optical chips for testing the optical functions of the pre-cleaved optical chips. The sacrificial optical structures are disabled upon the cleaving the optical chips from the wafer and the cleaved optical chips can be used for their desired end functions. The test structures may remain on the cleaved optical chips or they may be discarded.
    Type: Application
    Filed: December 8, 2014
    Publication date: May 28, 2015
    Applicant: OCLARO TECHNOLOGY LTD
    Inventors: Neil David Whitbread, Lloyd Nicholas Langley, Andrew Cannon Carter
  • Publication number: 20150145146
    Abstract: Methods of exposing conductive vias of semiconductor devices may involve positioning a barrier material over conductive vias extending from a backside surface of a substrate to at least substantially conform to the conductive vias. A self-planarizing isolation material may be positioned on a side of the barrier material opposing the substrate. An exposed surface of the self-planarizing isolation material may be at least substantially planar. A portion of the self-planarizing isolation material, a portion of the barrier material, and a portion of at least some of the conductive vias may be removed to expose each of the conductive vias. Removal may be stopped after exposing at least one laterally extending portion of the barrier material proximate the substrate.
    Type: Application
    Filed: February 3, 2015
    Publication date: May 28, 2015
    Inventors: Hongqi Li, Anurag Jindal, Irina Vasilyeva
  • Patent number: 9040314
    Abstract: A translucent member 41 that has been trial-coated with a resin 8 for measurement of a light emission characteristic is placed on a translucent member placement portion 53, an excitation light that excites a phosphor is emitted from a light source unit 42 disposed above, the resin 8 coated on the translucent member 41 is irradiated with the excitation light from above, a deviation between a measurement result obtained by measuring the light emission characteristic of the light emitted from the resin 8, and a light emission characteristic specified in advance is obtained, and an appropriate resin coating amount of the resin to be coated on the LED element for actual production is derived on the basis of the deviation.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: May 26, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Seikou Abe, Masaru Nonomura, Kei Tsunemasa
  • Patent number: 9034665
    Abstract: Some embodiments of the present disclosure relate to a tool configuration and method for EUV patterning with a deformable reflective surface comprising a mirror or reticle. A radiation source provides EUV radiation which is reflected off the deformable reflective surface to transfer a reticle pattern to a semiconductor workpiece. A metrology tool measures a residual vector formed between a first shape of the semiconductor workpiece and a second shape of the reticle pattern. And, a topology of the deformable reflective surface is changed based upon the residual vector to minimize a total magnitude of the residual vector.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: May 19, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ching Huang, Tzu-Hsiang Chen, Chia-Hao Hsu, Chia-Chen Chen
  • Publication number: 20150132865
    Abstract: A semiconductor substrate is secured by suction to a rear face of a supporting face of a substrate supporting table. In this event, the thickness of the semiconductor substrate is made fixed by planarization on the rear face, and the rear face is forcibly brought into a state free from undulation by the suction to the supporting face, so that the rear face becomes a reference face for planarization of a front face. In this state, a tool is used to cut surface layers of Au projections and a resist mask on the front face, thereby planarizing the Au projections and the resist mask so that their surfaces become continuously flat. This can planarize the surfaces of fine bumps formed on the substrate at a low cost and a high speed in place of CMP.
    Type: Application
    Filed: January 20, 2015
    Publication date: May 14, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Masataka Mizukoshi, Yoshiharu Ishizuki, Kanae Nakagawa, Keishiro Okamoto, Kazuo Teshirogi, Taiji Sakai
  • Publication number: 20150132864
    Abstract: A method for manufacturing an electroluminescent element including: a first manufacturing step of layering on a substrate, in the following order, a first electroconductive layer, a dielectric layer in which plural contact holes are formed which pass therethrough in a direction orthogonal to the substrate, a second electroconductive layer which is electrically connected to the first electroconductive layer inside the contact holes and which fills the contact holes, a light-emitting layer, and a third electroconductive layer; a temperature distribution measurement step of applying a voltage to the first electroconductive layer and the third electroconductive layer, causing the light-emitting layer to emit light, and measuring the temperature distribution of the electroluminescent element to obtain temperature unevenness information for the electroluminescent element; and a second manufacturing step of adjusting, on the basis of the temperature unevenness information, the density of the plural contact holes tha
    Type: Application
    Filed: February 28, 2013
    Publication date: May 14, 2015
    Applicant: SHOWA DENKO K.K.
    Inventors: Masahiro Suzuki, Yusuke Yamazaki
  • Publication number: 20150125968
    Abstract: A method for improving imaging properties of an optical system and an optical system of this type having improved imaging properties are described. The optical system can have a plurality of optical elements. In some embodiments, an optical element is positioned and/or deformed by mechanical force action and by thermal action. In certain embodiments, one optical element is positioned and/or deformed by mechanical force action and another optical element is deformed by thermal action.
    Type: Application
    Filed: January 15, 2015
    Publication date: May 7, 2015
    Inventor: Olaf Conradi
  • Patent number: 9023665
    Abstract: An apparatus and method of manufacturing a light emitting diode (LED) device, and more particularly, an apparatus and method of manufacturing an LED device by dispensing a fluorescent solution prepared by mixing a fluorescent material with a liquid synthetic resin, onto an LED chip. An apparatus and method of manufacturing an LED device, whereby an appropriate amount of fluorescent solution simultaneously in consideration of several factors, such as characteristics of an LED chip and viscosity of the fluorescent solution may be dispensed onto the LED chip, is provided. An apparatus and method of manufacturing an LED device, whereby an appropriate amount of fluorescent solution may be calculated actively in consideration of viscosity of the fluorescent solution, a change in characteristics of an LED chip, or the like, and the appropriate amount of fluorescent solution may be dispensed onto the LED chip, is provided.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: May 5, 2015
    Assignee: Protec Co., Ltd.
    Inventor: Seung Min Hong
  • Patent number: 9018023
    Abstract: An efficient method of detecting defects in metal patterns on the surface of wafers. Embodiments include forming a metal pattern on each of a plurality of wafers, polishing each wafer, and analyzing the surface of the metal pattern on each polished wafer for the presence of defects in the metal pattern by analyzing an optical across-wafer endpoint signal, generated at the endpoint of polishing. Embodiments include determining the location of defects in the metal pattern by determining the position of non-uniformities in the optical-across-wafer endpoint signal.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: April 28, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Mike Schlicker
  • Publication number: 20150111313
    Abstract: Provided are a high-quality LED and LED member, and a method and a device with which it is possible to manufacture the same in large quantities and at minimal manufacturing cost. The present invention comprises a detachment/attachment unit for the LED or the LED member, a coating unit for performing automatic coating, and a drying unit. A coating is applied using the coating unit, and provisional drying is performed or hardening is accelerated using the drying device. Alternatively, coating and drying are repeated multiple times, after which drying or hardening is finally performed.
    Type: Application
    Filed: December 30, 2014
    Publication date: April 23, 2015
    Inventor: Masafumi Matsunaga
  • Publication number: 20150111312
    Abstract: Provided are a deposition data processing apparatus, an apparatus and a method for manufacturing an organic EL device, which make it possible to check deposition states of constituent layers of each of organic EL elements that are continuously formed on a substrate being conveyed. The deposition data processing apparatus includes a scanning section configured to scan at least two of a plurality of constituent layers that constitute each of the organic EL elements; and a processor configured to accumulate data of the constituent layers scanned by the scanning section at a specific position in a longitudinal direction of the substrate as data of a specific one of the organic EL elements.
    Type: Application
    Filed: March 5, 2013
    Publication date: April 23, 2015
    Applicant: NITTO DENKO CORPORATION
    Inventors: Ryohei Kakiuchi, Satoru Yamamoto, Takayoshi Yamano
  • Patent number: 9012244
    Abstract: The present disclosure relates to a method to form a plurality of openings within a substrate with a single photo exposure and a single etch process. A photoresist layer is disposed over a substrate and aligned with a photomask, wherein the photomask comprises a transparent area, a grayscale area, and an opaque area. The photomask and substrate are exposed to radiation comprising a single illumination step to form a first 3-dimensional pattern within the photoresist layer. The 3-dimensional pattern comprises a first opening comprising a first thickness formed by transmitting the radiation through the transparent area with full intensity, and a second opening comprising a second thickness formed by transmitting the radiation through the grayscale area with partial intensity. The 3-dimensional pattern is transferred to form a plurality of openings of varying depths within the substrate through a single etch step.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: April 21, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lin-Ya Huang, Chi-Sheng Juan, Chien-Lin Tseng, Chang-Sheng Tsao
  • Publication number: 20150104886
    Abstract: A semiconductor device arrangement comprising a functional circuit comprising a plurality of timing components and a reference module comprising a plurality of reference components is described. Each reference component comprises a reference timing component corresponding to a timing component of the plurality of timing components and a controllable timing component. The controllable timing component is arranged to provide a delay in dependence on an applied light stimulus. A method of analysing a performance of a functional circuit on a semiconductor device is also described. A device analysis system for analysing a functional circuit comprising a plurality of timing components is also described.
    Type: Application
    Filed: April 23, 2012
    Publication date: April 16, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Yoav Weizman, Jacob Fridburg, Shai Shperber
  • Patent number: 9005998
    Abstract: A laser annealing apparatus reduces laser annealing time and has a simple configuration. A laser annealing method is used to manufacture a display apparatus. The laser annealing apparatus includes a mounting unit, a substrate mounted on the mounting unit, first and second driving modules installed on the mounting unit and adjusting locations of first and second mark masks to be placed on a part of the substrate, first and second image modules that may obtain image data regarding the first and second mark masks to be location-adjusted by first and second driving modules, and a laser module that radiates a laser beam to the substrate and changes at least a part of an amorphous silicon layer of the substrate to crystalline silicon.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: April 14, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Cheol-Ho Park, Byung-Sul Kim, Jong-Hyun Yun, Hee-Geun Son
  • Publication number: 20150099313
    Abstract: A method for producing a plurality of optoelectronic components may include measuring at least one measurement parameter for a first optoelectronic component and a second optoelectronic component, and processing the first optoelectronic component and the second optoelectronic component taking account of the measured measurement parameter value of the first optoelectronic component and the measured measurement parameter value of the second optoelectronic component, such that the optoelectronic properties of the first optoelectronic component and the optoelectronic properties of the second optoelectronic component are changed in a different way toward at least one common predefined optoelectronic target property. The processing of at least one value of a measurement parameter of the optoelectronic properties of the first optoelectronic component or of the optoelectronic properties of the second optoelectronic component toward the optoelectronic target property is formed by means of a compensation element.
    Type: Application
    Filed: April 24, 2013
    Publication date: April 9, 2015
    Inventors: Simon Schicktanz, Daniel Steffen Setz
  • Publication number: 20150079703
    Abstract: An organic light emitting diode (OLED) display includes a substrate where a plurality of pixels are formed, a first pixel defining layer on the substrate, the first pixel defining layer dividing the plurality of pixels, a connection wire on the first pixel defining layer, the connection wire electrically connecting two adjacent pixels, and a second pixel defining layer on the first pixel defining layer, the second pixel defining layer covering the connection wire.
    Type: Application
    Filed: November 21, 2014
    Publication date: March 19, 2015
    Inventors: Guang hai JIN, Jae-Beom CHOI, Kwan-Wook JUNG, June-Woo LEE, Moo-Jin KIM, Ga-Young KIM
  • Publication number: 20150079702
    Abstract: A manufacturing method for a solar cell, wherein after a texture is formed on a principal surface of a substrate, infrared light in a predetermined wave number range is applied to a portion, on which the texture is formed, of the principal surface, a wave number at a specified transmission detection rate of the infrared light transmitted through the substrate and detected is acquired, the Tx size of the substrate is calculated on the basis of the acquired wave number using a previously obtained relationship between the wave number at the specified transmission detection rate and the Tx size, and when the calculated Tx size is within a reference value range, a collecting electrode is formed on the principal surface.
    Type: Application
    Filed: November 21, 2014
    Publication date: March 19, 2015
    Inventor: Hirotada INOUE
  • Patent number: 8980651
    Abstract: A multi-patterning method of manufacturing a patterned wafer provides test structures designed to enhance overlay error measurement sensitivity for monitoring and process control. One or more patterns are overlaid on a first pattern, each of a given pitch, with the elements interleaved. Test structure is formed with elements of the overlaid patterns spaced away from respective mid-positions more closely toward elements of the first pattern. In some embodiments, test structure elements of the second pattern are overlaid midway between mid-positions of elements of the first pattern and measured by scatterometry. In other embodiments, test structure elements of the second pattern are overlaid at a slightly different pitch than the elements of the first pattern and measured by reflectivity. Measurements are compared with library measurements to identify the error, which may be fed back to control the patterning process. The multi-patterning may be formed by LELE, LLE, LFLE, or other methods.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: March 17, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Hongyu Henry Yue, Shifang Li
  • Publication number: 20150072445
    Abstract: A lithography apparatus which performs writing on a substrate using a charged particle beam is provided. The apparatus comprises a plurality of column units each of which comprises a charged particle optical system, a plurality of stages each of which is movable while holding the substrate, and a controller. The controller moves the stages in synchronization with each other in a positional relationship corresponding to an arrangement of the column units, and performs writing on substrates held in the stages simultaneously.
    Type: Application
    Filed: September 9, 2014
    Publication date: March 12, 2015
    Inventors: Toshiro Yamanaka, Gaku Takahashi, Go Tsuchiya, Shinji Ohishi
  • Patent number: 8975094
    Abstract: A test structure and method are provided to facilitate developing or optimizing a fabrication process by determining values of one or more lithography process parameters for use in semiconductor device fabrication. The test structure is configured to facilitate determining values of the one or more fabrication process parameters, and includes a plurality of test structure components arranged on a substrate according to a test pattern. The test pattern may be based on: varying distances between the test structure components according to a first rule; varying distances between centers of the test structure components according to a second rule; and/or varying at least one dimension of the test structure components according to a third rule. The method may further include determining dimensions of one or more components of the test structure using, for example, scatterometry, and using the dimensions of the components to ascertain one or more fabrication process parameters.
    Type: Grant
    Filed: January 21, 2013
    Date of Patent: March 10, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Abner F. Bello, Shubhankar Basu
  • Publication number: 20150062891
    Abstract: A system and method of providing a deformed FAC Lens to a multi-emitter diode bar laser system comprised of a lens holder and FAC lens wherein the FAC Lens is deformed so as to offset or compensate for the inherent smile properties present in a multi-emitter diode bar.
    Type: Application
    Filed: September 3, 2014
    Publication date: March 5, 2015
    Applicant: TERADIODE, INC.
    Inventors: Michael Deutsch, Daqing Wang
  • Patent number: 8956886
    Abstract: In some embodiments, a method of controlling a photoresist trimming process in a semiconductor manufacturing process may include forming a photoresist layer atop a first surface of a substrate, wherein the photoresist layer comprises a lower layer having a first pattern to be etched into the first surface of the substrate, and an upper layer having a second pattern that is not etched into the first surface of the substrate; trimming the photoresist layer in a direction parallel to the first surface of the substrate; measuring a trim rate of the second pattern using an optical measuring tool during the trimming process; and correlating the trim rate of the second pattern to a trim rate of the first pattern to control the trim rate of the first pattern during the trimming process.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: February 17, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Samer Banna, Olivier Joubert, Lei Lian, Maxime Darnon, Nicolas Posseme, Laurent Vallier
  • Publication number: 20150044784
    Abstract: A manufacturing method for an electroluminescent element including a first manufacturing step of layering on a substrate, a first electroconductive layer, a dielectric layer in which plural contact holes are formed which penetrate therethrough, a second electroconductive layer electrically connected to the first electroconductive layer inside the contact holes and which fills the contact holes, a light-emitting layer, and a third electroconductive layer; a luminance distribution measurement step of applying a voltage to the first electroconductive layer and the third electroconductive layer of the electroluminescent element manufactured, causing the light-emitting layer to emit light, and the luminance distribution of the electroluminescent element is measured to obtain luminance unevenness information; and a second manufacturing step in which, on the basis of the luminance unevenness information, the density of the plural contact holes that penetrate the dielectric layer is adjusted to manufacture a second e
    Type: Application
    Filed: February 28, 2013
    Publication date: February 12, 2015
    Applicant: SHOWA DENKO K.K.
    Inventors: Masahiro Suzuki, Yusuke Yamazaki