Abstract: Provided is a semiconductor device that suppresses the occurrence of defects due to photocorrosion. A method for manufacturing the semiconductor device includes the steps of: forming an insulating layer with a concave portion over a substrate; forming a conductive film over the insulating film and the inside of the concave portion; polishing and removing the conductive film positioned over the insulating layer; and cleaning the insulating layer in a light-shielded state. Between the step of polishing and the step of cleaning, or after the step of cleaning, the substrate SUB is moved by detecting the presence or absence of the substrate SUB in the light-shielded state using an infrared sensor.

Abstract: A superposed wafer is separated to a processing target wafer and a supporting wafer while being heated. Then, an adhesive on a joint surface of the processing target wafer is removed by supplying an organic solvent onto the joint surface of the processing target wafer. Then, an oxide film formed on the predetermined pattern on the joint surface of the processing target wafer is removed by supplying acetic acid to the joint surface of the processing target wafer. Then, the joint surface of the processing target wafer is inspected. Then, based on an inspection result, the adhesive on the joint surface of the processing target wafer is removed and the oxide film formed on the predetermined pattern on the joint surface of the processing target wafer is removed.

Abstract: A lithography apparatus for performing pattern formation on a substrate includes a stage configured to hold the substrate and be movable, an optical system configured to irradiate the substrate with an energy beam for the pattern formation, and a controller configured to set an arrangement of first and second marks for overlay inspection, which is variable with respect to a first substrate for condition setting, and control the stage and the optical system so that first processing for forming the first mark on the first substrate without the pattern formation and second processing for forming the second mark on the first substrate with the pattern formation are performed based on the set arrangement.

Abstract: A method of manufacturing a solar cell includes a first center alignment step S10 of setting a substrate center position as a reference position for processing of an impurity implanting step S20 and a second center alignment step S30 of setting a substrate center position as a reference position for processing of an electrode forming step S40.

Abstract: There is provided a measuring apparatus including: an illuminator configured to illuminate, with an illumination light, a substrate having a pattern formed by exposure on a surface; a detector configured to detect the illumination light modulated by the pattern to output a detection signal; and a measuring unit configured to measure an exposure condition of the pattern of a desired portion by using the detection signals detected at a plurality of portions of the pattern.

Abstract: Provided is a substrate processing apparatus in which flexibility of disposing a device configured to determine a holding state of a substrate and the flexibility of timing of determining the holding state are enhanced. The substrate processing apparatus includes a light projector configured to radiate detection light toward a region where a substrate may exist when the substrate is held by a substrate holding member and a light receiver configured to receive the detection light radiated from the light projector. A light path of the detection light from the light projector toward the light receiver passes a substrate surrounding member installed around the substrate held by the substrate holding member. The detection light penetrates the substrate surrounding member and has a wavelength which does not penetrate the substrate.

Abstract: A method of detecting the circular uniformity of semiconductor circular contact holes. Several detection circuit structures are disposed on the semiconductor wafer: N-type active regions and P-type active regions; silicon dioxide layers separate the N-type active regions from the P-type active regions; the N-type active regions are formed in the P well and the P-type active regions are formed in the N well; polysilicon gates bridge the N-type active regions and the P-type active regions; gate oxide layers insulate the P-type regions and the N-type regions from the polysilicon gates, so that the P-type regions and the N-type regions are independent; the N-type active regions connect with circular contact holes while the P-type active regions and the polysilicon gates connect with oval contact holes; a electron beam scanner detects the circular uniformity of the contact holes. This invention advantageously reflects effectively and comprehensively the circular uniformity of the contact holes.

Abstract: A thin film deposition apparatus includes: a chamber; a mask stage in the chamber and configured to support a mask; a jig in the chamber and above the mask stage, the jig being configured to move in a direction of the mask stage; and a rail in the chamber and configured to support the movement of the jig. Another thin film deposition apparatus includes a chamber, a mask stage positioned within the chamber and configured to support a mask, a camera part proximate to a side of the mask stage, and a jig above the mask stage and configured to move in a direction of the mask stage and over the camera part. The jig is further configured to radiate laser beams in a downward direction from the jig to obtain first scanning data regarding the mask stage and second scanning data regarding the camera part.

Abstract: Exemplary embodiments are directed to controlling CD uniformity of a wafer by controlling trim time on temperature in a plasma processing system. The plasma processing system has a wafer support assembly including a plurality of independently controllable temperature control zones across a chuck and a controller that controls each temperature control zone. The controller receives process control and temperature data associated with at least one wafer previously processed in a plasma chamber of the plasma processing system, and critical device parameters of a current wafer to be processed in the plasma chamber. The controller calculates a target trim time and a target temperature profile of the current wafer based on the process control and temperature data, and the critical device parameters. The current wafer is trimmed during the target trim time while the temperature of each device die location is controlled based on the target temperature profile.

Abstract: The terminating layer that covers the top layer of a GaN-based semiconductor having a principal surface which is either a non-polar plane or a semi-polar plane, is removed by performing an organic solvent cleaning process step, and replaced with an organic solvent cleaned layer. Next, by irradiating the semiconductor with an ultraviolet ray, the organic solvent cleaned layer is removed to form a surface-modified layer instead. By performing these process steps, the top layer of the GaN-based semiconductor becomes the surface-modified layer and an electrical polarity is given to the surface of the GaN-based semiconductor. As a result, the hydrophilicity, hydrophobicity and wettability of the GaN-based semiconductor can be controlled.

Abstract: A method of thermally treating a wafer includes loading a wafer into a process chamber having one or more regions of uniform temperature gradient and one or more regions of non-uniform temperature gradient. A defect is detected in the wafer. The wafer is aligned to position the defect within one of the one or more regions of uniform temperature gradient. A rapid thermal process is performed on the wafer in the process chamber while the defect is positioned within one of the one or more regions of uniform temperature gradient.

Abstract: The method and apparatus to fabricate vias in the gallium nitride (“GaN”) layer of a GaN monolithic microwave integrated circuit (“MMIC”). The method and apparatus create vias in the GaN layer of a GaN MMIC through the use of controlled laser ablation and spectroscopic analysis of SiC and CVD diamond MMICs. The use of spectroscopic measurements helps to control the ablation by detecting a change in layers, including the GaN layer. The method and apparatus uses short pulse length, short wavelength, and a lower threshold intensity to remove material without undue heating or damage to the surrounding areas while retaining depth control.

Abstract: An optoelectronic device including at least one of a solar device, a semiconductor device, and an electronic device. The device includes a semiconductor unit. A plurality of metal fingers is disposed on a surface of the semiconductor unit for electrical conduction. Each of the metal fingers includes a pad area for forming an electrical contact. The optoelectronic device includes a plurality of pad areas that is available for connection to a bus bar, wherein each of the metal fingers is connected to a corresponding pad area for forming an electrical contact.

Abstract: A method of manufacturing a quantum dot layer, and a quantum dot optoelectronic device including the quantum dot layer. The method includes sequentially stacking a self-assembled monolayer, a sacrificial layer, and a quantum dot layer on a source substrate; disposing a stamp on the quantum dot layer; picking up the sacrificial layer, the quantum dot layer and the stamp; and removing the sacrificial layer from the quantum dot layer using a solution that dissolves the sacrificial layer.

Abstract: A deposition apparatus and a method for recycling a solution. The deposition apparatus includes a bath in which a solution used in a chemical bath deposition (CBD) method is filled, a tank in which the solution used in the CBD method is temporarily stored, and a filter unit for filtering the solution stored in the tank to be reused in the CBD method again. Thus, when a buffer layer is formed by the CBD method, the number of times of reusing the solution for forming the buffer layer may be increased.

Abstract: A laser annealing apparatus reduces laser annealing time and has a simple configuration. A laser annealing method is used to manufacture a display apparatus. The laser annealing apparatus includes a mounting unit, a substrate mounted on the mounting unit, first and second driving modules installed on the mounting unit and adjusting locations of first and second mark masks to be placed on a part of the substrate, first and second image modules that may obtain image data regarding the first and second mark masks to be location-adjusted by first and second driving modules, and a laser module that radiates a laser beam to the substrate and changes at least a part of an amorphous silicon layer of the substrate to crystalline silicon.

Abstract: A system and method for forming a semiconductor device is provided. The system may measure characteristics of the substrate to determine an amount of induced stress on the substrate. The measured characteristics may include warpage, reflectivity and/or crack information about the substrate. The induced stress may be determined, at least in part, based on the measured characteristics. The system may compare the induced stress on the substrate to a maximum intrinsic strength of the substrate and adjust an anneal for the substrate based on the comparison. The adjustment may reduce or limit breakage of the substrate during the anneal. The system may control at least one of a peak anneal temperature and a maximum anneal duration for an anneal unit, which may perform an anneal on the substrate. The measurements and control may be performed ex-situ or in-situ with the anneal.

Abstract: Embodiments include methods of depositing and controlling the deposition of a film in multiple stages. The disclosed deposition and deposition control methods include the optical monitoring of a deposition matrix to determine a time when at least one transition point occurs. In certain embodiments, the transition point or transition points are a stoichiometry point. Methods may also include controlling the length of time in which material is deposited during a deposition stage or controlling the amount of the first, second or subsequent materials deposited during any deposition stage in response to a determination of the time when a selected transition point occurs.

Abstract: Disclosed herein is a method of forming a stress relieved film stack, the method comprising forming a film stack on a first side of a substrate, the film stack comprising a plurality of film layers and creating a plurality of film stack openings according to a cutting pattern and along at least a portion of a buffer region. The plurality of film stack openings extend from a top surface of the film stack to the substrate. A deflection of the substrate may be determined, and the cutting pattern selected prior to creating the film stack openings based on the deflection of the substrate. The substrate may have a deflection of less than about 2 ?m after the creating the plurality of film stack openings. And at least one of the plurality of film layers may comprise one of titanium nitride, silicon carbide and silicon dioxide.

Abstract: A method for controlling semiconductor production through use of a hybrid Focus Exposure Matrix (FEM) model includes taking measurements of a set of structures formed onto a substrate. The method further includes using a FEM model to determine focus and exposure conditions used to form the structure The model was created through use of measurements of structures formed on a substrate under varying focus and exposure conditions, the measurements being taken using both an optical measurement tool and a scanning electron microscope.

Abstract: Provided is a method of manufacturing a semiconductor device, which includes the steps of: (a) preparing a processing target including a wafer (21) and a protective member (24) formed on the wafer (21); (b) measuring a thickness of the protective member (24) at a plurality of points; and (c) setting a desired value of a total thickness of the wafer (21) and the protective member (24) based on measurement results at the plurality of points to grind the wafer (21) in accordance with the desired value.

Abstract: Systems and methods for forming a time-averaged line image having a relatively high amount of intensity uniformity along its length is disclosed. The method includes forming at an image plane a line image having a first amount of intensity non-uniformity in a long-axis direction and forming a secondary image that at least partially overlaps the primary image. The method also includes scanning the secondary image over at least a portion of the primary image and in the long-axis direction according to a scan profile to form a time-average modified line image having a second amount of intensity non-uniformity in the long-axis direction that is less than the first amount. For laser annealing a semiconductor wafer, the amount of line-image overlap for adjacent scans of a wafer scan path is substantially reduced, thereby increasing wafer throughput.

Abstract: According to a sub-resolution assist feature arranging method in embodiments, it is selected which of a rule base and a model base is set for which pattern region on pattern data corresponding to a main pattern as a type of the method of arranging the sub-resolution assist feature for improving resolution of the main pattern formed on a substrate. Then, the sub-resolution assist feature by the rule base is arranged in a pattern region set as the rule base and the sub-resolution assist feature by the model base is arranged in a pattern region set as the model base.

Abstract: A method of manufacturing a white light emitting device includes dividing a phosphor sheet into phosphor film units to be applied to individual light emitting diode (LED) devices, measuring light conversion characteristics of the respective phosphor film units, classifying the phosphor film units of the phosphor sheet into a plurality of groups according to measurement results of the light conversion characteristics and combining the phosphor film units classified into the plurality of groups and an LED device having predetermined light characteristics so as to obtain target color characteristics.

Abstract: A nitride film manufacturing apparatus forms a nitride film on a substrate provided in a chamber by a plasma CVD technique. Specifically, the nitride film manufacturing apparatus includes a controller for calculating a first period for applying first high-frequency power having a relatively high frequency and a second period for applying second high-frequency power having a relatively low frequency in order to obtain desired compressive stress or tensile stress of the nitride film, based on distribution of a refractive index of the nitride film and/or distribution of a deposition rate of the nitride film, the distribution falling within a predetermined numerical range and being obtained using the first high-frequency power and/or the second high-frequency power applied independently for forming the nitride film.

Abstract: A translucent member 41 that has been trial-coated with a resin 8 for measurement of a light emission characteristic is placed on a translucent member placement portion 53, an excitation light that excites a phosphor is emitted from a light source unit 42 disposed above, the resin 8 coated on the translucent member 41 is irradiated with the excitation light from above, a deviation between a measurement result obtained by measuring the light emission characteristic of the light emitted from the resin 8, and a light emission characteristic specified in advance is obtained, and an appropriate resin coating amount of the resin to be coated on the LED element for actual production is derived on the basis of the deviation.

Abstract: A fabricating method of a customized mask includes forming first patterns in a mold structure, forming second patterns in the mold structure using initial masks, the mold structure having the first patterns formed therein, measuring overlap failure between the first patterns and the second patterns, and fabricating customized masks by compensating for pattern positions of the initial masks based on the measuring results, wherein compensating for the pattern positions of the initial masks includes shifting positions of at least some patterns of the initial masks according to shift directions and sizes of at least some of the first patterns.

Abstract: An alignment system for aligning a wafer when lithographically fabricating LEDs having an LED wavelength ?LED is disclosed. The system includes the wafer. The wafer has a roughened alignment mark with a root-mean-square (RMS) surface roughness ?S. The system has a lens configured to superimpose an image of the reticle alignment mark with an image of the roughened alignment mark. The roughened alignment marked image is formed with alignment light having a wavelength ?A that is in the range from about 2?S to about 8?S. An image sensor detects the superimposed image. An image processing unit processes the detected superimposed image to measure an alignment offset between the wafer and the reticle.

Abstract: A wafer inspection method comprises imaging a full surface of the wafer at an imaging resolution insufficient to resolve individual microstructures which are repetitively arranged on the wafer. A mask 109 is applied to the recorded image and unmasked portions 111 of the image are further processed by averaging. The unmasked portions 111 are selected such that they include memory portions of the wafer.

Abstract: The present disclosure provides a semiconductor structure including a semiconductor substrate having a device region and a dummy region adjacent the device region; a plurality of active regions in the device region; and a plurality of dummy active regions in the dummy region, where each of the active regions has a first dimension in a first direction and a second dimension in a second direction perpendicular to the first direction, and the first dimension is substantially greater than the second dimension; and each of the dummy active regions has a third dimension in the first direction and a fourth dimension in the second direction, and the third dimension is substantially greater than the fourth dimension. The plurality of dummy active regions are configured such that thermal annealing effect in the dummy region is substantially equal to that of the device region.

Abstract: A method and system for real-time, in-line calculations of opto-electronic properties and thickness of the layers of multi-layered transparent conductive oxide stacks of photovoltaic devices is provided. The method and system include taking measurements of each layer of the stack during deposition thereof. The measurements are then used to calculate the opto-electronic properties and thicknesses of the layers in real-time.

Abstract: An organic EL device (OELD) having a defective portion is irradiated with a laser beam; first luminance of light emitted from the OELD is measured after the OELD is irradiated with the laser beam, while supplying, to the OELD, a first amount of current with which the OELD in a normal state would emit light having luminance corresponding to a first grayscale level smaller than a reference level; the OELD is re-irradiated with the laser beam when the first luminance is smaller than a threshold; and second luminance of light emitted from the OELD is measured when the first luminance is greater than or equal to the threshold, while supplying, to the OELD, a second amount of current with which the OELD in the normal state would emit light having luminance corresponding to a second grayscale level greater than or equal to the reference level.

Abstract: A method of forming a pattern of doped region includes the following steps. At first, a device layout pattern including a gate layout pattern and a doped region layout pattern is provided to a computer system. Subsequently, the device layout pattern is split into a plurality of sub regions, and the sub regions have different pattern densities of the gate layout pattern. Then, at least an optical proximity correction (OPC) calculation is respectively performed on the doped region layout pattern in each of the sub regions to respectively form a corrected sub doped region layout pattern in each of the sub regions. Afterwards, the corrected sub doped region layout patterns are combined to form a corrected doped region layout pattern, and the corrected doped region layout pattern is outputted onto a mask through the computer system.

Abstract: Methods of characterizing semiconductor light-emitting devices (LEDs) based on product wafer characteristics are disclosed. The methods include measuring at least one product wafer characteristic, such curvature or device layer stress. The method also includes establishing a relationship between the at least one characteristic and the emission wavelengths of the LED dies formed from the product wafer. The relationship allows for predicting the emission wavelength of LED structures formed in the device layer of similarly formed product wafers. This in turn can be used to characterize the product wafers and in particular the LED structures formed thereon, and to perform process control in high-volume LED manufacturing.

Abstract: This method of manufacturing a silicon wafer has a step of preparing a wafer, in which a surface of the silicon wafer is surface-treated, a step of setting stress, in which the stress S (MPa) subjected on the wafer is set, a step of inspecting, in which a defect on a surface of the wafer is inspected, and a step of determining, in which the wafer is evaluated if the wafer satisfies a criterion. In this method, it is possible to manufacture a wafer with cracking resistance even if it is subjected to a millisecond annealing by the FLA annealing treatment.

Abstract: A thin film photovoltaic cell has an insulating substrate divided into a plurality of unit cells by alternately forming patterning lines in layers stacked on two faces of the insulating substrate; a rear face electrode layer, a photoelectric conversion layer, and a transparent electrode layer stacked in order on one face of the insulating substrate accordingly; and a back face electrode layer deposited on the other face of the insulating substrate. The photovoltaic cell further has a first penetrating hole penetrating the insulating substrate to electrically connect the transparent electrode layer and the back face electrode layer; a second penetrating hole penetrating the insulating substrate to electrically connect the rear face electrode layer and the back face electrode layer; and a transparent electrode layer removal portion in which the transparent electrode layer at least in a region surrounding the second penetrating hole is removed by an ultraviolet pulsed laser.

Abstract: Disclosed is a plasma doping apparatus provided with a plasma generating mechanism. The plasma generating mechanism includes a microwave generator that generates microwave for plasma excitation, a dielectric window that transmits the microwave generated by the microwave generator into a processing container, and a radial line slot antenna formed with a plurality of slots. The radial line slot antenna radiates the microwave to the dielectric window. A control unit controls the plasma doping apparatus such that a doping gas and a gas for plasma excitation are supplied into the processing container by a gas supply unit in a state where the substrate is placed on a holding unit, and then plasma is generated by the plasma generating mechanism to perform doping on the substrate such that the concentration of the dopant implanted into the substrate is less than 1×1013 atoms/cm2.

Abstract: Among other things, a system and method for adjusting the intensity of a laser beam applied to a semiconductor device are provided for herein. A sensor is configured to measure the intensity of a laser beam reflected from the semiconductor device. Based upon the reflection intensity, an intensity of the laser beam that is applied to the semiconductor device is adjusted, such as to alter an annealing operation performed on the semiconductor device, for example.

Abstract: A method according to embodiments of the invention includes providing a wafer including a semiconductor structure grown on a growth substrate, the semiconductor structure comprising a III-nitride light emitting layer sandwiched between an n-type region and a p-type region. The wafer is bonded to a second substrate. The growth substrate is removed. After bonding the wafer to the second substrate, the wafer is processed into multiple light emitting devices.

Abstract: A laser annealing device for compensating wafer heat maps and its method are disclosed. A laser annealing device comprises a pump laser source array including of a plurality of pump laser sources for irradiating a tunable mask, each pump laser source emitting pump laser, an annealing laser source for emitting annealing laser and irradiating the tunable mask, and a tunable mask for transmitting at least part of the annealing laser after being irradiated by the pump laser.

Abstract: Improved fidelity to an integrated circuit pattern design in a semiconductor structure ultimately produced is achieved by modeling material removal and deposition processes in regard to materials, reactant, feature size, feature density, process parameters and the like as well as the effects of such parameters on etch and material deposition bias due to microloading and RIE lag (including inverse RIE lag) and using the models to work backward through the intended manufacturing method steps, including hard mask pattern decomposition, to morphologically develop feature patterns for use in most or all process steps which will result in the desired feature sizes and shapes at the completion of the overall process. Modeling of processes may be simplified through use of process assist features to locally adjust rates of material deposition and removal.

Abstract: A focus through a projection lens is corrected to prevent the occurrence of a dimensional error in a pattern due to defocusing. At least one automatic focus correction mark is formed over each of chip patterns formed in a reticle used for exposure. Using one of the automatic focus correction marks located in the center portion of an actual device region, automatic correction of the focus of exposure light is performed. In this manner, a variation in the focus of the exposure light through the center portion of the projection lens, which is more likely to reach a high temperature than an end portion of the projection lens, is detected and corrected.

Abstract: An apparatus for recognizing an object may include a lens, a camera and a signal-processing unit. The lens may include two cross sections having different focal lengths. The camera may be configured to photograph the object having a first part through the lens. The first part may have a first shape. The signal-processing unit may be configured to recognize a height of the first part based on deviations of the first shape in an image obtained from the camera. Thus, the apparatus may only include the cylindrical lens interposed between the object and the camera except for the softwares for processing the signals. As a result, the apparatus may have a simple structure without a structure of a laser irradiation.

Abstract: A translucent member 41 that has been trial-coated with a resin 8 for measurement of a light emission characteristic is placed on a translucent member placement portion 53, an excitation light that excites a phosphor is emitted from a light source unit 42 disposed above, the resin 8 coated on the translucent member 41 is irradiated with the excitation light from above, a deviation between a measurement result obtained by measuring the light emission characteristic of the light emitted from the resin 8, and a light emission characteristic specified in advance is obtained, and an appropriate resin coating amount of the resin to be coated on the LED element for actual production is derived on the basis of the deviation.

Abstract: Methods of characterizing semiconductor light-emitting devices (LEDs) based on product wafer characteristics are disclosed. The methods include measuring at least one product wafer characteristic, such curvature or device layer stress. The method also includes establishing a relationship between the at least one characteristic and the emission wavelengths of the LED dies formed from the product wafer. The relationship allows for predicting the emission wavelength of LED structures formed in the device layer of similarly formed product wafers. This in turn can be used to characterize the product wafers and in particular the LED structures formed thereon, and to perform process control in high-volume LED manufacturing.

Abstract: A method of controlling processing of a substrate includes measuring a spectrum reflected from the substrate, for each partition of a plurality of partitions of the measured spectrum, computing a partition value based on the measured spectrum within the partition to generate a plurality of partition values, for each reference spectrum signature of a plurality of reference spectrum signatures, determining a membership function for each partition, for each partition, computing a membership value based on the membership function for the partition and the partition value for the partition to generate a plurality of groups of membership values with each group of the plurality of groups associated with a reference spectrum signature, selecting a best matching reference spectrum signature from the plurality of reference spectra signatures based on the plurality of groups of membership values, and determining a characterizing value associated with the best matching reference spectrum signature.

Abstract: The present disclosure relates to a method to form a plurality of openings within a substrate with a single photo exposure and a single etch process. A photoresist layer is disposed over a substrate and aligned with a photomask, wherein the photomask comprises a transparent area, a grayscale area, and an opaque area. The photomask and substrate are exposed to radiation comprising a single illumination step to form a first 3-dimensional pattern within the photoresist layer. The 3-dimensional pattern comprises a first opening comprising a first thickness formed by transmitting the radiation through the transparent area with full intensity, and a second opening comprising a second thickness formed by transmitting the radiation through the grayscale area with partial intensity. The 3-dimensional pattern is transferred to form a plurality of openings of varying depths within the substrate through a single etch step.

Abstract: A method for producing a phosphor layer-covered optical semiconductor element includes a step of opposing a phosphor layer containing a phosphor to an optical semiconductor element and an adjusting step of adjusting a color tone of light emitted from the optical semiconductor element and exited via the phosphor layer by adjusting the thickness of the phosphor layer.

Abstract: A method of detecting the circular uniformity of semiconductor circular contact holes. Several detection circuit structures are disposed on the semiconductor wafer: N-type active regions and P-type active regions; silicon dioxide layers separate the N-type active regions from the P-type active regions; the N-type active regions are formed in the P well and the P-type active regions are formed in the N well; polysilicon gates bridge the N-type active regions and the P-type active regions; gate oxide layers insulate the P-type regions and the N-type regions from the polysilicon gates, so that the P-type regions and the N-type regions are independent; the N-type active regions connect with circular contact holes while the P-type active regions and the polysilicon gates connect with oval contact holes; a electron beam scanner detects the circular uniformity of the contact holes. This invention advantageously reflects effectively and comprehensively the circular uniformity of the contact holes.

Abstract: The invention is directed towards methods and compositions for identifying the amount of hydrofluoric acid in a buffered oxide etching composition. In buffered oxide etching compositions it is very difficult to measure the amount of hydrofluoric acid because it has varying equilibriums and it is toxic so it hard to handle and sample. When used to manufacture microchips however, incorrect amounts of hydrofluoric acid will ruin those chips. The invention utilizes a unique method of spectrographically measuring the hydrofluoric acid when in contact with added chromogenic agents to obtain exact measurements that are accurate, immediate, and safe.