Plasma Etching Patents (Class 438/9)
  • Patent number: 10453696
    Abstract: The present invention provides a method and apparatus for etching a photomask substrate with enhanced process monitoring, for example, by providing for optical monitoring at certain regions of the photomask to obtain dual endpoints, e.g., etch rate or thickness loss of both a photoresist layer and an absorber layer. By monitoring transmissity of an optical beam transmitted through areas having photoresist layer and etched absorber layer at two different predetermined wavelength, dual process endpoints may be obtained by a signal optical detection.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: October 22, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Michael Grimbergen
  • Patent number: 10431436
    Abstract: A method and system are for monitoring and controlling deformation of a wafer substrate during a plasma etching of the wafer substrate. The method includes disposing a wafer substrate on a platen assembly within a process chamber so that an entire upper surface of the wafer is exposed, passing a process gas into the process chamber, applying a radio frequency bias voltage to the platen assembly, generating a plasma within the process chamber, monitoring a voltage difference between the platen assembly and the process chamber, during the etch process, and attenuating or extinguishing the plasma to prevent further etching once a threshold monitored voltage is reached.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: October 1, 2019
    Assignee: SPTS TECHNOLOGIES LIMITED
    Inventors: Huma Ashraf, Kevin Riddell, Roland Mumford, Grant Baldwin
  • Patent number: 10403814
    Abstract: A method of cleaning a substrate processing apparatus that etches a film including a metal, the method include a first cleaning step of providing a gas containing a hydrogen-containing gas, and removing a carbon-containing deposition by plasma generated from the gas containing the hydrogen-containing gas; a second cleaning step of, after the first cleaning step, providing an inert gas, and removing a metal-containing deposition by plasma generated from the inert gas; and a third cleaning step of, after the second cleaning step, providing a gas containing a fluorine-containing gas and an oxygen-containing gas, and removing a silicon-containing deposition by plasma generated from the gas containing the fluorine-containing gas and the oxygen-containing gas.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: September 3, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Takuya Kubo, Song yun Kang, Keiichi Shimoda, Tetsuya Ohishi
  • Patent number: 10197908
    Abstract: Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: February 5, 2019
    Assignee: Lam Research Corporation
    Inventors: Saravanapriyan Sriraman, Richard Wise, Harmeet Singh, Alex Paterson, Andrew D. Bailey, III, Vahid Vahedi, Richard A. Gottscho
  • Patent number: 10074550
    Abstract: A method and apparatus for determining a stability of plasma in a plasma processing apparatus for performing a plasma processing by converting into plasma a processing gas supplied into a processing container. The method includes: detecting a light emission intensity of the plasma in the processing container while the plasma is generated in the processing container; generating a first function representing a relationship between time and the light emission intensity from a detection result of the light emission intensity; differentiating the first function with time to calculate a differential value, and generating a second function from a relationship between an absolute value of the differential value and time; and integrating the second function with time to calculate an integral value, and determining a stability of the plasma based on the calculated integral value. A related apparatus is also provided.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: September 11, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Ryo Miyama, Naoto Watanabe, Koichiro Nakamura
  • Patent number: 10032681
    Abstract: Monitoring a geometric parameter value for one or more features produced on a substrate during an etch process may involve: (a) measuring optical signals produced by optical energy interacting with features being etched on the substrate; (b) providing a subset of the measured optical signals, wherein the subset is defined by a range where optical signals were determined to correlate with target geometric parameter values for features; (c) applying the subset of optical signals to a model configured to predict the target geometric parameter values from the measured optical signals; (d) determining, from the model, a current value of the target geometric parameter of the features being etched; (e) comparing the current value of the target geometric parameter of the features being etched to an etch process endpoint value for the target geometric parameter; and (f) repeating (a)-(e) until the comparing in (e) indicates that the current value of the target geometric parameter of the features being etched has reach
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: July 24, 2018
    Assignee: Lam Research Corporation
    Inventors: Andrew D. Bailey, III, Mehmet Derya Tetiker, Duncan W. Mills
  • Patent number: 9727672
    Abstract: Transport and surface chemistry of certain deposition techniques is modeled. Methods provide a model of the transport inside nanostructures as a single-particle discrete Markov chain process. This approach decouples the complexity of the surface chemistry from the transport model, thus allowing its application under general surface chemistry conditions, including atomic layer deposition (ALD) and chemical vapor deposition (CVD). Methods provide for determination of determine statistical information of the trajectory of individual molecules, such as the average interaction time or the number of wall collisions for molecules entering the nanostructures as well as to track the relative contributions to thin-film growth of different independent reaction pathways at each point of the feature.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: August 8, 2017
    Assignee: UCHICAGO ARGONNE, LLC
    Inventors: Angel Yanguas-Gil, Jeffrey W. Elam
  • Patent number: 9449850
    Abstract: Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: September 20, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Anchuan Wang, Xinglong Chen, Zihui Li, Hiroshi Hamana, Zhijun Chen, Ching-Mei Hsu, Jiayin Huang, Nitin K. Ingle, Dmitry Lubomirsky, Shankar Venkataraman, Randhir Thakur
  • Patent number: 9299614
    Abstract: Methods of and carriers for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a carrier for supporting a wafer or substrate in an etch process includes a frame having a perimeter surrounding an inner opening. The carrier also includes a tape coupled to the frame and disposed below the inner opening of the frame, the tape comprising an etch stop layer disposed above a support layer.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: March 29, 2016
    Assignee: Applied Materials, Inc.
    Inventors: James M. Holden, Brad Eaton, Aparna Iyer, Ajay Kumar
  • Patent number: 9285409
    Abstract: An apparatus for inspecting static electricity of a substrate includes a probe having substantially a same shape as a substrate to be inspected, the probe including a contact surface made of a conductive material, a wiring connected to the contact surface of the probe and delivering static electricity collected by the probe, and a measurement unit connected to the wiring, the measurement unit receiving the static electricity from the wiring and analyzing an intensity of the static electricity.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: March 15, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jeong Hyun Ahn, Kyoung Hyo Kim
  • Patent number: 9087798
    Abstract: An etching method can improve etching accuracy as well as secure selectivity when forming a dummy gate of a fin-type field effect transistor. In the etching method, the dummy gate of a fin-type field effect transistor is formed with a target object. In the etching method, a gate material deposited between multiple fins is etched by using surface wave plasma. A pressure in the etching method is 50 mTorr (6.67 Pa) or more, a frequency of a power to be applied to a mounting table configured to mount thereon the target object is in a range of 10 Hz or more to 200 Hz or less, and the power is pulse-modulated such that a duty ratio as a ratio of an ON-time to a pulse cycle is 50% or less.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: July 21, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hiroto Ohtake, Akinori Kitamura, Hironori Matsuoka, Yoko Noto
  • Patent number: 9039907
    Abstract: A method is described for improving the uniformity over a predetermined substrate area of a spectral response of photonic devices fabricated in a thin device layer. The method includes (i) establishing an initial device layer thickness map for the predetermined area, (ii) establishing a linewidth map for the predetermined area, and (iii) establishing an etch depth map for the predetermined area. The method further includes, based on the initial device layer thickness map, the linewidth map and the etch depth map, calculating an optimal device layer thickness map and a corresponding thickness correction map for the predetermined substrate area taking into account photonic device design data. Still further, the method includes performing a location specific corrective etch process in accordance with the thickness correction map.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: May 26, 2015
    Assignees: IMEC, Universiteit Gent
    Inventors: Philippe Absil, Shankar Kumar Selvaraja
  • Publication number: 20150111315
    Abstract: A method and apparatus for etching a photomask substrate with enhanced process monitoring is provided. In one embodiment, a method of determining an etching endpoint includes performing an etching process on a first tantalum containing layer through a patterned mask layer, directing a radiation source having a first wavelength from about 200 nm and about 800 nm to an area uncovered by the patterned mask layer, collecting an optical signal reflected from the area covered by the patterned mask layer, analyzing a waveform obtained the reflected optical signal reflected from the substrate from a first time point to a second time point, and determining a first endpoint of the etching process when a slope of the waveform is changed about 5 percent from the first time point to the second time point.
    Type: Application
    Filed: December 2, 2014
    Publication date: April 23, 2015
    Inventor: Michael GRIMBERGEN
  • Patent number: 9006703
    Abstract: Aspects of the present invention relate to method for reducing lateral extrusion formed in semiconductor structures and semiconductor structures formed thereof. Various embodiments include a method for reducing lateral extrusion formed in semiconductor structures. The method can include removing a portion of a first lateral extrusion in an aluminum layer of the semiconductor structure, and determining a post-removal thickness of a dielectric layer positioned adjacent the aluminum layer. The post-removal thickness may be determined subsequent to the removing of the portion of the first lateral extrusion. The method can also include determining a difference between the post-removal thickness of the dielectric layer and a pre-removal thickness of the dielectric layer.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Shawn A. Adderly, Brian M. Czabaj, Daniel A. Delibac, Jeffrey P. Gambino, Matthew D. Moon, David C. Thomas
  • Publication number: 20150099314
    Abstract: Etch rate distribution non-uniformities are predicted for a succession of hardware tilt angles of the RF source applicator relative to the workpiece, and the behavior is modeled as a non-uniformity function for each one of at least two plasma reactors. An offset ?? in tilt angle ? between the non-uniformity functions of the two plasma reactors is detected. The two reactors are then matched by performing a hardware tilt in one of them through a tilt angle equal to the offset ??.
    Type: Application
    Filed: October 28, 2013
    Publication date: April 9, 2015
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Gaurav Saraf, Xiawan Yang, Farid Abooameri, Wen Teh Chang, Anisul H. Khan, Bradley Scott Hersch
  • Publication number: 20150097276
    Abstract: An article having alternating oxide layers and nitride layers is etched by an etch process. The etch process includes providing a first gas comprising C4F6H2 in a chamber of an etch reactor, ionizing the C4F6H2 containing gas to produce a plasma comprising a plurality of ions, and etching the article using the plurality of ions.
    Type: Application
    Filed: September 19, 2014
    Publication date: April 9, 2015
    Inventors: Jong Mun Kim, Kenny L. Doan, Li Ling, Jairaj Payyapilly, Srinivas D. Nemani, Daisuke Shimizu, Yuju Huang
  • Patent number: 8999068
    Abstract: Provided is a chamber cleaning method capable of efficiently removing a CF-based shoulder deposit containing Si and Al deposited on an outer periphery of an ESC. A mixed gas of an O2 gas and a F containing gas is supplied toward an outer periphery 24a of an ESC 24 at a pressure ranging from about 400 mTorr to about 800 mTorr; plasma generated from the mixed gas is irradiated onto the outer periphery 24a of the ESC 24; an O2 single gas as a mask gas is supplied to the top surface of ESC 24 except the outer periphery 24a; and the shoulder deposit 50 adhered to the outer periphery 24a is decomposed and removed while preventing the top surface of ESC 24 except the outer periphery 24a from being exposed to a F radical.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: April 7, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Masanobu Honda, Hidetoshi Hanaoka, Taichi Hirano, Takanori Mimura, Manabu Iwata, Taketoshi Okajo
  • Publication number: 20150083328
    Abstract: There is provided a method of analyzing data obtained from an etching apparatus for micromachining a wafer using plasma. This method includes the following steps: acquiring the plasma light-emission data indicating light-emission intensities at a plurality of different wavelengths and times, the plasma light-emission data being measured under a plurality of different etching processing conditions, and being obtained at the time of the etching processing, evaluating the relationship between changes in the etching processing conditions and changes in the light-emission intensities at the plurality of different wavelengths and times with respect to the wavelengths and times of the plasma light-emission data, and identifying the wavelength and the time of the plasma light-emission data based on the evaluation result, the wavelength and the time being to be used for the adjustment of the etching processing condition.
    Type: Application
    Filed: June 13, 2014
    Publication date: March 26, 2015
    Inventors: Ryoji ASAKURA, Kenji TAMAKI, Akira KAGOSHIMA, Daisuke SHIRAISHI
  • Patent number: 8987843
    Abstract: A method and system to map density and temperature of a chip, in situ, is disclosed. The method includes measuring a propagation time that a mechanical propagation wave travels along at least one predefined path in a substrate. The method further includes calculating an average substrate density and temperature along the at least one predefined path as a function of the propagation time and distance. The method further includes determining a defect or unauthorized modification in the substrate based on the average substrate density being different than a baseline substrate density.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jerome L. Cann, David P. Vallett
  • Patent number: 8989888
    Abstract: A method for automatically detecting fault conditions and classifying the fault conditions during substrate processing is provided. The method includes collecting processing data by a set of sensors during the substrate processing. The method also includes sending the processing data to a fault detection/classification component. The method further includes performing data manipulation of the processing data by the fault detection/classification component. The method yet also includes executing a comparison between the processing data and a plurality of fault models stored within a fault library. Each fault model of the plurality of fault models represents a set of data characterizing a specific fault condition. Each fault model includes at least a fault signature, a fault boundary, and a set of principal component analysis (PCA) parameters.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: March 24, 2015
    Assignee: Lam Research Corporation
    Inventors: Gunsu Yun, Vijayakumar C. Venugopal
  • Publication number: 20150064810
    Abstract: An embodiment low contamination chamber includes a gas inlet, an adjustable top electrode, an adjustable bottom electrode, and an outlet. The chamber is configured to adjust a distance between the adjustable top and bottom electrodes in accordance with a desired density of plasma disposed between the top electrode and the bottom electrode.
    Type: Application
    Filed: August 30, 2013
    Publication date: March 5, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Yin Liu, Xin-Hua Huang, Lee-Chuan Tseng, Lan-Lin Chao
  • Publication number: 20150060859
    Abstract: In accordance with an embodiment, an evaluation sample includes a substrate and a polycrystalline film on the substrate. The polycrystalline film has crystal grains. A specific orientation plane is exposed on the surface of each crystal grain. The orientation planes exhibit random angles to the surface of the substrate.
    Type: Application
    Filed: January 6, 2014
    Publication date: March 5, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Ryota NIHEI
  • Patent number: 8945939
    Abstract: The invention is directed towards methods and compositions for identifying the amount of hydrofluoric acid in a buffered oxide etching composition. In buffered oxide etching compositions it is very difficult to measure the amount of hydrofluoric acid because it has varying equilibriums and it is toxic so it hard to handle and sample. When used to manufacture microchips however, incorrect amounts of hydrofluoric acid will ruin those chips. The invention utilizes a unique method of spectrographically measuring the hydrofluoric acid when in contact with added chromogenic agents to obtain exact measurements that are accurate, immediate, and safe.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: February 3, 2015
    Assignee: Ecolab USA Inc.
    Inventors: Amy M. Tseng, Brian V. Jenkins, Robert Mack
  • Publication number: 20150024517
    Abstract: A plasma etch tool includes a wafer chuck with a chuck base and at least one functional component layer attached to the chuck base. A perimeter of the functional component layer has a polymer material permanently attached to it that extends to within 2 millimeters of a top surface of the chuck. The top surface of the wafer chuck contacts a bottom surface of a semiconductor wafer during an etch process for forming an integrated circuit. The polymer material is protected from an etch ambient by a plasma etcher chuck band installed around the perimeter of the functional component layer, extending over a portion of the chuck base. An integrated circuit may be formed by installing the plasma etcher chuck band on the chuck of the plasma etch tool, and subsequently performing an etch process in the plasma etch tool on a semiconductor wafer containing the partially formed integrated circuit.
    Type: Application
    Filed: July 11, 2014
    Publication date: January 22, 2015
    Inventor: John Christopher SHRINER
  • Patent number: 8932874
    Abstract: The invention is directed towards methods and compositions for identifying the amount of ammonium acid in a buffered oxide etching composition. In buffered oxide etching compositions it is very difficult to measure the amount of ammonium acid because it has varying equilibriums and it is toxic so it hard to handle and sample. When used to manufacture microchips however, incorrect amounts of ammonium acid will ruin those chips. The invention utilizes a unique method of spectrographically measuring the ammonium acid when in contact with added chromogenic agents to obtain exact measurements that are accurate, immediate, and safe.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: January 13, 2015
    Assignee: Nalco Company
    Inventors: Amy M. Tseng, Brian V. Jenkins, Robert M. Mack
  • Publication number: 20150004721
    Abstract: An OES measuring unit outputs a spectroscopically measured value for each step at the end of or immediately after each step. A CD estimating unit obtains an estimated CD value for each step using a CD estimation model and a spectroscopically measured value received from an estimation model storage unit.
    Type: Application
    Filed: January 30, 2013
    Publication date: January 1, 2015
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Toshikazu Akimoto, Hiroshi Kannan
  • Publication number: 20140370625
    Abstract: A method of etching including providing a plurality of nanostructures extending away from a support, the support comprising a dielectric layer located between the plurality of nanowires, forming a patterned mask over a first portion of the plurality of nanostructures, such that a second portion of the plurality of nanostructures are exposed and are not located under the patterned mask, etching the second portion of the plurality of nanostructures to remove at least a portion of the patterned mask and the second portion of the plurality of nanostructures, monitoring at least one gaseous byproduct of the etching of the plurality of nanostructures during the etching of the plurality of nanostructures and stopping the etching on detecting that the dielectric layer is substantially removed.
    Type: Application
    Filed: June 17, 2014
    Publication date: December 18, 2014
    Inventor: Daniel Bryce Thompson
  • Patent number: 8900470
    Abstract: A method for etching a layer is provided. A substrate is provided in a chamber. An etch plasma for etching a layer on the substrate is generated. Light from a first region of the chamber is measured to provide a first signal. Light from a second region of the chamber is measured to provide a second signal. The first signal with the second signal are compared to determine an etch endpoint.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: December 2, 2014
    Assignee: Lam Research Corporation
    Inventor: Evelio Sevillano
  • Patent number: 8900899
    Abstract: Novel processing methods for production of high-refractive index contrast and low loss optical waveguides are disclosed. In one embodiment, a “channel” waveguide is produced by first depositing a lower cladding material layer with a low refractive index on a base substrate, a refractory metal layer, and a top diffusion barrier layer. Then, a trench is formed with an open surface to the refractory metal layer. The open surface is subsequently oxidized to form an oxidized refractory metal region, and the top diffusion barrier layer and the non-oxidized refractory metal region are removed. Then, a low-refractive-index top cladding layer is deposited on this waveguide structure to encapsulate the oxidized refractory metal region. In another embodiment, a “ridge” waveguide is produced by using similar process steps with an added step of depositing a high-refractive-index material layer and an optional optically-transparent layer.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: December 2, 2014
    Inventor: Payam Rabiei
  • Patent number: 8883025
    Abstract: A plasma processing apparatus includes a stock unit, a processing unit, and an alignment chamber. The stock unit supplies and collects a conveyable tray formed with a plurality of housing holes in each of which a wafer is housed. In the processing chamber, plasma processing is executed on the wafers housed in the tray supplied from the stock unit. The alignment chamber is provided with a rotating table on which the tray before being subjected to the plasma processing is set to perform positioning of the wafers on the rotating table. A housing state determination unit of a control device determines whether or not the wafer is misaligned with respect the housing hole of the tray based on a height detected by height detecting sensors.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: November 11, 2014
    Assignee: Panasonic Corporation
    Inventors: Shogo Okita, Yasuhiro Onishi
  • Publication number: 20140327003
    Abstract: A method of processing a plurality of packaged electronic chips being connected to one another in a common substrate is provided, wherein the method comprises etching the electronic chips, detecting information indicative of an at least partial removal of an indicator structure following an exposure of the indicator structure embedded within at least a part of the electronic chips and being exposed after the etching has removed chip material above the indicator structure, and adjusting the processing upon detecting the information indicative of the at least partial removal of the indicator structure.
    Type: Application
    Filed: May 3, 2013
    Publication date: November 6, 2014
    Inventors: Edward FUERGUT, Irmgard Escher-Poeppel, Manfred Engelhardt, Hans-Joerg Timme, Hannes Eder
  • Patent number: 8877079
    Abstract: The present invention relates to a method of manufacturing a semiconductor device wherein etching is performed on films on a wafer using a plasma treatment apparatus. In the manufacturing method according to the present invention, a change in the difference between the emission intensities of a first wavelength component and a second wavelength component in plasma is monitored during etching. If the amount of change in the difference per unit time exceeds a predetermined threshold a given number of times in a row, then the flow rate of oxygen introduced to the plasma treatment apparatus is increased or, if the amount of change exceeding the predetermined threshold has not been seen, then the oxygen flow rate is set back to the original value thereof. This series of actions is repeated all the time during a set period of time.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: November 4, 2014
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Yasuhiko Ueda
  • Patent number: 8852964
    Abstract: Exemplary embodiments are directed to controlling CD uniformity of a wafer by controlling trim time on temperature in a plasma processing system. The plasma processing system has a wafer support assembly including a plurality of independently controllable temperature control zones across a chuck and a controller that controls each temperature control zone. The controller receives process control and temperature data associated with at least one wafer previously processed in a plasma chamber of the plasma processing system, and critical device parameters of a current wafer to be processed in the plasma chamber. The controller calculates a target trim time and a target temperature profile of the current wafer based on the process control and temperature data, and the critical device parameters. The current wafer is trimmed during the target trim time while the temperature of each device die location is controlled based on the target temperature profile.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: October 7, 2014
    Assignee: Lam Research Corporation
    Inventors: Yoshie Kimura, Tom Kamp, Eric Pape, Rohit DeshPande, Keith Gaff, Gowri Kamarthy
  • Publication number: 20140234992
    Abstract: A plasma etching method is provided for etching a substrate corresponding to an etching object within an etching apparatus that includes a supply condition adjustment unit for adjusting a supply condition for supplying etching gas to the substrate, a temperature adjustment unit for adjusting a temperature of the substrate placed on a stage along a radial direction, and a plasma generating unit for generating plasma within a space between the supply condition adjustment unit and the stage. The plasma etching method includes a control step in which the temperature adjustment unit controls the temperature of the substrate to be uniform within a substrate plane of the substrate, and an adjustment step in which the supply condition adjustment unit adjusts a concentration distribution of active species contained in the plasma generated by the plasma generation unit within the space above the substrate.
    Type: Application
    Filed: September 25, 2012
    Publication date: August 21, 2014
    Applicant: Tokyo Electron Limited
    Inventors: Kazuhiro Kubota, Masanobu Honda, Takayuki Katsunuma
  • Patent number: 8809132
    Abstract: A capping layer may be deposited over the active channel of a thin film transistor (TFT) in order to protect the active channel from contamination. The capping layer may affect the performance of the TFT. If the capping layer contains too much hydrogen, nitrogen, or oxygen, the threshold voltage, sub threshold slope, and mobility of the TFT may be negatively impacted. By controlling the ratio of the flow rates of the nitrogen, oxygen, and hydrogen containing gases, the performance of the TFT may be optimized. Additionally, the power density, capping layer deposition pressure, and the temperature may also be controlled to optimize the TFT performance.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: August 19, 2014
    Assignee: Applied Materials, Inc.
    Inventor: Yan Ye
  • Patent number: 8778204
    Abstract: A method and apparatus for monitoring a target layer in a plasma process having a photoresist layer is provided. The method is useful in removing noise associated with the photoresist layer, and is particularly useful when signals associated with the target layer is weak, such as when detecting an endpoint for a photomask etching process.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: July 15, 2014
    Assignee: Applied Materials, Inc.
    Inventor: Michael N. Grimbergen
  • Patent number: 8722481
    Abstract: When forming high-k metal gate electrode structures in a semiconductor device on the basis of a basic transistor design, undue exposure of sensitive materials at end portions of the gate electrode structures of N-channel transistors may be avoided, for instance, prior to and upon incorporating a strain-inducing semiconductor material into the active region of P-channel transistors, thereby contributing to superior production yield for predefined transistor characteristics and performance.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: May 13, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan-Detlef Kronholz, Peter Javorka, Maciej Wiatr
  • Patent number: 8716028
    Abstract: The invention is directed towards methods and compositions for identifying the amount of hydrofluoric acid in a buffered oxide etching composition. In buffered oxide etching compositions it is very difficult to measure the amount of hydrofluoric acid because it has varying equilibriums and it is toxic so it hard to handle and sample. When used to manufacture microchips however, incorrect amounts of hydrofluoric acid will ruin those chips. The invention utilizes a unique method of spectrographically measuring the hydrofluoric acid when in contact with added chromogenic agents to obtain exact measurements that are accurate, immediate, and safe.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: May 6, 2014
    Assignee: Nalco Company
    Inventors: Amy Tseng, Brian V. Jenkins, Robert M. Mack
  • Patent number: 8716149
    Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a gate structure. An atomic layer deposition (ALD) process is performed to deposit a spacer around the gate structure. The ALD process includes alternating flowing ionized radicals of a first precursor across the semiconductor substrate and flowing a chlorosilane precursor across the semiconductor substrate to deposit the spacer.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: May 6, 2014
    Assignee: GlobalFoundries, Inc.
    Inventors: Fabian Koehler, Sergej Mutas, Dina Triyoso, Itasham Hussain
  • Publication number: 20140106476
    Abstract: A method for etching a layer is provided. A substrate is provided in a chamber. An etch plasma for etching a layer on the substrate is generated. Light from a first region of the chamber is measured to provide a first signal. Light from a second region of the chamber is measured to provide a second signal. The first signal with the second signal are compared to determine an etch endpoint.
    Type: Application
    Filed: October 17, 2012
    Publication date: April 17, 2014
    Applicant: Lam Research Corporation
    Inventor: Evelio SEVILLANO
  • Publication number: 20140106477
    Abstract: Disclosed is a method for determining an endpoint of an etch process using optical emission spectroscopy (OES) data as an input. Optical emission spectroscopy (OES) data are acquired by a spectrometer attached to a plasma etch processing tool. The acquired time-evolving spectral data are first filtered and demeaned, and thereafter transformed into transformed spectral data, or trends, using multivariate analysis such as principal components analysis, in which previously calculated principal component weights are used to accomplish the transform. A functional form incorporating multiple trends may be used to more precisely determine the endpoint of an etch process. A method for calculating principal component weights prior to actual etching, based on OES data collected from previous etch processing, is disclosed, which method facilitates rapid calculation of trends and functional forms involving multiple trends, for efficient and accurate in-line determination of etch process endpoint.
    Type: Application
    Filed: October 17, 2013
    Publication date: April 17, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Yan CHEN, Serguei Komarov, Vi Vuong
  • Patent number: 8691102
    Abstract: A method of manufacturing a plasmon generator includes the steps of: forming an etching mask on a dielectric layer; forming an accommodation part by etching the dielectric layer using the etching mask; and forming the plasmon generator to be accommodated in the accommodation part. The step of forming the etching mask includes the steps of: forming a patterned layer on an etching mask material layer, the patterned layer having a first opening that has a sidewall; forming a structure by forming an adhesion film on the sidewall, the structure having a second opening smaller than the first opening; and etching a portion of the etching mask material layer exposed from the second opening.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: April 8, 2014
    Assignee: Headway Technologies, Inc.
    Inventors: Hironori Araki, Yoshitaka Sasaki, Hiroyuki Ito, Yukinori Ikegawa, Seiichiro Tomita, Shigeki Tanemura
  • Patent number: 8685265
    Abstract: An etching apparatus includes a process unit and a control unit. Emission intensity of plasma inside the process unit is obtained by an OES detector, a nonlinear regression analysis is performed by an etching control device to determine a regression formula. The nonlinear regression analysis is performed by using the emission intensity of the plasma obtained until a first time when the emission intensity of the plasma passes a peak, and a second time to be an etching end point is calculated by using the regression formula. The etching end point is calculated as a time when the emission intensity decreases for a predetermined value from the first time. The etching apparatus finishes an etching when the process reaches the etching end point. It is thereby possible to control the etching end point with high-accuracy.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: April 1, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Yoshiyuki Nakao, Kazuo Hashimi
  • Patent number: 8680881
    Abstract: An interposer to be mounted with an integrated circuit to be a test object is provided with a switch and a probe to detect an electric current corresponding to individual terminals of the integrated circuit. A test pattern signal is then inputted to the integrated circuit through a test substrate as a switch that is connected to a power supply terminal of the integrated circuit and that is turned off. If the integrated circuit normally operates and the current values of all the terminals of the integrated circuit are within a tolerance, the power supply terminal connected to the turned-off switch is identified as a terminal that may be removed.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: March 25, 2014
    Inventors: Yutaka Uematsu, Hideki Osaka, Satoshi Nakamura, Satoshi Muraoka, Mitsuaki Katagiri, Ken Iwakura, Yukitoshi Hirose
  • Patent number: 8679922
    Abstract: The method includes a step of forming a mask having an opening, for forming an opening in multiple insulating films, above a semiconductor substrate on which a member becoming a first insulating film, a member becoming a second insulating film being different from the member becoming the first insulating film, a member becoming a third insulating film, and a member becoming a fourth insulating film being different from the member becoming the third insulating film are stacked in this order; a first step of continuously removing the member becoming the fourth insulating film and the member becoming the third insulating film at a portion corresponding to the opening of the mask; and a second step of removing the member becoming the second insulating film, after the first step, at a portion corresponding to the opening of the mask.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: March 25, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takaharu Kondo, Takashi Usui
  • Patent number: 8664040
    Abstract: A method includes performing an etching step on a package. The package includes a package component, a connector on a top surface of the package component, a die bonded to the top surface of the package component, and a molding material molded over the top surface of the package component. The molding material covers the connector, wherein a portion of the molding material covering the connector is removed by the etching step, and the connector is exposed.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: March 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Chun-Cheng Lin, Meng-Tse Chen, Ming-Da Cheng
  • Patent number: 8664060
    Abstract: A semiconductor structure and a method of fabricating the same comprising the steps of providing a substrate, forming at least one fin structure on said substrate, forming a gate covering said fin structure, forming a plurality of epitaxial structures covering said fin structures, performing a gate pullback process to reduce the critical dimension (CD) of said gate and separate said gate and said epitaxial structures, forming lightly doped drains (LDD) in said fin structures, and forming a spacer on said gate and said fin structures.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: March 4, 2014
    Assignee: United Microelectronics Corp.
    Inventors: An-Chi Liu, Chun-Hsien Lin, Yu-Cheng Tung, Chien-Ting Lin, Wen-Tai Chiang, Shih-Hung Tsai, Ssu-I Fu, Ying-Tsung Chen, Chih-Wei Chen
  • Patent number: 8647892
    Abstract: A method for process control is disclosed. The method includes performing an etching process on a semiconductor substrate forming a structure and a test structure having a pattern and a releasing mechanism coupled to the pattern; and monitoring the pattern of the test structure to determine whether the etching process is complete.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: February 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chih Liang, Wen-Chuan Tai, Chun-Ren Cheng
  • Publication number: 20140024143
    Abstract: Disclosed is an in-situ optical monitor (ISOM) system and associated method for controlling plasma etching processes during the forming of stepped structures in semiconductor manufacturing. The in-situ optical monitor (ISOM) can be optionally configured for coupling to a surface-wave plasma source (SWP), for example a radial line slotted antenna (RLSA) plasma source. A method is described to correlate the lateral recess of the steps and the etched thickness of a photoresist layer for use with the in-situ optical monitor (ISOM) during control of plasma etching processes in the forming of stepped structures.
    Type: Application
    Filed: July 18, 2013
    Publication date: January 23, 2014
    Applicant: Tokyo Electron Limited
    Inventors: Shifang LI, Junwei Bao, Hanyou Chu, Wen Jin, Ching-Ling Meng, Weiwen Xu, Ping Wang, Holger Tuitje, Mihail Mihaylov, Xinkang Tian
  • Patent number: 8633116
    Abstract: A dry etching method includes a first step and a second step. The first step includes generating a first plasma from a gas mixture, which includes an oxidation gas and a fluorine containing gas, and performing anisotropic etching with the first plasma on a silicon layer to form a recess in the silicon layer. The second step includes alternately repeating an organic film forming process whereby an organic film is deposited on the inner surface of the recess with a second plasma, and an etching process whereby the recess covered with the organic film is anisotropically etched with the first plasma. When an etching stopper layer is exposed from a part of the bottom surface of the recess formed in the first step, the first step is switched to the second step.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: January 21, 2014
    Assignee: Ulvac, Inc.
    Inventors: Manabu Yoshii, Kazuhiro Watanabe