Plural Coating Steps Patents (Class 438/702)
  • Patent number: 10410861
    Abstract: Methods for void-free material filling of fine recessed features have been disclosed in various embodiments. According to one embodiment, the method includes a) providing a substrate containing a recessed feature having an opening, a sidewall and a bottom, the sidewall including an area of retrograde profile relative to a direction extending from a top of the recessed feature to the bottom of the recessed feature, b) depositing an amount of a material in the recessed feature, the material having a greater thickness at the bottom than on the sidewall of the recessed feature, c) stopping the depositing in step b) before the recessed feature is fully filled with the material, d) etching a portion of the material from the recessed feature, and e) depositing an additional amount of the material to fully fill the recessed feature with the material without any voids in the recessed feature.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: September 10, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Kandabara N. Tapily, Gerrit J. Leusink
  • Patent number: 10354876
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate and a material layer. The substrate has a first region, and the material layer is disposed on the substrate. The material layer includes plural of first patterns and plural of second patterns arranged in an array, and two third patterns. The first patterns are disposed within the first region, the second patterns are disposed at two opposite outer sides of the first region, and the third patterns are disposed at another two opposite outer sides of the first region, wherein each of the third patterns partially merges each of a part of the first patterns and each of a part of the second patterns.
    Type: Grant
    Filed: June 24, 2018
    Date of Patent: July 16, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Yu-Cheng Tung, Fu-Che Lee, Ying-Chih Lin
  • Patent number: 10340149
    Abstract: A method of forming dense hole patterns of semiconductor devices includes: forming a plurality of first pillars on at least one lower hard mask layer disposed on a substrate; forming a spacer layer on the lower hard mask layer to form a plurality of second pillars respectively covering the first pillars, wherein a plurality of first holes are formed among the second pillars; etching the spacer layer to expose first portions of the lower hard mask layer via the first holes and expose top surfaces of the first pillars; removing the first pillars to form a plurality of second holes in the spacer layer to expose second portions of the lower hard mask layer; etching the first portions and the second portions of the lower hard mask layer at least until portions of the substrate are exposed; and removing remaining portions of the spacer layer.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: July 2, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Shing-Yih Shih, Jen-Jui Huang
  • Patent number: 10325777
    Abstract: A chemical material is deposited on a surface of a substrate. A mandrel composition is deposited on a surface of the chemical material. A mandrel hard mask pattern is deposited on a surface of the mandrel composition. The mandrel composition is etched. The mandrel hard mask pattern is removed. A plurality of spacer materials are deposited sequentially onto a surface of the chemical material and a surface of the mandrel composition. A portion of each of the plurality of spacer materials are removed sequentially. A remainder of the mandrel composition is removed. The substrate is etched. The chemical material and at least one of the spacer materials of the plurality of spacer materials are removed.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, John H. Zhang, Carl Radens
  • Patent number: 10224214
    Abstract: In order to provide a semiconductor device with high reliability while manufacturing cost is being suppressed, dry etching for an insulating film is performed by using mixed gas containing at least CF4 gas and C3H2F4 gas as its components.
    Type: Grant
    Filed: October 21, 2017
    Date of Patent: March 5, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Kotaro Horikoshi, Toshikazu Hanawa, Masatoshi Akaishi, Yuji Kikuchi
  • Patent number: 10170306
    Abstract: A method includes performing a double patterning process to form a first mandrel, a second mandrel, and a third mandrel, with the third mandrel being between the first mandrel and the second mandrel, and etching the third mandrel to cut the third mandrel into a fourth mandrel and a fifth mandrel, with an opening separating the fourth mandrel from the fifth mandrel. A spacer layer is formed on sidewalls of the first, the second, the fourth, and the fifth mandrels, wherein the opening is fully filled by the spacer layer. Horizontal portions of the spacer layer are removed, with vertical portions of the spacer layer remaining un-removed. A target layer is etched using the first, the second, the fourth, and the fifth mandrels and the vertical portions of the spacer layer as an etching mask, with trenches formed in the target layer. The trenches are filled with a filling material.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ju Lee, Hsin-Chieh Yao, Shau-Lin Shue, Tien-I Bao, Yung-Hsu Wu
  • Patent number: 10134592
    Abstract: A method is disclosed to prepare a substrate for photolithography. The method includes forming an underlayer over a surface of the substrate; depositing an interface hardmask layer on the underlayer using one of a vapor phase deposition process or an atomic layer deposition process; and forming a layer of extreme UV (EUV) resist on the interface hardmask layer, where the interface hardmask layer is comprised of material having a composition and properties tuned to achieve a certain secondary electron yield from the interface hardmask layer. Also disclosed is a structure configured for photolithography. The structure includes a substrate; an underlayer over a surface of the substrate; an interface hardmask layer disposed on the underlayer; and a layer of EUV resist disposed on the interface hardmask layer. The interface hardmask layer contains material having a composition and properties tuned to achieve a certain secondary electron yield from the interface hardmask layer.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael P Belyansky, Ravi K Bonam, Anuja Desilva, Scott Halle
  • Patent number: 10121785
    Abstract: Provided herein is a multi-channel finFET having a plurality of fins prepared by a process. The process includes forming a series of mandrels on hard mask layer which overlays a semiconductor layer. The semiconductor layer has areas of a first semiconductor material and a second semiconductor material in contact with the hard mask layer. The process includes applying a first conformal coating on the hard mask layer and the series of mandrels, to form spacer layer sacrificial fins. The process includes removing the first conformal coating from horizontal surfaces while retaining the first conformal coating on sidewalls of the series of mandrels. The process includes removing the series of mandrels and etching into a material of the hard mask layer using the spacer layer sacrificial fins as a mask.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: November 6, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sivananda K. Kanakasabapathy, Fee Li Lie, Eric Miller, Stuart A. Sieg
  • Patent number: 10068769
    Abstract: In a described example method, semiconductor wafer with a backside silicon nitride layer is encapsulated with a diffusion barrier layer prior to a high temperature anneal greater than about 1000 degrees Celsius. After the high temperature anneal the diffusion barrier layer and the backside silicon nitride layers are stripped.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: September 4, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Prakash Dalpatbhai Dev, Fuchao Wang, Nicholas Andrew Kusek
  • Patent number: 9991131
    Abstract: A double masking process is used to form semiconductor fin arrays having a controlled and variable fin pitch within different arrays. During the process, a top mandrel layer overlies a bottom mandrel layer over a semiconductor substrate. Sidewall structures formed on first mandrels within a first region of the substrate define a patterned hard mask that cooperates with a patterned photoresist layer over a second region of the substrate to form second mandrels within first and second regions of the substrate. Sidewall structures formed on the second mandrels are used as a masking layer to form a plurality of fins over the substrate.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: June 5, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Min Gyu Sung, Ruilong Xie, Chanro Park
  • Patent number: 9881794
    Abstract: In some embodiments, a method of a semiconductor process includes conformally forming a spacer layer over a plurality of mandrels that are disposed over a mask layer, portions of the spacer layer disposed over opposing sidewalls of adjacent ones of the plurality of mandrels defining trenches therebetween, filling the trenches with a dummy material, and removing first portions of the dummy material in the trenches, thereby forming a plurality of openings in the dummy material. The method further includes filling the plurality of openings with a first material, removing a remaining portion of the dummy material in the trenches, and removing the plurality of mandrels after the removing the dummy material.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: January 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yi-Nien Su
  • Patent number: 9818620
    Abstract: In order to provide a semiconductor device with high reliability while manufacturing cost is being suppressed, dry etching for an insulating film is performed by using mixed gas containing at least CF4 gas and C3H2F4 gas as its components.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: November 14, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Kotaro Horikoshi, Toshikazu Hanawa, Masatoshi Akaishi, Yuji Kikuchi
  • Patent number: 9711716
    Abstract: A magnetic memory device and a method for manufacturing the magnetic memory device are disclosed. The method includes forming a first interlayer insulating layer on a substrate, forming a first conductive pattern that penetrates the first interlayer insulating layer, forming a mold insulating layer that includes first and second mold insulating layers on the first interlayer insulating layer, forming a second conductive pattern that penetrates the first and second mold insulating layers and the first interlayer insulating layer, and forming a magnetic tunnel junction pattern on the second conductive pattern. The first mold insulating layer is in contact with the first conductive pattern, and the second mold insulating layer is disposed on the first mold insulating layer.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: July 18, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Myoungsu Son, Kiseok Suh, Gwanhyeob Koh, KyungTae Nam, Yoonjong Song
  • Patent number: 9704816
    Abstract: An active region structure includes a device region, an active layer and a shallow trench isolation (STI) layer. The device region is defined on a substrate. The active layer is formed by a top portion of the substrate and has a plurality of device cells within the device region and a border structure surrounding the device region. The border structure has at least one branch extending into the device region and is between a portion of the device cells. The STI layer has a first part formed within the border structure to insulate the device cells from one another and a second part surrounding an outer periphery of the border structure. The second part of the STI layer isolates the device cells from a peripheral active region.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: July 11, 2017
    Assignees: United Microelectronics Corp., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventor: Tsai-Yu Huang
  • Patent number: 9685331
    Abstract: A semiconductor device manufacturing method includes forming a first film on a substrate having a first region and a second region. A second film is formed on the first film. Guide grooves are formed by removing portions of the second film and exposing the first film. A self-assembly material is coated on the exposed first film and heated to cause a phase separation into a first and a second phase section. The self-assembly material is irradiated. A mask pattern including at least a portion of the first phase section is formed by removing the second phase section. The mask pattern has a first dimension in the first region and a second dimension in the second region that is different from the first dimension. The first film is etched after the mask pattern is formed.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: June 20, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ayako Kawanishi, Yusuke Kasahara, Hiroki Yonemitsu
  • Patent number: 9634012
    Abstract: In a method of forming active patterns, first patterns are formed in a first direction on a cell region of a substrate, and a second pattern is formed on a peripheral circuit region of the substrate. The first pattern extends in a third direction crossing the first direction. First masks are formed in the first direction on the first patterns, and a second mask is formed on the second pattern. The first mask extends in a fourth direction crossing the third direction. Third masks are formed between the first masks extending in the fourth direction. The first and second patterns are etched using the first to third masks to form third and fourth patterns. Upper portions of the substrate are etched using the third and fourth patterns to form first and second active patterns in the cell and peripheral circuit regions.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: April 25, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Jin Park, Chan-sic Yoon, Ki-Seok Lee, Hyeon-Ok Jung, Dae-Ik Kim, Bong-Soo Kim, Yong-Kwan Kim, Eun-Jung Kim, Se-Myeong Jang, Min-su Choi, Sung-Hee Han, Yoo-Sang Hwang
  • Patent number: 9576850
    Abstract: When a recess is formed in a SiCOH film, C is removed from the film to form a damage layer. If the damage layer is removed by hydrofluoric acid or the like, the surface becomes hydrophobic. By supplying a boron compound gas, a silicon compound gas or a gas containing trimethyl aluminum to the SiCOH film, B, Si or Al is adsorbed on the SiCOH film. These atoms bond with Ru and a Ru film is easily formed on the SiCOH film. The Ru film is formed using, for example, Ru3(CO)12 gas and CO gas. Copper is filled in the recess and an upper side wiring structure is formed by carrying out CMP processing.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: February 21, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Tadahiro Ishizaka, Atsushi Gomi, Kenji Suzuki, Tatsuo Hatano, Yasushi Mizusawa
  • Patent number: 9505610
    Abstract: Techniques and mechanisms for providing precisely fabricated structures of a semiconductor package. In an embodiment, a build-up carrier of the semiconductor package includes a layer of porous dielectric material. Seed copper and plated copper is disposed on the layer of porous dielectric material. Subsequent etching is performed to remove copper adjacent to the layer of porous dielectric material, forming a gap separating a suspended portion of a MEMS structure from the layer of porous dielectric material. In another embodiment, the semiconductor package includes a copper structure disposed between portions of an insulating layer or portions of a layer of silicon nitride material. The layer of silicon nitride material couples the insulating layer to another insulating layer. One or both of the insulating layers are each protected from desmear processing with a respective release layer structure.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: November 29, 2016
    Assignee: Intel Corporation
    Inventors: Weng Hong Teh, Tarek A Ibrahim, Sarah K Haney, Daniel N Sobieski, Parshuram B Zantye, Chad E Mair, Telesphor Kamgaing
  • Patent number: 9478506
    Abstract: Approaches for multilayer pattern transfer for chemical guides are provided. In a typical embodiment, a device is formed by forming an etch mask layer (e.g., a nitride layer and an oxide layer) over a substrate (e.g., silicon (Si)). An orientation control layer (e.g., a neutral layer) is then formed over the etch mask layer, and an ARC layer (e.g., SiARC) is formed over the orientation control layer. In other embodiments, an organic planarization layer (OPL) and/or a protection layer may also be formed between the ARC layer and the orientation control layer. Regardless, a tapered etch profile/pattern may then be formed through the ARC and/or other layers.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: October 25, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Richard A. Farrell, Gerard M. Schmid, Sudharshanan Raghunathan
  • Patent number: 9478415
    Abstract: A method for forming on a substrate a doped silicon oxide film with a cap film, includes: forming an arsenosilicate glass (ASG) film as an arsenic (As)-doped silicon oxide film on a substrate; continuously treating a surface of the ASG film with a treating gas constituted by Si, N, and H without excitation; and continuously forming a silicon nitride (SiN) film as a cap film on the treated surface of the ASG film.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: October 25, 2016
    Assignee: ASM IP Holding B.V.
    Inventors: Yosuke Kimura, David de Roest
  • Patent number: 9455177
    Abstract: Methods of forming contact holes comprising: (a) providing a substrate comprising a plurality of post patterns over a layer to be patterned; (b) forming a hardmask layer over the post patterns and the layer to be patterned; (c) coating a pattern treatment composition over the hardmask layer, wherein the pattern treatment composition comprises a polymer comprising a reactive surface attachment group and a solvent; and optionally baking the substrate; wherein the polymer becomes bonded to the hardmask layer to form a polymer layer over the hardmask layer; and (d) treating the substrate with a rinsing agent comprising a solvent to remove residual, unbound said polymer, thereby forming a first hole disposed between a plurality of surrounding post patterns. The method is free of exposing the polymer to activating radiation from coating the pattern treatment composition to treating the substrate with the solvent. Also provided are pattern treatment compositions and electronic devices formed by the methods.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: September 27, 2016
    Assignees: Dow Global Technologies LLC, Rohm and Haas Electronic Materials LLC
    Inventors: Jong Keun Park, Phillip D. Hustad
  • Patent number: 9431265
    Abstract: Methods that enable fin cut at very tight pitch are provided. After forming a first set of paired sidewall image transfer (SIT) spacers and a second set of paired SIT spacers composed of different materials, portions of the first set of the paired SIT spacers can be selectively removed without adversely affecting the second set of the paired SIT spacers, even portions of both sets of the paired SIT spacers are exposed by the cut mask due to the different etching characteristics of the different materials.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: August 30, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Tenko Yamashita
  • Patent number: 9412604
    Abstract: The present inventive concept provides methods of manufacturing a semiconductor device including forming an inner mask layer on an etching target film, the inner mask layer including a polymer; forming a porous film on the etching target film, the porous film covering the inner mask layer; supplying an acid source to an outer surface area of the inner mask layer through the porous film; inducing a chemical reaction of the polymer included in the inner mask layer in the outer surface area by using the acid source; forming inner mask patterns by removing a chemically reacted portion of the inner mask layer; and etching the etching target film by using at least a portion of the porous film and the inner mask patterns as an etching mask.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: August 9, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Cha-won Koh, Hyun-woo Kim, Jong-soo Kim, Jin Park, Hyung-rae Lee
  • Patent number: 9349808
    Abstract: A semiconductor structure is provided by a process in which two aspect ratio trapping processes are employed. The structure includes a semiconductor substrate portion of a first semiconductor material having a first lattice constant. A plurality of first semiconductor-containing pillar structures of a second semiconductor material having a second lattice constant that is greater than the first lattice constant extend upwards from a surface of the semiconductor substrate portion. A plurality of second semiconductor-containing pillar structures of a third semiconductor material having a third lattice constant that is greater than the first lattice constant extend upwards from another surface of the semiconductor substrate portion. A spacer separates each first semiconductor-containing pillar structure from each second semiconductor-containing pillar structure. Each second semiconductor-containing pillar structure has a width that is different from a width of each first semiconductor-containing pillar structure.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: May 24, 2016
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9318342
    Abstract: One illustrative method disclosed herein includes forming a plurality of initial fins in a substrate, wherein at least one of the initial fins is a to-be-removed fin, forming a material adjacent the initial fins, forming a fin removal masking layer above the plurality of initial fins, removing a desired portion of the at least one to-be-removed fin by: (a) performing a recess etching process on the material to remove a portion, but not all, of the material positioned adjacent the sidewalls of the at least one to-be-removed fin, (b) after performing the recess etching process, performing a fin recess etching process to remove a portion, but not all, of the at least one to be removed fin and (c) repeating steps (a) and (b) until the desired amount of the at least one to-be-removed fin is removed.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: April 19, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Andreas Knorr, Ajey Poovannummoottil Jacob, Michael Hargrove
  • Patent number: 9287109
    Abstract: One method disclosed herein includes forming a layer of insulating material above a semiconductor substrate, forming a hard mask layer comprised of a metal-containing material above the layer of insulating material, forming a blanket protection layer on the hard mask layer, forming a masking layer above the protection layer, performing at least one etching process on the masking layer to form a patterned masking layer having an opening that stops on and exposes a portion of the blanket protection layer, confirming that the patterned masking layer is properly positioned relative to at least one underlying structure or layer and, after confirming that the patterned masking layer is properly positioned, performing at least one etching process through the patterned masking layer to pattern at least the blanket protection layer.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: March 15, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Torsten Huisinga, Keith Donegan, Robert Seidel
  • Patent number: 9263542
    Abstract: A semiconductor device comprises a substrate, an active layer over the substrate, and an insulating layer between the substrate and the active layer. The insulating layer is doped with one of positive charge and negative charge and configured to establish an electric field across the active layer when the semiconductor device is powered.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: February 16, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chee-Wee Liu, Yen-Yu Chen, Hsuan-Yi Lin, Cheng-Yi Peng
  • Patent number: 9257301
    Abstract: Provided is a method of etching a silicon oxide film. The method includes exposing a workpiece including the silicon oxide film and a mask formed on the silicon oxide film to plasma of a processing gas to etch the silicon oxide film. The mask includes a first film formed on the silicon oxide film and a second film formed on the first film, and the second film is constituted by a film having an etching rate lower than that of the first film with respect to active species in the plasma.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: February 9, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Masahiro Ogasawara, Masafumi Urakawa, Yoshinobu Hayakawa, Kazuhiro Kubota, Hikaru Watanabe
  • Patent number: 9218970
    Abstract: A method to form a titanium nitride (TiN) hard mask in the Damascene process of forming interconnects during the fabrication of a semiconductor device, while the type and magnitude of stress carried by the TiN hard mask is controlled. The TiN hard mask is formed in a multi-layered structure where each sub-layer is formed successively by repeating a cycle of processes comprising TiN and chlorine PECVD deposition, and N2/H2 plasma gas treatment. During its formation, the stress to be carried by the TiN hard mask is controlled by controlling the number of TiN sub-layers and the plasma gas treatment duration such that the stress may counter-balance predetermined external stress anticipated on a conventionally made TiN hard mask, which causes trench sidewall distortion, trench opening shrinkage, and gap filling problem.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: December 22, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Rueijer Lin, Chun-Chieh Lin, Hung-Wen Su, Ming-Hsing Tsai
  • Patent number: 9177920
    Abstract: Embodiments of the present invention disclose a thin film transistor array substrate, a method of manufacturing the same, and display device. A method of manufacturing a thin film transistor array substrate, comprises: forming a resin layer on a substrate formed with a thin film transistor array, patterning the resin layer by using a mask process to form a spacer and a contact hole filling layer, the contact hole filing layer is used for filling contact holes on the thin film transistor array substrate; forming an alignment film on the substrate patterning with the spacer and the contact hole filing layer.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: November 3, 2015
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hyun Sic Choi, Zhiqiang Xu, Hui Li
  • Patent number: 9159547
    Abstract: A semiconductor device and method of making the semiconductor device is described. A semiconductor die is provided. A polymer layer is formed over the semiconductor die. A via is formed in the polymer layer. The polymer layer is crosslinked in a first process. The polymer layer is thermally cured in a second process. The polymer layer can comprise polybenzoxazoles (PBO), polyimide, benzocyclobutene (BCB), or siloxane-based polymers. A surface of the polymer layer can be crosslinked by a UV bake to control a slope of the via during subsequent curing. The second process can further comprise thermally curing the polymer layer using conduction, convection, infrared, or microwave heating. The polymer layer can be thermally cured by increasing a temperature of the polymer at a rate greater than or equal to 10 degrees Celsius per minute, and can be completely cured in less than or equal to 60 minutes.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: October 13, 2015
    Assignee: DECA Technologies Inc.
    Inventors: William Boyd Rogers, Willibrordus Gerardus Maria van den Hoek
  • Patent number: 9088125
    Abstract: An electromagnetic wave generator for outputting wideband electromagnetic waves, including terahertz (THz) band waves, and for controlling wavelengths of the output electromagnetic waves and an optical shutter are provided. The electromagnetic wave generator includes two electrodes that separately face each other, a chargeable particle disposed between the two electrodes, and a chamber disposed to surround the chargeable particle between the two electrodes. When DC voltages are applied to the two electrodes to generate an electric field between the two electrodes, the chargeable particle may be charged. Then, the chargeable particle reciprocates between the two electrodes to generate the electromagnetic waves. A wavelength of the output electromagnetic wave may be controlled by adjusting a potential difference between the two electrodes.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: July 21, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Sung Nae Cho
  • Patent number: 9076989
    Abstract: A masking film (13) is formed so as to have an opening in a display region (R1) (luminescent region) and a sealing region. Subsequently, luminescent layers (8R, 8G, and 8B) having a stripe pattern are formed. Then, the masking film (13) is peeled off, so that the luminescent layers (8R, 8G, and 8B) patterned with high resolution are provided.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: July 7, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tohru Sonoda, Shinichi Kawato, Satoshi Inoue, Satoshi Hashimoto
  • Patent number: 9076847
    Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: July 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Matthew S. Angyal, Junjing Bao, Griselda Bonilla, Samuel S. Choi, James A. Culp, Thomas W. Dyer, Ronald G. Filippi, Stephen E. Greco, Naftali E. Lustig, Andrew H. Simon
  • Publication number: 20150147863
    Abstract: Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.
    Type: Application
    Filed: December 12, 2014
    Publication date: May 28, 2015
    Inventor: Bernhard Sell
  • Publication number: 20150137204
    Abstract: A semiconductor process for manufacturing particular patterns includes the steps of forming a target layer and evenly-spaced core bodies on a substrate, conformally forming a hard mask layer, forming a first photoresist covering a predetermined region on the hard mask layer wherein the predetermined region encompasses at least two core bodies, performing a first etch process to remove a portion of the hard mask layer outside the predetermined region and expose a number of core bodies, removing the exposed core bodies, forming a second photoresist at least encompassing all the recesses in the predetermined region, and performing a second etch process to pattern the target layer.
    Type: Application
    Filed: May 19, 2014
    Publication date: May 21, 2015
    Applicant: Powerchip Technology Corporation
    Inventors: Zih-Song Wang, Chia-Ming Wu
  • Publication number: 20150140824
    Abstract: A jig includes a wafer including an accommodation groove configured to accommodate a capacitive micromachined ultrasonic transducer (cMUT) when flip chip bonding is performed, and a separation groove formed in a bottom surface of the accommodation groove, the separation groove having a bottom surface that is spaced apart from thin films of the cMUT that face the bottom surface of the separation groove when the cMUT is seated on portions of the bottom surface of the accommodation groove.
    Type: Application
    Filed: January 28, 2015
    Publication date: May 21, 2015
    Applicants: SAMSUNG ELECTRONICS CO., LTD., Kyungpook National University Industry-Academic Cooperation Foundation
    Inventors: Young Il KIM, Bae Hyung KIM, Jong Keun SONG, Seung Heun LEE, Kyung Il CHO, Yong Rae ROH, Won Seok LEE
  • Patent number: 9034766
    Abstract: According to one embodiment, a pattern formation method includes: forming a first guide layer having of first openings exposing a surface of an underlayer, and the first openings being arranged in a first direction; forming a second guide layer on the underlayer and on the first guide layer, the second guide layer extending in the first direction, the second guide layer dividing each of the first openings into the first opening portion and the second opening portion, and the second guide layer being sandwiched by a first opening portion and a second opening portion; forming a block copolymer layer in each of the first opening portion and the second opening portion; forming a first layer and a second layer surrounded by the first layer in each of the first opening portion and the second opening portion by phase-separating the block copolymer layer; and removing the second layer.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: May 19, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kentaro Matsunaga, Yoshihiro Yanai, Hirokazu Kato
  • Patent number: 9034755
    Abstract: Embodiments of the present invention provide a method of forming contact structure for transistor. The method includes providing a semiconductor substrate having a first and a second gate structure of a first and a second transistor formed on top thereof, the first and second gate structures being embedded in a first inter-layer-dielectric (ILD) layer; epitaxially forming a first semiconductor region between the first and second gate structures inside the first ILD layer; epitaxially forming a second semiconductor region on top of the first semiconductor region, the second semiconductor region being inside a second ILD layer on top of the first ILD layer and having a width wider than a width of the first semiconductor region; and forming a silicide in a top portion of the second semiconductor region.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Reinaldo A. Vega
  • Patent number: 9034763
    Abstract: A method for manufacturing a sloped structure is disclosed. The method includes the steps of: (a) forming a sacrificial film above a substrate; (b) forming a first film above the sacrificial film; (c) forming a second film having a first portion connected to the substrate, a second portion connected to the first film, and a third portion positioned between the first portion and the second portion; (d) removing the sacrificial film; and (e) bending the third portion of the second film after the step (d), thereby sloping the first film with respect to the substrate.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: May 19, 2015
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Takahiko Yoshizawa
  • Patent number: 9034765
    Abstract: A method of forming a semiconductor device includes first preliminary holes over an etch target, the first preliminary holes arranged as a plurality of rows in a first direction, forming dielectric patterns each filling one of the first preliminary holes, sequentially forming a barrier layer and a sacrificial layer on the dielectric patterns, forming etch control patterns between the dielectric patterns, forming second preliminary holes by etching the sacrificial layer, each of the second preliminary holes being in a region defined by at least three dielectric patterns adjacent to each other, and etching the etch target layer corresponding to positions of the first and second preliminary holes to form contact holes.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: May 19, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joonsoo Park, JungWoo Seo, KyoungRyul Yoon, Cheolhong Kim, Seokwoo Nam, Yongjik Park
  • Patent number: 9034764
    Abstract: A method of forming an encapsulated wide trench includes providing a silicon on oxide insulator (SOI) wafer, defining a first side of a first sacrificial silicon slab by etching a first trench in a silicon layer of the SOI wafer, defining a second side of the first sacrificial silicon slab by etching a second trench in the silicon layer, forming a first sacrificial oxide portion in the first trench, forming a second sacrificial oxide portion in the second trench, forming a polysilicon layer above the first sacrificial oxide portion and the second sacrificial oxide portion, and etching the first sacrificial oxide portion and the second sacrificial oxide portion.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: May 19, 2015
    Assignee: Robert Bosch GmbH
    Inventor: Gary O'Brien
  • Publication number: 20150130027
    Abstract: A method of forming a carbon-containing thin film and a method of manufacturing a semiconductor device using the method of forming the carbon-containing thin film are described. The method of forming a carbon-containing thin film includes the steps of introducing a substrate into a chamber, injecting hydrocarbon gas and at least nitrogen gas simultaneously into the chamber, and depositing a carbon-containing thin film including carbon and nitrogen on the substrate, thereby forming a carbon-containing thin film having high selectivity and uniform thickness.
    Type: Application
    Filed: November 11, 2014
    Publication date: May 14, 2015
    Inventors: Se jun PARK, Ho jun KIM, Jaihyung WON, Gyuwan CHOI, Dohyung KIM
  • Publication number: 20150130028
    Abstract: A method of manufacturing a semiconductor chip according to an embodiment includes forming on a semiconductor substrate a plurality of etching masks each including a protection film to demarcate a plurality of first regions of the substrate protected by the plurality of etching masks and a second region as an exposed region of the substrate, and anisotropically removing the second region by a chemical etching process to form a plurality of grooves each including a side wall at least partially located in the same plane as an end face of the etching mask and a bottom portion reaching a back surface of the substrate, thereby singulating the semiconductor substrate into a plurality of chip main bodies corresponding to the plurality of first regions.
    Type: Application
    Filed: November 13, 2014
    Publication date: May 14, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yusaku ASANO, Kazuhito Higuchi, Taizo Tomioka, Tomohiro Iguchi
  • Publication number: 20150123212
    Abstract: Approaches for providing a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. A previously deposited amorphous carbon layer can be removed from over a mandrel that has been previously formed on a subset of a substrate, such as using a photoresist. A pad hardmask can be formed over the mandrel on the subset of the substrate. This formation results in the subset of the substrate having the pad hardmask covering the mandrel thereon and the remainder of the substrate having the amorphous carbon layer covering the mandrel thereon. This amorphous carbon layer can be removed from over the mandrel on the remainder of the substrate, allowing a set of fins to be formed therein while the amorphous carbon layer keeps the set of fins from being formed in the portion of the substrate that it covers.
    Type: Application
    Filed: November 4, 2013
    Publication date: May 7, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Xiang Hu, Lokesh Subramany, Alok Vaid, Sipeng Gu, Akshey Sehgal
  • Publication number: 20150126034
    Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming etch resistant fill control topographical features that overlie a semiconductor substrate. The etch resistant fill control topographical features define an etch resistant fill control confinement well. A block copolymer is deposited into the etch resistant fill control confinement well. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The etch resistant fill control topographical features direct the etch resistant phase to form an etch resistant plug in the etch resistant fill control confinement well.
    Type: Application
    Filed: November 5, 2013
    Publication date: May 7, 2015
    Applicant: GLOBALFOUNDRIES, Inc.
    Inventors: Azat Latypov, Edward Teoh Kah Ching, He Yi
  • Publication number: 20150118832
    Abstract: Embodiments of the present invention provide a methods for patterning a hardmask layer with good process control for an ion implantation process, particularly suitable for manufacturing the fin field effect transistor (FinFET) for semiconductor chips. In one embodiment, a method of patterning a hardmask layer disposed on a substrate includes forming a planarization layer over a hardmask layer disposed on a substrate, disposing a patterned photoresist layer over the planarization layer, patterning the planarization layer and the hardmask layer uncovered by the patterned photoresist layer in a processing chamber, exposing a first portion of the underlying substrate, and removing the planarization layer from the substrate.
    Type: Application
    Filed: October 24, 2013
    Publication date: April 30, 2015
    Inventors: Bingxi Sun WOOD, Li Yan MIAO, Huixiong DAI, Adam BRAND, Yongmei CHEN, Mandar B. PANDIT, Qingjun ZHOU
  • Patent number: 9012955
    Abstract: A MOS transistor protected against overvoltages formed in an SOI-type semiconductor layer arranged on an insulating layer itself arranged on a semiconductor substrate including a lateral field-effect control thyristor formed in the substrate at least partly under the MOS transistor, a field-effect turn-on region of the thyristor extending under at least a portion of a main electrode of the MOS transistor and being separated therefrom by said insulating layer, the anode and the cathode of the thyristor being respectively connected to the drain and to the source of the MOS transistor, whereby the thyristor turns on in case of a positive overvoltage between the drain and the source of the MOS transistor.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: April 21, 2015
    Assignee: STMicroelectronics SA
    Inventor: Pascal Fonteneau
  • Patent number: 9012326
    Abstract: A lower layer of a microelectronic device may be patterned by forming a first sacrificial layer on the lower layer; patterning a plurality of spaced apart trenches in the first sacrificial layer; forming a second sacrificial layer in the plurality of spaced apart trenches; patterning the second sacrificial layer in the plurality of spaced apart trenches to define upper openings in the plurality of spaced apart trenches; and patterning the lower layer using the first and second sacrificial layers as a mask to form lower openings in the lower layer.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: April 21, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Nam-Gun Kim, Yoonjae Kim, Sungil Cho
  • Patent number: 9012314
    Abstract: A method for forming doping regions is disclosed, including providing a substrate, forming a first-type doping material on the substrate and forming a second-type doping material on the substrate, wherein the first-type doping material is separated from the second-type doping material by a gap; forming a covering layer to cover the substrate, the first-type doping material and the second-type doping material; and performing a thermal diffusion process to diffuse the first-type doping material and the second-type doping material into the substrate.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: April 21, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Wen-Ching Sun, Sheng-Min Yu, Tai-Jui Wang, Tzer-Shen Lin