Abstract: The present invention provides a method of forming an opening on a semiconductor substrate. First, a substrate is provided. Then a dielectric layer and a cap layer are formed on the substrate. A ratio of a thickness of the dielectric layer and a thickness of the cap layer is substantially between 15 and 1.5. Next, a patterned boron nitride layer is formed on the cap layer. Lastly, an etching process is performed by using the patterned hard mask as a mask to etch the cap layer and the dielectric layer so as to form an opening in the cap layer and the dielectric layer.

Abstract: Disclosed herein are methods of doping a patterned substrate in a reaction chamber. The methods may include forming a first conformal film layer which has a dopant source including a dopant, and driving some of the dopant into the substrate to form a conformal doping profile. In some embodiments, forming the first film layer may include introducing a dopant precursor into the reaction chamber, adsorbing the dopant precursor under conditions whereby it forms an adsorption-limited layer, and reacting the adsorbed dopant precursor to form the dopant source. Also disclosed herein are apparatuses for doping a substrate which may include a reaction chamber, a gas inlet, and a controller having machine readable code including instructions for operating the gas inlet to introduce dopant precursor into the reaction chamber so that it is adsorbed, and instructions for reacting the adsorbed dopant precursor to form a film layer containing a dopant source.

Abstract: According to one embodiment, a pattern formation method includes: forming a first guide layer having of first openings exposing a surface of an underlayer, and the first openings being arranged in a first direction; forming a second guide layer on the underlayer and on the first guide layer, the second guide layer extending in the first direction, the second guide layer dividing each of the first openings into the first opening portion and the second opening portion, and the second guide layer being sandwiched by a first opening portion and a second opening portion; forming a block copolymer layer in each of the first opening portion and the second opening portion; forming a first layer and a second layer surrounded by the first layer in each of the first opening portion and the second opening portion by phase-separating the block copolymer layer; and removing the second layer.

Abstract: A method of fabricating a patterned structure of a semiconductor device is provided. First, a substrate having a first region and a second region is provided. A target layer, a hard mask layer and a first patterned mask layer are then sequentially formed on the substrate. A first etching process is performed by using the first patterned mask layer as an etch mask so that a patterned hard mask layer is therefore formed. Spacers are respectively formed on each sidewall of the patterned hard mask layer. Then, a second patterned mask layer is formed on the substrate. A second etching process is performed to etch the patterned hard mask layer in the second region. After the exposure of the spacers, the patterned hard mask layer is used as an etch mask and an exposed target layer is removed until the exposure of the corresponding substrate.

Abstract: Some embodiments include methods of forming vertically-stacked memory cells. An opening is formed to extend partially through a stack of alternating electrically insulative levels and electrically conductive levels. A liner is formed along sidewalls of the opening, and then the stack is etched to extend the opening. The liner is at least partially consumed during the etch and forms passivation material. Three zones occur during the etch, with one of the zones being an upper zone of the opening protected by the liner, another of the zones being an intermediate zone of the opening protected by passivation material but not the liner, and another of the zones being a lower zone of the opening which is not protected by either passivation material or the liner. Cavities are formed to extend into the electrically conductive levels along sidewalls of the opening. Charge blocking dielectric and charge-storage structures are formed within the cavities.

Abstract: Methods of manufacturing semiconductor integrated circuits having FinFET structures with epitaxially formed source and drain regions are disclosed. For example, a method of fabricating an integrated circuit includes forming a plurality of silicon fin structures on a semiconductor substrate, forming disposable spacers on vertical sidewalls of the fin structures, and depositing a silicon oxide material over the fins and over the disposable spacers. The method further includes anisotropically etching at least one of the fin structures and the disposable spacers on the sidewalls of the at least one fin structure, thereby leaving a void in the silicon oxide material, and etching the silicon oxide material and the disposable spacers from at least one other of the fin structures, while leaving the at least one other fin structure un-etched. Still further, the method includes epitaxially growing a silicon material in the void and on the un-etched fin structure.

Abstract: Methods of forming contact holes include forming a first guide pattern over an etching target layer. The first guide pattern has first openings each extending in a first direction and each first opening arranged in a direction perpendicular to the first direction. A first BCP structure is formed in each first opening. The first BCP structure includes first material layers in the first direction at a first pitch in each of the first openings, and second material layers filling a remaining portion of each first opening. First holes are formed by removing the first material layers. A second guide pattern is formed over the first guide pattern and the second material layers, and the above processes are performed on the second guide pattern to form second holes. Portions of the etching target layer overlapped by the first holes or the second holes are removed to form a desired pattern.

Abstract: A method of manufacturing a semiconductor device, includes the steps of forming a top surface nitride film on a top surface of a substrate and a bottom surface nitride film on a bottom surface of the substrate, forming a protective film on the top surface nitride film, removing the bottom surface nitride film by wet etching while the top surface nitride film is being protected by the protective film, removing the protective film after the removing of the bottom surface nitride film, patterning the top surface nitride film so as to form an opening in the top surface nitride film, and forming a second oxide film on the bottom surface of the substrate while forming a first oxide film on a surface portion of the substrate which is exposed by the opening.

Abstract: There is provided a manufacturing method of a semiconductor device including forming a first pattern of first features, according to a lithography process, in a photoresist layer disposed on a substrate, the lithography process having a minimum printable dimension and a minimum printable pitch, applying an additional layer on the photoresist layer having the first pattern formed therein, forming a second pattern of second features in the additional layer, the second features concentric with the first features, and etching portions of the substrate exposed through the second pattern. Further, in the provided method, the first features include geometrical features separated by a distance less than the dimension of minimum printable feature, and the geometrical features are disposed at a pitch less than the minimum printable pitch.

Abstract: Methods for fabricating integrated circuits with improved patterning schemes are provided. In an embodiment, a method for fabricating an integrated circuit includes depositing an interlayer dielectric material overlying a semiconductor substrate. Further, the method includes forming a patterned hard mask overlying the interlayer dielectric material. Also, the method forms an organic planarization layer overlying the patterned hard mask and contacting portions of the interlayer dielectric material. The method patterns the organic planarization layer using an extreme ultraviolet (EUV) lithography process. The method also includes etching the interlayer dielectric material using the patterned hard mask and organic planarization layer as a mask to form vias in the interlayer dielectric material.

Abstract: A method of fabricating a semiconductor device is provided. An etch-target layer is formed on a substrate. A photoresist layer is formed on the etch-target layer. A first exposure process is performed using a first photo mask to form a plurality of first-irradiated patterns in the photoresist layer. The first photo mask includes a plurality of first transmission regions. Each first transmission region has different optical transmittance. A second exposure process is performed using a second photo mask to form a plurality of second-irradiated patterns in the photoresist layer. The second photo mask includes a plurality of second transmission regions. Each second transmission region has different optical transmittance. A photoresist pattern is formed from the photoresist layer by removing the plurality of first-irradiated and second-irradiated patterns from the photoresist layer. A lower structure is formed from the etch-target layer by etching the etch-target layer using the photoresist pattern.

Abstract: Methods of forming patterns are provided. The methods may include sequentially forming an etch-target layer and a photoresist layer on a substrate, exposing two first portions of the photoresist layer to light to transform the two first portions into two first photoresist patterns and exposing a second portion of the photoresist layer to light to transform the second portion into a second photoresist pattern disposed between the two first photoresist patterns. The method may also removing portions of the photoresist layer to leave the two first photoresist patterns and the second photo resist pattern on the etch-target layer such that the etch-target layer is exposed.

Abstract: A NAND flash memory array is initially patterned by forming a plurality of sidewall spacers according along sides of patterned portions of material. The pattern of sidewall spacers is then used to form a second pattern of hard mask portions including first hard mask portions defined on both sides by sidewall spacers and second hard mask portions defined on only one side by sidewall spacers.

Abstract: A method includes receiving a substrate having an etch stop layer deposited over the substrate and a dummy mandrel layer deposited over the etch stop layer, forming a plurality of hard mask patterns using a hard mask layer deposited over the dummy mandrel layer, wherein the hard mask patterns includes a first dimension adjusted by a predetermined value, depositing a first spacer layer over the hard mask patterns, wherein a thickness of the first spacer layer is adjusted by the predetermined value, forming a plurality of spacer fins in the dummy mandrel layer, wherein the spacer fins include a second dimension, a first space, and a second space, performing a first fin cut process to remove at least one spacer fin, adjusting the second dimension to a target dimension, performing a second fin cut process, and forming a plurality of fin structures in the substrate by etching the spacer fins.

Abstract: Transistors are formed using pitch multiplication. Each transistor includes a source region and a drain region connected by strips of active area material separated by shallow trench isolation (STI) structures, which are formed by dielectric material filling trenches formed by pitch multiplication. During pitch multiplication, rows of spaced-apart mandrels are formed and spacer material is deposited over the mandrels. The spacer material is etched to define spacers on sidewalls of the mandrels. The mandrels are removed, leaving free-standing spacers. The spacers constitute a mask, through which an underlying substrate is etched to form the trenches and strips of active area material. The trenches are filled to form the STI structures. The substrate is doped, forming source, drain and channel regions. A gate is formed over the channel region. In some embodiments, the STI structures and the strips of material facilitate the formation of transistors having a high breakdown voltage.

Abstract: A method of fabricating a patterned substrate, with which the optical performance of a photovoltaic cell including an organic solar cell and an organic light-emitting diode (OLED) can be improved. The method includes generating electrostatic force on a surface of a substrate by treating the substrate with electrolytes, causing nano-particles to be adsorbed on the surface of the substrate, etching the surface of the substrate using the nano-particles as an etching mask, and removing the nano-particles residing on the surface of the substrate.

Abstract: The present invention provides a method of forming via holes. First, a substrate is provided. A plurality of first areas is defined on the substrate. A dielectric layer and a blocking layer are formed on the substrate. A patterned photoresist layer is formed on the blocking layer. The patterned photoresist layer includes a plurality of holes arranged in a regular array wherein the area of the hole array is greater than those of the first areas. The blocking layer in the first areas is removed by using the patterned photoresist layer as a mask. Lastly, the dielectric layer is patterned to form at least a via hole in the dielectric layer in the first area.

Abstract: Provided are a method for forming a microfine structure and a microfine structure forming body prepared by the method. The method allows a remaining film part to be formed thinner and more uniform on a substrate than the conventional techniques. The method comprises the steps of: forming an oxide layer on a metallic thin film; a photocurable resin layer via first and second adhesive layers over the oxide layer; and transferring a microfine structure formed on a mold by pressing the mold onto the photocurable resin layer. The first adhesive layer includes a compound having at least two hydrolysable functional groups, and the second adhesive layer includes a compound having at least a hydrolysable functional group and a reactive functional group.

Abstract: A method of forming fine patterns in a semiconductor device includes forming narrow-width patterns in a first region and wide-width patterns in a second region, where the widths of the narrow-width patterns are smaller than the resolution limitations in a photolithography process used to make the semiconductor device. The first and second regions may comprise cell array regions, with memory cells in the first region and peripheral circuits for operating the memory cells in the second region. The semiconductor device can be, for example, a NAND FLASH memory device. The semiconductor memory device can be variously classified according to the type of memory cells to be integrated in the cell array region, e.g., a DRAM, an SRAM, a PRAM, a RRAM, an MRAM, and a FRAM. In other embodiments, a MEMS device, an optoelectronic device, or a processor, such as CPU or DSP, may be provided on the semiconductor substrate.

Abstract: Embodiments described herein generally relate to the fabrication of integrated circuits and more particularly to nitrogen doped amorphous carbon layers and processes for depositing nitrogen doped amorphous carbon layers on a semiconductor substrate. In one embodiment, a method of forming a nitrogen doped amorphous carbon layer on a substrate is provided. The method comprises positioning a substrate in a substrate processing chamber, introducing a nitrogen containing hydrocarbon source into the processing chamber, introducing a hydrocarbon source into the processing chamber, introducing a plasma-initiating gas into the processing chamber, generating a plasma in the processing chamber, and forming a nitrogen doped amorphous carbon layer on the substrate.

Abstract: The inventive concepts provide methods of forming a pattern. In the method, a block copolymer layer may be formed on a neutral layer having an uneven structure and then phase separation is induced. The neutral layer may have an affinity for all of a hydrophilic polymer and a hydrophobic polymer, so that vertical cultivation of phases of the block copolymer may be realized on the uneven structure. Thus, a self-assembled phenomenon may be induced.

Abstract: A method includes forming a sacrificial layer over a bottom substrate. The sacrificial layer is patterned based on a desired etching distance. A top layer is formed over the sacrificial layer. At least one release hole is formed through the top layer. The sacrificial layer is etched through the at least one release hole.

Abstract: A metal mask having an etching pattern having a very high verticality is formed, and an etching shape having a very high verticality is formed by etching a semiconductor with the metal mask as a mask. A resist film patterned with a reversal pattern obtained by reversing an etching pattern is formed on a semiconductor (resist film forming process, S100), a metal paste is filled in the reversal pattern of the resist film (metal paste filling process, S200), a metal mask having the etching pattern is formed by removing the resist film while baking the metal paste by a heating control (metal mask forming process, S300), and plasma etching is performed on the semiconductor by using the metal mask (etching process, S400).

Abstract: A process is provided for methods of reducing damage to an ultra-low k layer during fabrication. In one aspect, a method includes: providing a cured ultra-low k film containing pores filled with a pore-stuffing material; and modifying an exposed surface of the ultra-low k film to provide a modified layer in the ultra-low k film. In another aspect, a semiconductor device comprising a modified layer on a surface of an ultra-low k film is provided.

Abstract: A method of forming a metal oxide hardmask on a template includes: providing a template constituted by a photoresist or amorphous carbon formed on a substrate; and depositing by atomic layer deposition (ALD) a metal oxide hardmask on the template constituted by a material having a formula SixM(1-x)Oy wherein M represents at least one metal element, x is less than one including zero, and y is approximately two or a stoichiometrically-determined number.

Abstract: A method of producing plurality of etched features in an electronic device is disclosed that avoids micro-loading problems thus maintaining more uniform sidewall profiles and more uniform critical dimensions. The method comprises performing a first time-divisional plasma etch process step within a plasma chamber to a first depth of the plurality of etched features, and performing a flash process step to remove any polymers from exposed surfaces of the plurality of etched features without requiring an oxidation step. The flash process step is performed independently of the time-divisional plasma etch step. A second time-divisional plasma etch process step is performed within the plasma chamber to a second depth of the plurality of etched features. The method may be repeated until a desired etch depth is reached.

Abstract: A method for fabricating a semiconductor device includes: forming an interlayer insulating film on a substrate; forming a first hard mask formation film on the interlayer insulating film; altering the first hard mask formation film; after the altering of the first hard mask formation film, transferring an interconnect groove pattern to the altered first hard mask formation film to form a first hard mask made of the altered first hard mask formation film; and etching the interlayer insulating film using the first hard mask to form an interconnect groove in the interlayer insulating film. The first hard mask formation film is made of a metal film or a metallic compound film.

Abstract: A glass composition for protecting a semiconductor junction contains at least SiO2, B2O3, Al2O3, ZnO, and at least two oxides of alkaline earth metal selected from the group consisting of CaO, MgO and BaO, and substantially contains none of Pb, P, As, Sb, Li, Na and K.

Abstract: Methods of forming fine patterns for a semiconductor device include forming a hard mask layer on an etch target layer; forming a carbon containing layer on the hard mask layer; forming carbon containing layer patterns by etching the carbon containing layer; forming spacers covering opposing side walls of each of the carbon containing layer patterns; removing the carbon containing layer patterns; forming hard mask patterns by etching the hard mask layer using the spacers as a first etching mask; and etching the etch target layer by using the hard mask patterns a second etching mask.

Abstract: The description relates to a method of patterning a semiconductor device to create a through substrate via. The method produces a through substrate via having no photoresist material therein. An intermediate layer deposited over an interlayer dielectric prevents etching solutions from etching interlayer dielectric sidewalls to prevent peeling. The description relates to a semiconductor apparatus including a semiconductor substrate having a through substrate via therein. The semiconductor apparatus further includes an interlayer dielectric over the semiconductor substrate and an intermediate layer over semiconductor substrate and over sidewalls of the interlayer dielectric.

Abstract: Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n?2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over and parallel to mandrels at tier n?1, and the distance between adjoining mandrels at tier n is greater than the distance between adjoining mandrels at tier n?1. Spacers are simultaneously formed on sidewalls of the mandrels. Exposed portions of the mandrels are etched away and a pattern of lines defined by the spacers is transferred to the substrate.

Abstract: Disclosed herein are methods of patterning features that have differing widths. In one example, the method includes forming a layer of material above a semiconductor substrate, forming a masking layer above the layer of material, wherein the masking layer is comprised of a first plurality features positioned above a first region of the semiconductor substrate and a second plurality of features positioned above a second region of the semiconductor substrate, wherein the first and second plurality of features have the same pitch spacing and wherein the first and second plurality of features have different widths, and performing at least one etching process on the layer of material through the masking layer.

Abstract: A cleaning solution is provided. The cleaning solution includes an aliphatic polycarboxylic acid, a chain sulfonic acid substantially less than 4 wt % and an amine containing buffer agent.

Abstract: Embodiments of the present invention disclose a thin film transistor array substrate, a method of manufacturing the same, and display device. A method of manufacturing a thin film transistor array substrate, comprises: forming a resin layer on a substrate formed with a thin film transistor array, patterning the resin layer by using a mask process to form a spacer and a contact hole filling layer, the contact hole filing layer is used for filling contact holes on the thin film transistor array substrate; forming an alignment film on the substrate patterning with the spacer and the contact hole filing layer.

Abstract: A semiconductor device is fabricated by forming first holes arranged along a first direction on an etch-target layer, forming dielectric patterns in the first holes, conformally forming a barrier layer on the dielectric patterns, forming a sacrificial layer on the barrier layer to define a first void, partially removing the sacrificial layer to expose the first void, anisotropically etching the barrier layer to form second holes below the first void, and etching portions of the etch-target layer located below the first and second holes to form contact holes. The first void may be formed on a first gap region confined by at least three of the dielectric patterns disposed adjacent to each other, and the sacrificial layer may include a material having a low conformality.

Abstract: A method is provided for etching silicon in a plasma processing chamber, having an operating pressure and an operating bias. The method includes: performing a first vertical etch in the silicon to create a hole having a first depth and a sidewall; performing a deposition of a protective layer on the sidewall; performing a second vertical etch to deepen the hole to a second depth and to create a second sidewall, the second sidewall including a first trough, a second trough and a peak, the first trough corresponding to the first sidewall, the second trough corresponding to the second sidewall, the peak being disposed between the first trough and the second trough; and performing a third etch to reduce the peak.

Abstract: A method of manufacturing a semiconductor device includes forming a second insulating layer over a first insulating layer, forming a mask over the second insulating layer, after the forming the mask, a first etching of the second insulating layer which is not covered by the mask, and after the first etching, a second etching of the second insulating layer and the first insulating layer which are not covered by the mask. At the first etching, the second insulating layer left over the first insulating layer and the first insulating layer is not exposed. At the second etching, the left over second insulating layer and the first insulating layer are etched. The first insulating layer has a lower dielectric constant than the second insulating layer. A second etching condition of the second etching includes a larger flow rate of oxygen than a first etching condition of the first etching.

Abstract: In one embodiment, a method of making a trench for a semiconductor device can include: (i) providing a semiconductor substrate; (ii) forming a patterned hard mask layer with an opening on the semiconductor substrate, where a thickness of the patterned hard mask layer is from about 100 nm to about 400 nm; and (iii) using the patterned hard mask layer as a mask, and etching the semiconductor substrate to form the trench in the semiconductor substrate.

Abstract: According to the present invention, there is provided a process for producing a transistor having a high precision and a high quality with a high yield by selectively etching a natural silicon oxide film, and further by selectively etching a dummy gate made of silicon. The present invention relates to a process for producing a transistor using a structural body which includes a substrate, and a dummy gate laminate formed by laminating at least a high dielectric material film and a dummy gate made of silicon having a natural silicon oxide film on a surface thereof, a side wall disposed to cover a side surface of the laminate and an interlayer insulating film disposed to cover the side wall which are provided on the substrate, said process including an etching step using a specific etching solution and thereby replacing the dummy gate with an aluminum metal gate.

Abstract: A method for defining a template for directed self-assembly (DSA) materials includes patterning a resist on a stack including an ARC and a mask formed over a hydrophilic layer. A pattern is formed by etching the ARC and the mask to form template lines which are trimmed to less than a minimum feature size (L). Hydrophobic spacers are formed on the template lines and include a fractional width of L. A neutral brush layer is grafted to the hydrophilic layer. A DSA material is deposited between the spacers and annealed to form material domains in a form of alternating lines of a first and a second material wherein the first material in contact with the spacers includes a width less than a width of the lines. A metal is added to the domains forming an etch resistant second material. The first material and the spacers are removed to form a DSA template pattern.

Abstract: A method for manufacturing a semiconductor die may have the steps of:—Providing a semiconductor substrate;—Processing the substrate to a point where shallow trench isolation (STI) can be formed;—Depositing at least one underlayer having a predefined thickness on the wafer;—Depositing a masking layer on top of the underlayer;—Shaping the masking layer to have areas of predefined depths;—Applying a photolithograthy process to expose all the areas where the trenches are to be formed; and—Etching the wafer to form silicon trenches wherein the depth of a trench depends on the location with respect to the masking layer area.

Abstract: Embodiments of the present invention provide a contact structure for transistor. The contact structure includes a first epitaxial-grown region between a first and a second gate of, respectively, a first and a second transistor; a second epitaxial-grown region directly on top of the first epitaxial-grown region with the second epitaxial-grown region having a width that is wider than that of the first epitaxial-grown region; and a silicide region formed on a top portion of the second epitaxial-grown region with the silicide region having an interface, with rest of the second epitaxial-grown region, that is wider than that of the first epitaxial-grown region. In one embodiment, the second epitaxial-grown region is at a level above a top surface of the first and second gates of the first and second transistors.

Abstract: A method of manufacturing a semiconductor device includes forming a continuous silicate glass structure over a first surface of a semiconductor body, including a first part of the continuous glass structure over an active area of the semiconductor body and a second part of the continuous glass structure over an area of the semiconductor body outside of the active area. A first composition of dopants included in the first part of continuous glass structure differs from a second composition of dopants of the second part of the continuous glass structure.

Abstract: According to one embodiment, a pattern forming method includes forming a first guide layer on a processed film, phase-separating a first self-assembly material with the use of the first guide layer to form a first self-assembly pattern including a first polymer portion and a second polymer portion, selectively removing the first polymer portion, forming a second guide layer with the use of the second polymer portion, and phase-separating a second self-assembly material with the use of the second guide layer to form a second self-assembly pattern including a third polymer portion and a fourth polymer portion.

Abstract: A method of fabricating a patterned structure of a semiconductor device is provided. First, a substrate having a first region and a second region is provided. A target layer, a hard mask layer and a first patterned mask layer are then sequentially formed on the substrate. A first etching process is performed by using the first patterned mask layer as an etch mask so that a patterned hard mask layer is therefore formed. Spacers are respectively formed on each sidewall of the patterned hard mask layer. Then, a second patterned mask layer is formed on the substrate. A second etching process is performed to etch the patterned hard mask layer in the second region. After the exposure of the spacers, the patterned hard mask layer is used as an etch mask and an exposed target layer is removed until the exposure of the corresponding substrate.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The device includes first and second line pattern units configured to extend substantially parallel to one another in a first direction and alternately disposed such that end portions of the first and second line pattern units are arranged in a diagonal direction, third and fourth pattern units configured to respectively extend from the end portions of the first and second line pattern units in a second direction crossing the first direction, first contact pad units respectively formed in the third line pattern units disposed a first distance from the end portions of the first line pattern units, and fourth contact pad units respectively formed in the fourth line pattern units disposed a second distance from the end portions of the second line pattern units. Here, the second distance is different from the first distance.

Abstract: A method is provided for preparing a prepatterned substrate for use in DSA integration. In one example, the method includes removing a radiation-sensitive material pattern overlying a patterned cross-linked polystyrene copolymer layer by a) exposure to a solvent vapor, b) exposure to a liquid solvent, and c) repeating steps a)-b) until the radiation-sensitive material pattern is completely removed. In another example, the method includes removing a neutral layer by affecting removal of an underlying patterned radiation-sensitive material layer, which includes swelling the neutral layer; and removing the radiation-sensitive material pattern and the swollen neutral layer in portions by exposing the swollen layer and pattern to a developer solution. Swelling the neutral layer includes a) exposure to a solvent vapor; b) exposure to a liquid solvent; and c) repeating steps a)-b) until the neutral layer is sufficiently swollen to allow penetration of the developing solution through the swollen neutral layer.

Abstract: A method includes forming a first pattern having a first opening on a semiconductor substrate. The first opening is then filled. A second pattern of a first and second feature, interposed by the filled opening, is formed on the semiconductor substrate. Spacer elements then are formed on sidewalls of the filled opening, the first feature and the second feature. After forming the spacer elements, the material comprising first and second features is removed to form a second opening and a third opening. The filled opening, the second opening and the third opening are used as a masking element to etch a target layer of the substrate.

Abstract: Polycrystalline silicon (poly-Si) can be thoroughly removed without significant effect on adjacent oxides by an aqueous solution of ammonium hydroxide with smaller concentrations of hydrogen peroxide than are normally used in ammonia-peroxide mixture (APM) formulations used for cleaning. The etching selectivity of poly-Si relative to oxides can be widely tuned by varying the hydrogen-peroxide concentration. Compared to other formulations used to remove poly-Si dummy gates in logic-node fabrication, such as TMAH, these aqueous solutions are less hazardous to workers and the environment.

Abstract: A method of forming a target pattern includes forming a mandrel pattern on a substrate, the mandrel pattern having a line with a first dimension in a first direction and a second dimension in a second direction; forming a spacer around the mandrel pattern, the spacer having a first width; forming a cut pattern over the mandrel pattern and the spacer wherein the cut pattern partially overlaps the spacer on both sides of the line in the first direction; etching the mandrel pattern using the cut pattern as an etch mask, thereby defining a plurality of openings with sidewalls of the spacer, the cut pattern, and a portion of the mandrel pattern underneath the cut pattern; and reducing the first width of the spacer thereby to enlarge the plurality of openings.