Abstract: A semiconductor sensor having a thin-film structure body, in which thin-film structure is prevented from bending due to the internal stress distribution in the thickness direction, is disclosed. A silicon-oxide film is formed as a sacrificial layer on a silicon substrate, and a polycrystalline-silicon thin film is formed on the silicon-oxide film. Thereafter, phosphorus (P) is ion-implanted in the surface of the polycrystalline-silicon thin film, and thereby the surface state of the polycrystalline-silicon thin film is modified. A portion of distribution of stress existing in the thickness direction of the polycrystalline-silicon thin film is changed by this modification, and stress distribution is adjusted. By removal of the silicon-oxide film, a movable member of the polycrystalline-silicon thin film is disposed above the silicon substrate with a gap interposed therebetween.

Abstract: Porous semiconductor material in the form of at least partly crystalline silicon is produced with a porosity in excess of 90% determined gravimetrically, and voids, crazing and peeling are substantially not observable by scanning electron microscopy at a magnification of 7,000. The porous silicon is dried by supercritical drying. The silicon material has good luminescence properties together with good morphology and crystallinity.

Abstract: The present invention provides a method for forming a metallic wiring pattern, in which narrowing of a resist during patterning of a metallic film is prevented, adhesion of sputtered metallic film to the side walls of the resist is also prevented, and thereby a highly accurate metallic wiring pattern can be achieved.

Abstract: A composite body includes a semiconductor substrate having an oxide layer formed thereon and a nitride layer formed over the oxide layer. First and second deep trench configurations are formed in the composite body. To form a shallow isolation trench between the first and second deep trench configurations, intrinsic polysilicon upper layers of the first and second deep trench configurations and the nitride layer are planarized. A titanium layer is formed over the planarized composite body and caused to react with the intrinsic polysilicon upper layers to form first and second titanium silicide caps over the first and second deep trench configurations. A masking layer is formed over the composite body such that an opening exposes the region between the first and second deep trench configurations. An etching step that is selective to titanium silicide is then performed with the first and second deep trench caps serving as masks.

Abstract: A method of removing a resist layer formed on a substrate wherein the resist layer includes an ion-implanted upper region. The method includes hydrogenating the ion implanted upper region of the resist layer resulting in the hydrogenated ion-implanted upper region. The resist layer, including the hydrogenated ion-implanted upper region is then removed. A hydrogenation of the ion-implanted upper region may be performed by immersing the resist layer, including the ion-implanted upper region, into pressurized boiling water, and/or treating the ion-implanted upper region with pressurized water vapor.

Abstract: A intermetal level dielectrics with fluorinated (co)polymers of parylene (142) between metal lines (112-120), and vapor deposition method for the (co)polymerization followed by fluorination of the (co)polymers.

Abstract: Trench structures (12,32,35,46) are formed in single crystal silicon substrates (10,30) that have either a (110) or (112) orientation. A selective wet etch solution is used that removes only the exposed portions of the single crystal silicon substrates (10,30) that are in the (110) or (112) crystal planes. The trench structures (12,32,35,46) are defined by the {111} crystal planes in the single crystal silicon substrate (10,30) that are exposed during the selective wet etch process. Trench structures (32,35) can be formed on both sides of a single crystal silicon substrate (30) to form an opening (34). Opening (34) can be used as an alignment mark to align front side processing to backside and vice versa. Trench structures can also be use to form a microstructure (41,61) for a sensor (40,60).

Abstract: The etch profile of side surfaces of a gate electrode is improved by heat treating the gate electrode layer after nitrogen implantation and before etching to form the gate electrode. Nitrogen implantation at high dosages to prevent subsequent impurity penetration through the gate dielectric layer, e.g., B penetration, amorphizes the upper portion of the gate electrode layer resulting in concave side surfaces upon etching to form the gate electrode. Heat treatment performed after nitrogen implantation can restore sufficient crystallinity so that, after etching the gate electrode layer, the side surfaces of the resulting gate electrode are substantially parallel.

Abstract: A method for forming a patterned fluorine containing plasma etched layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a fluorine containing plasma etchable layer. There is then formed upon the fluorine containing plasma etchable layer a patterned photoresist layer. There is then etched through a fluorine containing plasma etching method while employing the patterned photoresist layer as a photoresist etch mask layer the fluorine containing plasma etchable layer to form a patterned fluorine containing plasma etched layer. The patterned fluorine containing plasma etched layer has a fluoropolymer residue layer formed thereupon. The fluorine containing plasma etch method employs a first etchant gas composition comprising a nitrogen trifluoride etchant gas.

Abstract: A method for fabricating shallow trench isolation using a gradient-doped polysilicon trench-fill and a chemical/mechanical polishing that improves substrate planarity was achieved. The method involves forming shallow trenches in a silicon substrate having a silicon nitride layer on the surface. After selectively oxidizing silicon exposed in the trenches, a second silicon nitride layer is deposited, and a composite polysilicon layer consisting of an undoped polysilicon layer and a gradient-doped polysilicon layer is deposited filling the trenches. The composite polysilicon layer is then chemical/mechanically polished back. The gradient-doped polysilicon layer improves the removal rate uniformity across the substrate (wafer) by removing the heavily doped regions at a faster rate than undoped or lightly doped regions. This results in improved global planarity which improves the polysilicon dishing in the trenches near the edge of the substrate.

Abstract: The present invention is related to a method for increasing utilzable surface area of a rugged polysilicon layer in a semiconductor device. The present method includes steps of: (a) providing a pre-grown rugged polysilicon layer which is composed of polysilicon with first dopants doped therein; (b) forming another polyslicon layer on the pre-grown rugged polysilicon layer; (c) removing a portion of the another polysilicon layer by an anisotropic etching process to expose an upper surface of the pre-grown rugged polysilicon layer; and (d) etching the resulting pre-grown rugged polysilicon layer which an etching selectivity ratio of the pre-grown rugged polysilicon layer to the another polysilicon layer being greater than one, to obtain the rugged polysilicon layer having increasing utilizable surface area. A semiconductor device containing the rugged polysilicon layer created according to the present invention can work well in a relatively dense and small semiconductor chip.

Abstract: The invention provides a method of fabricating corrosion free metal lines. The method involves forming a thin polymeric passivation layer 30 over the metal layer 20 immediately after the metal deposition and before any photolithographic or etching processes. The polymeric passivation layer 30 is formed using a F-containing gas plasma treatment. The passivation layer prevents corrosion of the metal layer before a metal etch. The passivation layer is preferably composed of a polymeric of C, O, and F and has a thickness in a range of between about 40 and 80 .ANG.. The passivation layer is formed using a F-containing plasma treatment at a power of between 225 and 275 W, a pressure between about 80 and 120 mtorr, a CHF.sub.3 flow between about 40 and 60 sccm and for a duration between about 10 to 30 seconds. Following this, the metal layer is patterned using photo and etch steps.

Abstract: A semiconductor processing method of forming a contact opening includes providing a substrate having a node location to which electrical connection is to be made. A layer comprising doped silicon dioxide is formed over the node location. Thereafter, both O.sub.2 and O.sub.3 are flowed simultaneously to the substrate along with tetraethylorthosilicate to the substrate to form a continuous layer comprising undoped silicon dioxide on the layer comprising doped silicon dioxide. During the flowing, a ratio of O.sub.3 to O.sub.2 flows is increased to form an outer portion of the continuous layer comprising undoped silicon dioxide to have a higher etch rate for a selected wet etch chemistry than an inner portion of said continuous layer. A common contact opening is anisotropically dry etched into the layer comprising undoped silicon dioxide and into the layer comprising doped silicon dioxide over the node location to outwardly expose the node location.

Abstract: A method for forming a highly dense quantum wire, the method comprising the steps of: depositing a dielectric mask having dielectric patterns on the top surface of a semiconductor (100) substrate; forming the dielectric patterns in parallel to a (011) orientation on the semiconductor substrate; exposing a (111)B side and a(111)B side by chemical etching a selected region between the patterns so that the semiconductor substrate has a dove-tail shape; forming a buffer layer on the dove-tail semiconductor substrate; forming the first barrier layer on the buffer layer; forming a well layer on the first barrier layer; and forming the second barrier layer on the well layer.

Abstract: In a method of introducing phosphorous from phosphorous oxychloride (POCl.sub.3) into an undoped gate polysilicon region formed as part of an integrated circuit structure, an initial MOS structure is developed utilizing conventional techniques through the formation of a layer of undoped polysilicon over thin gate oxide. A POCl.sub.3 layer is then formed over the undoped polysilicon and thermally annealed to drive phosphorous into the gate polysilicon to achieve a desired conductivity level. The phosphorous-rich organic layer is then cleaned from the surface of the POCl.sub.3 using sulfuric peroxide and the POCl.sub.3 layer is removed using a DI:HF solution to expose the surface of the doped polysilicon. After formation of a photoresist gate mask, arsenic, or another heavy ion species, is implanted into the exposed polysilicon to amorphized the exposed poly, thereby eliminating the polysilicon grain boundaries.

Abstract: A layer of silicon dioxide is formed conformably over a substrate having a surface with non-planar topography. The layer of silicon dioxide is then implanted with a species that affects the etch rate of the silicon dioxide when etched in an HF based etchant. The implant energy, dose, and direction are chosen such that only a selected portion of the layer of silicon dioxide is implanted with the implant species. The layer of silicon dioxide is then etched in an HF based etchant. The HF etchant etches both doped and undoped silicon dioxide, but the implanted silicon dioxide is removed at a faster rate or slower rate, depending on the implant species, than the unimplanted silicon dioxide. This allows the formation of specialized silicon dioxide structures due to the selectivity of the etch as between the implanted and unimplanted portions of the layer of silicon dioxide, without any damage to silicon.

Abstract: A method of fabricating an integrated circuit on a semiconductor substrate is provided including the steps of forming a tungsten silicide conductor structure having a nitride encapsulating layer on the substrate and disposing a doped nonconducting layer over the conductor structure. A self-aligned contact etch is performed wherein the etch is a selective etch of the conductor structure and the nonconducting layer. The selective etch preferentially removes material forming the nonconducting layer rather than material forming the conductor structure. The semiconductor layer is preferably doped with germanium but may also be doped with phosphorous or other known dopants. A germanium concentration of 5% to 25% provides the preferred increased selectivity of the etch. The nonconducting layer can be formed of SG, BPSG, BSG, PSG and TEOS.

Abstract: The invention relates to a method of forming trenches having different depths in a substrate of an IC using different refractory metal layers. The depths of the trenches can be changed by controlling the thicknesses of the refractory metal layers. The profiles of the trenches can be also changed by controlling operating parameters, such as temperature, reaction time, and so on. Thus, trenches having different depths are generated.

Abstract: A method for preparing a semiconductor member comprises:forming a substrate having a non-porous silicon monocrystalline layer and a porous silicon layer;bonding another substrate having a surface made of an insulating material to the surface of the monocrystalline layer; andetching to remove the porous silicon layer by immersing in an etching solution.

Abstract: A method of forming apparatus including a force transducer on a silicon substrate having an upper surface, the silicon substrate including a dopant of one of the n-type or the p-type, the force transducer including a cavity having spaced side walls and a diaphragm supported in the cavity, the diaphragm extending between the side walls of the cavity, comprising the steps of: a. implant in the substrate a layer of a dopant of the one of the n-type or the p-type; b. deposit an epitaxial layer on the upper surface of the substrate, the epitaxial layer including a dopant of the other of the n-type or the p-type; c. implant spaced sinkers through the epitaxial layer and into electrical connection with the layer of a dopant of the one of the n-type or the p-type, each of the sinkers including a dopant of the one of the n-type or the p-type; d. anodize the substrate to form porous silicon of the sinkers and the layer; e. oxidize the porous silicon to form silicon dioxide; and f.

Abstract: A structure and method for fabricating circuits which use field effect transistors (FETs), bipolar transistors, or BiCMOS (combined Bipolar/Complementary Metal Oxide Silicon structures), uses low temperature germanium gas flow to affect metals and alloys deposited in high aspect ratio structures including lines and vias. By using a germanium gas flow, germanium (Ge) will be introduced in a surface reaction which prevents voids and side seams and which also provides a passivating layer of CuGe. If a hard cap is needed for surface passivation or a wear-resistance application, the GeH.sub.4 gas followed by WF.sub.6 can be used to produce an in-situ hard cap and polish stop of W.sub.x Ge.sub.y, a tungsten-germanium alloy. Further, high aspect ratio vias/lines (aspect ratio of 3 or more) can be filled by utilizing low pressures and high temperatures (i.e., below 450.degree. C.) without degrading the underlying metals.

Abstract: A method for removing from a semiconductor substrate a partially fluorinated photoresist layer. There is first formed upon a semiconductor substrate a partially fluorinated photoresist layer. The partially fluorinated photoresist layer has a fluorinated surface layer of the partially fluorinated photoresist layer and an underlying non-fluorinated remainder layer of the partially fluorinated photoresist layer. The fluorinated surface layer of the partially fluorinated photoresist layer is then removed through a first etch method. The first etch method employs an oxygen containing plasma at a radio frequency power no greater than about 500 watts and a temperature no greater than about 120 degrees centigrade. Finally, the underlying non-fluorinated remainder layer of the partially fluorinated photoresist layer is removed through a second etch method.

Abstract: A process is disclosed for forming trenches having high surface-area sidewalls with undulating profiles. Such trenches are formed by first implanting multiple vertically separated layers of dopant in a substrate beneath a region where the trench is to be formed. Next, the trench is formed under conditions chosen to selectively attack highly doped substrate regions (i.e., substrate regions where the dopant has been implanted). The resulting trench sidewalls will have undulations corresponding to the positions of the implanted regions. In one case, the implanted layers contain germanium ions, and a trench is aniostropically etched through the layers of germanium. Thereafter, the trench is subjected to oxidizing conditions to form regions of germanium oxide. Finally, the trench is exposed to an aqueous solvent which dissolves germanium oxide, disrupting the silicon lattice, and leaving gaps or undulations in the sidewall.

Abstract: This invention provides a method for removing metal etch residue of silicon nodules, resulting from a small percentage of silicon in the metal, without causing overetch damage to the photoresist pattern, the metal electrode pattern, or to dielectric layers. The metal conductor layer is partially etched leaving from 20 to 80 percent of the original thickness. Any residue of silicon nodules formed during this partial etching is then removed using ion bombardment. The remainder of the metal conductor layer is then etched. A short overetch period is used to remove any remaining residue of silicon nodules. The overetch period is short and there is no deterioration of the photoresist or exposed edges of the electrode pattern.

Abstract: There is proposed a process for performing (quasi-) anisotropic etching on a silicon-based material without using plasma. The process consists of irradiating a polycrystalline or single-crystalline silicon film or substrate with a beam of accelerated hydrogen ions, silicon ions, or rare gas ions, so that the crystalline silicon is made amorphous. Then, the amorphous silicon is placed in an atmosphere of fluorinated halogen. Since the etching rate of fluorinated halogen for amorphous silicon is greater than that for polycrystalline or single-crystalline silicon, etching takes place selectively at the area which has been irradiated with a beam of accelerated hydrogen ions, silicon ions, or rare gas ions. The selective etching permits (quasi-) anisotropic etching instead of sideward isotropic etching.

Abstract: A process is disclosed for fabricating a CMOS structure with ESD protection. The outside transistors are covered with a protective oxide layer which is so masked as to cover the areas of the respective source and drain regions adjoining the field-oxide regions and the gate regions. The protective oxide layer is then subjected to a heat treatment, after which a siliciding process is carried out.

Abstract: A self-supporting thin film of silicon single crystal is produced essentially by the steps of implanting boron ions in a silicon single crystal substrate from one major surface thereof to form a high impurity concentration layer having a high boron concentration in the substrate; heating the silicon single crystal substrate formed with the high impurity concentration layer in an atmosphere containing oxygen to form an oxide film on the surface of the single crystal substrate and make the high impurity concentration layer resistant to etching; masking all of the oxide film surface other than that at the center region on the surface opposite from that implanted with boron ions and then exposing the high impurity concentration layer by high-speed mask etching followed by selective etching; and removing the oxide film.

Abstract: There is provided a method of fabricating a storage capacitor. A bottom semiconductor film having an electrical conductivity is formed for subsequent formation of a phase splitting glass film on the bottom semiconductor film. The phase splitting glass film is subjected to a heat treatment to allow the phase splitting glass film to be split into at least two different glass films which have different components. The phase splitting glass film is subjected to an etching in which one of the glass films has a higher etching rate than an etching rate of another of the glass films so that only the glass film having the higher etching rate is removed, while the other glass film remains thereby a mask pattern including the remaining other glass film is formed. The bottom semiconductor film is subjected to a dry etching using the mask to form trench grooves defined by trench pillars in the bottom semiconductor film. A dielectric film is formed on surfaces of the trench grooves and trench pillars.