Abstract: Disclosed are methods for facilitating concurrent formation of copper vias and memory element structures. The methods involve forming vias over metal lines and forming copper plugs, wherein the copper plugs comprise memory element film forming copper plugs (memE copper plugs) and non-memory element forming copper plugs (non-memE copper plugs), forming a tantalum-containing cap over an upper surface of non-memE copper plugs, and depositing memory element films. The tantalum-containing cap prevents the formation of the memory element films in the non-memE copper plugs. The subject invention advantageously facilitates cost-effective manufacturing of semiconductor devices.

Abstract: A resist layer is deposited a resist layer on a first layer of a layered stack. The stack also includes a second layer below the first layer. The resist layer is processed with a lithographic method to achieve a first structured resist layer. At least a part of the first structured resist layer is trimmed to achieve a second structured resist layer having at least in parts a structure with a critical dimension smaller than obtainable by processing the resist with a lithographic method. The first layer is selectively removed from the second layer in the areas not covered by the second structured resist layer. The second layer is modified by implantation to become a layer with defined selectivity to the non-modified material. The remains of the first layer are removed. The non-modified structures of the second layer are removed to create a hardmask layer by the remaining layer. The layered stack is further structured with the hardmask layer.

Abstract: In one embodiment, a method includes providing a semiconductor substrate that includes a memory container having a double-sided capacitor. The method also includes vapor phase etching a layer adjacent to the side wall of the memory container with a vapor having a surface tension lowering agent.

Abstract: The present invention relates to a method for fabricating a semiconductor device. The method comprises the steps of: forming a gate line on a semiconductor substrate; forming a buffer layer and a spacer nitride film on the entire surface of the substrate including the gate line; selectively etching the buffer layer and the spacer nitride film in such a manner that they remain on both sides of the gate line; performing an ion implantation process using the remaining buffer layer and spacer nitride film as a barrier film to form junction regions in the semiconductor substrate at both sides of the gate line; forming an interlayer insulating film on the entire upper portion of the resulting substrate; selectively removing the interlayer insulating film to form contact holes exposing the upper surface of the junction regions; and forming contact plugs in the contact holes.

Abstract: The present invention features a method of patterning a substrate that includes forming, on the substrate, a multi-layer film with a surface, an etch rate interface and an etch-differential interface. The etch-differential interface is defined between the etch rate interface and the surface. A recorded pattern is transferred onto the substrate defined, in part, by the etch-differential interface.

Abstract: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

Abstract: A method for fabricating recording head sliders made from silicon substrates, is described. A Silicon wafer with a SiO2 overcoat is provided, and a layer of material which is resistant to Deep Reactive Ion Etching (DRIE) is deposited on the SiO2 overcoat. A patterned layer of material which is resistant to Reactive Ion Etching (RIE) is deposited on the layer of DRIE-resistant material to form a primary mask. RIE is used through the primary mask to pattern the SiO2 overcoat layer and the layer of DRIE-resistant material. The primary mask is then removing to expose the layer of DRIE-resistant material which has now been patterned to form a secondary mask. DRIE is then used through the secondary mask to cut the Si wafer into pieces. Finally, the secondary mask is removed.

Abstract: A method is provided for fabricating a semiconductor device that includes a suspended micro-system. According to the method, a silicon porous layer is formed above a silicon substrate, and the silicon porous layer is oxidized. An oxide layer is deposited, and a first polysilicon layer is deposited above the oxide layer. The first polysilicon layer, the oxide layer, and the silicon porous layer are selectively removed. A nitride layer is deposited, and a second polysilicon layer is deposited. The second polysilicon layer, the nitride layer, the first polysilicon layer, and the oxide layer are selectively removed. The silicon porous layer is removed in areas made accessible by the previous step. Also provided is a semiconductor device that includes a suspended structure fixed to at least two walls through a plurality of hinges, with the suspended structure including an oxide layer, a first polysilicon layer, a nitride layer, and a second polysilicon layer.

Abstract: A wafer has a trench, a STI layer formed in the trench, an HfO2-containing gate dielectric covering the wafer and the STI layer, a gate electrode formed on the HfO2-containing gate dielectric, and at least a spacer formed beside the gate electrode. The wafer is preheated and a bromine-rich gas plasma is provided to remove portions of the HfO2-containing gate dielectric.

Abstract: A method for forming a recess. The method includes providing a substrate with two protrusions having a first side wall and a second side wall opposite to the first side wall disposed above the substrate, conformally forming a mask layer on the substrate and the protrusions, tilt implanting the mask layer with a first angle using a first implanting mask adjacent to the first side wall of the protrusions, tilt implanting the mask layer with a second angle using a second implanting mask adjacent to the second side wall of the protrusions, removing implanted portions of the mask layer to form a patterned mask layer, and etching the substrate using the patterned mask layer, thereby forming a recess, wherein distances from the recess to the two protrusions, respectively, are different.

Abstract: A thin layer of single-crystal silicon is produced by forming first trenches in a silicon substrate having (111) orientation; forming narrower second trenches at the bases of the trenches; anisotropically etching lateral channels (4) from the second trenches, until adjacent etch fronts (16) substantially meet; and detaching said layer from the substrate. The trenches may be arranged so that the resultant layer has rows of slots, whit the slots in adjacent rows being mutually offset. Solar cells may be formed on strips (5) between the trenches, having lengths of more than 50 mm, widths of up to 5 mm, and thicknesses of less than 100 microns, and having two electrical contacts on the same face (6) of each strip (5).

Abstract: According to a method for producing a solid body (1) including a microstructure (2), the surface of a substrate (3) is provided with a masking layer (6) that is impermeable to a substance to be applied. The substance is then incorporated into the substrate regions not covered by the masking layer (6). A heat treatment is used to diffuse the substance into a substrate region covered by the masking layer (6) such that a concentration gradient of the substance is created in the substrate region covered by the masking layer (6), proceeding from the edge of the masking layer (6) inward with increasing distance from the edge. The masking layer (6) is then removed to expose the substrate region under this layer, and a near-surface layer of the substrate (3) in the exposed substrate region is converted by a chemical conversion reaction into a coating (9) which has a layer thickness profile corresponding to the concentration gradient of the substance contained in this near-surface layer.

Abstract: A semiconductor device is made by patterning a conductive layer for forming gates of transistors. The process for forming the gates has a step of patterning photoresist that overlies the conductive layer. The patterned photoresist is trimmed so that its width is reduced. Fluorine, preferably F2, is applied to the trimmed photoresist to increase its hardness and its selectivity to the conductive layer. Using the trimmed and fluorinated photoresist as a mask, the conductive layer is etched to form conductive features useful as gates. Transistors are formed in which the conductive pillars are gates. Other halogens, especially chlorine, may be substituted for the fluorine.

Abstract: A liquid crystal display device includes a plurality of gate lines and data lines on a first substrate defining a plurality of pixel regions, a thin film transistor within the pixel regions, a pixel electrode within the pixel regions, and at least one TiOx layer provided with the thin film transistor.

Abstract: A method of fabricating an integrated circuit, having copper metallization formed by a dual damascene process, is disclosed. A layered insulator structure is formed over a first conductor (22), within which a second conductor (40) is formed to contact the first conductor. The layered insulator structure includes a via etch stop layer (24), an interlevel dielectric layer (26), a trench etch stop layer (28), an intermetal dielectric layer (30), and a hardmask layer (32). The interlevel dielectric layer (26) and the intermetal dielectric layer (30) are preferably of the same material. A via is partially etched through the intermetal dielectric layer (30), and through an optional trench etch stop layer (28). A trench location is then defined by photoresist (38), and this trench location is transferred to the hardmask layer (32).

Abstract: The present invention provides, in one embodiment, a method method of monitoring a process for forming a nitridated oxide gate dielectric. A nitrided oxide dielectric layer is formed on a test substrate (110). The nitrided oxide dielectric layer is exposed to an etch process (120). A change in a property of the nitrided oxide dielectric layer is measured as a function of the etch process (130). Other embodiments advantageously incorporate the method into methods for making semiconductor devices and integrated circuits.

Abstract: A method for the production of airgaps in a semiconductor device and device produced therefrom. The formation of airgaps is accomplished, in part, by chemically and/or mechanically changing the properties of a first dielectric layer locally, such that at least part of said first dielectric layer is converted locally and becomes etchable by a first etching substance. The local conversion of the dielectric material may be achieved during anisotropic etching of the material in oxygen containing plasma or ex-situ by performing an oxidizing step (e.g., a UV/ozone treatment or supercritical carbon dioxide with addition of an oxidizer). Formation of airgaps is achieved after creation of conductive lines and, alternatively, a barrier layer by a first etching substance. The airgaps are formed in a dual damascene structure, near the vias and/or the trenches of the damascene structure.

Abstract: A method of forming a silicon-germanium layer on an insulator includes depositing a layer of silicon-germanium on a silicon substrate to form a silicon/silicon-germanium portion; implanting hydrogen ions into the silicon substrate between about 500 ? to 1 ?m below a silicon-germanium/silicon interface; bonding the silicon/silicon-germanium portion to an insulator substrate to form a couplet; thermally annealing the couplet in a first thermal annealing step to split the couplet; patterning and etching the silicon-germanium-on-insulator portion to remove portions of the silicon and SiGe layers; etching the silicon-germanium-on-insulator portion to remove the remaining silicon layer; thermally annealing the silicon-germanium-on-insulator portion in a second annealing step to relaxed the SiGe layer; and depositing a layer of strained silicon about the SiGe layer.

Abstract: The subject invention pertains to a method and apparatus for etching copper (Cu). The subject invention can involve passing a halide gas over an area of Cu such that CuX, or CuX and CuX2, are formed, where X is the halide. Examples of halides which can be utilized with the subject matter include, but are not necessarily limited to, Cl, Br, F, and I. Once the CuX, or CuX and CuX2, are formed the subject invention can then involve passing a reducing gas over the area of Cu for a sufficient time to etch away at least a portion of the CuX, or CuX2, respectively. With respect to a specific embodiment in which CuX and CuX2 are produced when the halide gas is passed over the area of Cu, the reducing gas can be passed until essentially all of the CuX2 is etched and at least a portion of the CuX is etched. Examples of reducing gases which can be utilized with the subject invention include, but are not necessarily limited to, hydrogen gas and hydrogen gas plasma.

Abstract: A cleaning process for cleaning the surface of a substrate is disclosed, wherein the surface comprises portions of a dielectric material and portions of a conductive material. According to the method disclosed, the temperature at the surface of the substrate is kept below a predefined value during the actual cleaning step in a reactive and/or inert plasma ambient, such as an argon gas ambient, wherein the predefined value corresponds to the surface temperature at which agglomeration of the conductive material occurs.

Abstract: A method for etching a feature in an etch layer through a photoresist mask over a substrate is provided. A substrate with an etch layer disposed below a photoresist mask is placed in a process chamber. The photoresist mask is conditioned, wherein the conditioning comprises providing a conditioning gas comprising a hydrogen containing gas with a flow rate and at least one of a fluorocarbon and a hydrofluorocarbon with a flow rate to the process chamber; and energizing the conditioning gas to form the conditioning plasma. The conditioning plasma is stepped. An etch plasma is provided to the process chamber, wherein the etch plasma is different than the conditioning plasma. A feature is etched in the etch layer with the etch plasma.

Abstract: Preferably using a positive resist, a resist ridge (20) is formed in a photosensitive resist (16) applied on a semiconductor wafer (1) above a hard mask layer (12). The resist ridge (20) serves as a mask for a subsequent implantation step (46). This makes use of an effect whereby the material of the hard mask layer (12), in a part (122) shaded by the resist ridge (20), can be etched out selectively with respect to the implanted part (121). The consequently patterned hard mask layer is used as an etching mask with respect to an underlying layer or layer stack (102–104) that is actually to be patterned. From the resist ridge (10) that has been formed as a line in the photosensitive resist (16), in a type of tone reversal, an opening (24) has been formed in the hard mask layer and a trench (26) has been formed in the layer/layer stack (102–104). According to the invention, the width (51, 52) of the resist ridge (20) is reduced by exposing the resist ridge (20) to an oxygen plasma (42).

Abstract: Methods of forming an amorphous etch stop layer by implanting a substrate with an element that is electrically neutral within the substrate are described. The use of elements that are electrically neutral within the substrate prevents electrical interference by the elements if they diffuse to other areas within the substrate. The amorphous etch stop layer may be used as a hard mask in the fabrication of transistors or other devices such as a cantilever.

Abstract: A method for anisotropically and selectively removing a dielectric thin film layer from a substrate layer is disclosed, wherein the dielectric layer is subjected to ion implantation prior to wet etching. This method may be applied adjacent to a structure such as a gate electrode within a microelectronic structure to prevent undercutting of the dielectric material to be preserved between the gate electrode and the substrate layer, as may happen with more isotropic etching techniques.

Abstract: A method of patterning a layer of high-k dielectric material is provided, which may be used in the fabrication of a semiconductor device. A first etch is performed on the high-k dielectric layer. A portion of the high-k dielectric layer being etched with the first etch remains after the first etch. A second etch of the high-k dielectric layer is performed to remove the remaining portion of the high-k dielectric layer. The second etch differs from the first etch. Preferably, the first etch is a dry etch process, and the second etch is a wet etch process. This method may further include a process of plasma ashing the remaining portion of the high-k dielectric layer after the first etch and before the second etch.

Abstract: Method for the production of airgaps in a semiconductor device, the semiconductor device comprising a stack of layers, the stack of layers comprising at least one iteration of a sub-stack of layers.

Abstract: A self-correcting etching (SCORE) process for fabricating microstructure is provided. The SCORE process of the present invention is particularly useful for reducing preselected features of a hard mask without degrading the variation of the critical dimension (CD) within each wafer. Alternatively, the CD variation of the hard mask features' produced during printing can be substantially reduced by applying SCORE. Hence, ultra-sub-lithographic features (e.g., nanostructures) can be reliably fabricated. Consequently, the method of the present invention can be used to increase the circuit performance, while improving the manufacturing yield.

Abstract: A method for creating semiconductor devices by etching a layer over a wafer is provided. A photoresist layer is provided on a wafer. The photoresist layer is patterned. The wafer is placed in a process chamber. The photoresist is hardened by providing a hardening plasma containing high energy electrons in the process chamber to harden the photoresist layer, wherein the high energy electrons have a density. The layer is etched within the process chamber with an etching plasma, where a density of high energy electrons in the etching plasma is less than the density of high energy electrons in the hardening plasma.

Abstract: A method of masking and etching a semiconductor substrate includes forming a layer to be etched over a semiconductor substrate. An imaging layer is formed over the layer to be etched. Selected regions of the imaging layer are removed to leave a pattern of openings extending only partially into the imaging layer. After the removing, the layer to be etched is etched using the imaging layer as an etch mask. In one implementation, an ion implant lithography method of processing a semiconductor includes forming a layer to be etched over a semiconductor substrate. An imaging layer of a selected thickness is formed over the layer to be etched. Selected regions of the imaging layer are ion implanted to change solvent solubility of implanted regions versus non-implanted regions of the imaging layer, with the selected regions not extending entirely through the imaging layer thickness.

Abstract: A method for reducing the loss of silicon in a plasma assisted photoresist etching process including providing a silicon substrate including a polysilicon gate structure; masking a portion of the silicon substrate with photoresist to carry out an ion implantation process for forming source and drain regions; carrying out an ion implantation process; and, removing the photoresist according to at least one plasma assisted process wherein the at least one plasma assisted process comprises fluorine containing, oxygen, and hydrogen containing plasma source gases.

Abstract: A method for preventing formation of photoresist scum. First, a substrate on which a dielectric layer is formed is provided. Next, a non-nitrogen anti-reflective layer is formed on the dielectric layer. Finally, a photoresist pattern layer is formed on the non-nitrogen anti-reflective layer. During the formation of the photoresist pattern layer, the non-nitrogen anti-reflective layer does not react with the photoresist pattern layer, thus not forming photoresist scum. This prevents undesired etching profile and critical dimension (CD) change due to presence of photoresist scum. The non-nitrogen anti-reflective layer can be silicon-rich oxide (SiOx) or hydrocarbon-containing silicon-rich oxide (SiOxCy:H).

Abstract: Some embodiments provide a memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with charge carriers of the second type. According to some embodiments, the body region, the source region, and the drain region are oriented in a first direction, the body region and the source region form a first junction, and the body region and the drain region form a second junction. Moreover, a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased. Some embodiments further include a transistor oriented in a second direction, wherein the second direction is not parallel to the first direction.

Abstract: A method of removing a hard mask layer from a patterned layer formed over an underlying layer, where the hard mask layer is removed using an etchant that detrimentally etches the underlying layer when the underlying layer is exposed to the etchant for a length of time typically required to remove the hard mask layer, without detrimentally etching the underlying layer. The hard mask layer is modified so that the hard mask layer is etched by the etchant at a substantially faster rate than that at which the etchant etches the underlying layer. The hard mask layer is patterned. The patterned layer is etched to expose portions of the underlying layer. Both the hard mask layer and the exposed portions of the underlying layer are etched with the etchant, where the etchant etches the hard mask layer at a substantially faster rate than that at which the etchant etches the underlying layer, because of the modification of the hard mask layer.

Abstract: After forming an insulating film on an underlying layer, a resist pattern is formed on the insulating film. The insulating film is etched by using the resist pattern as a mask, thereby forming an insulating film pattern. Without removing the resist pattern, exposed portions of the underlying layer and the insulating film pattern are subjected to a plasma treatment, cleaning, a heat treatment or the like, so that a deposition grown during the formation of the insulating film pattern can be removed. Thereafter, the underlying layer is etched by using at least the insulating film pattern as a mask. As a result, even when a strict pattern rule is employed, pattern defects can be prevented from being caused in etching a multi-layer film.

Abstract: In one embodiment, a method of forming a multijunction solar cell having lattice mismatched layers and lattice-matched layers comprises growing a top subcell having a first band gap over a growth semiconductor substrate. A middle subcell having a second band gap is grown over the top subcell, and a lower subcell having a third band gap is grown over the middle subcell. The lower subcell is substantially lattice-mismatched with respect to the growth semiconductor substrate. The first band gap of the top subcell is larger than the second band gap of the middle subcell. The second band gap of the middle subcell is larger than the third band gap of the lower subcell. A support substrate is formed over the lower subcell, and the growth semiconductor substrate is removed. In various embodiments, the multijunction solar cell may further comprise additional lower subcells. A parting layer may also be provided between the growth substrate and the top subcell in certain embodiments.

Abstract: The method for fabricating a micro machine comprises the step of burying an oxide film 54 in a first semiconductor substrate 6, the step of bonding the first semiconductor substrate to the second semiconductor substrate with an insulation film 18 therebetween, the step of forming a first mask 66 with an opening in a first region and a second region on both sides of the first region, the step of etching the first semiconductor substrate with a first mask 66 and an oxide film 54 as a mask to thereby form a spring portion 20a integral with the first semiconductor substrate between the oxide film and the insulation film to thereby form a torsion bar including the spring portion, the step of forming a second mask 74 with an opening in the first region and the second region, the step of etching the second semiconductor substrate by using the second mask 74, and the step of etching the insulation film 18 in the first region and the second region. The thickness of the torsion bar can be easily controlled.

Abstract: In a method of fabricating a flash memory, a tunneling dielectric layer, a first conductive layer and a mask layer are sequentially formed on a substrate to form a gate structure. Buried source/drain regions are then formed in the substrate between the strips. The strips are further patterned into floating gate structures. An insulation layer is formed sideways adjacent to the gate structure. The insulation layer has a top surface lower than a top surface of the first conductive layer of the gate structure. The mask layer is removed, and an additional conductive layer is formed on the first conductive layer in a manner to extend over the adjacent insulation layer. The first and additional conductive layers form a floating gate. A gate dielectric layer is formed on the floating gate, and a control gate is formed on the gate dielectric layer.

Abstract: A semiconductor device includes first and second polysilicon areas on a chip. The first polysilicon area corresponds to circuit elements of the semiconductor device. At least some of the first polysilicon corresponds to polysilicon gates. At least some of the second polysilicon area comprises contacts of the semiconductor device. Metal covers the polysilicon contacts.

Abstract: A method for etching trenches having different depths on a semiconductor substrate includes providing a mask with first and second openings. The first and second openings are located where corresponding first and second trenches are to be etched. A slow-etch region, made of a slow-etch material, is provided above the substrate at a location corresponding to the second opening. When exposed to a selected etchant, the slow-etch material is etched at a rate less than the rate at which the semiconductor substrate is etched when exposed to the selected etchant.

Abstract: A method for precise thinning to form a recess to a precise depth in a crystalline silicon layer, which can be used to form various devices, such as MOSFET devices, includes the following steps. Form a patterning mask with a window therethrough over the top surface of the silicon layer. Form an amorphized region in the top surface of the silicon layer below the window. Selectively etch away the amorphized region of the silicon layer to form a recess in the surface of the silicon layer, and remove the patterning mask. In the case of an MOSFET device form a hard mask below the patterning mask with the window extending therethrough. Then create sidewall spacers in the window through the hard mask and form a gate electrode stack in the window. Then remove the hard mask and form the source/drain extensions, halos and regions plus silicide and complete the MOSFET device.

Abstract: Defective contact plug fills can be detected by applying an etching solution, which in some embodiments preferentially etches in the <111> direction. The etching solution is some embodiments may also produce a characteristic type of undercutting underneath the contact plug fill. Contact plug fills with defects in them have undercutting underneath as a result of the etchant exposure, while defective contact plug fills have no such undercutting. The contact plug fills that are now undercut by etching exposure are unable to dissipate surface charge or surface applied potential and can be detected using voltage contrast methods or conventional electrical testing techniques, for example.

Abstract: The present invention is provided to form a trench in a semiconductor device, wherein by performing an ion implanting process to an area of a semiconductor substrate in which the trench would be formed to cause lattice defects in the area before forming the trench, an etching speed of the area is increased in subsequent trench forming processes. As a result, it is possible to prevent micro trenches from being formed in edge portions of patterns and to suppress a micro loading effect to be generated depending upon pattern sizes.

Abstract: A method for removing carbon from or stripping a TERA layer. The method includes exposing the TERA layer to a plasma containing an effective amount of nitrogen, and, optionally, oxygen or fluorine. The method is compatible with fluorine based etching systems, and may thus be performed in the same etching system as other etching steps. For example, the method may be performed in the same system as a fluorine based plasma etch for oxide or nitride. The invention includes the method of stripping a TERA layer, etching an oxide layer, and etching a nitride layer in situ in the same etching system. The method is performed at low ion energies to avoid damaging oxide or nitride layers under the TERA film and to provide good selectivity.

Abstract: The present invention is directed to methods for editing copper features embedded within an organic body by exposing at least a portion of a top surface of the copper feature, forming a mill box there-over and then simultaneously milling both the copper feature and any organic material exposed through the mill box in a single step using an ion beam in combination with a XeF2 gas for a dwell time of at least 10 milliseconds. The invention dramatically increases the efficiency of Focused Ion Beam milling of copper features embedded in organic layers by milling these features in a gas-depleted environment at significantly increased dwell time while avoiding the problems of graphitization, destruction of the organic layer and metal redeposition.

Abstract: A method for treating a film of material, which can be defined on a substrate, e.g., silicon. The method includes providing a substrate comprising a cleaved surface, which had a porous silicon layer thereon. The substrate may have a distribution of hydrogen bearing particles defined from the cleaved surface to a region underlying said cleaved surface. The method also includes increasing a temperature of the cleaved surface to greater than about 1,000 Degrees Celsius while maintaining the cleaved surface in a etchant bearing environment to reduce a surface roughness value by about fifty percent and greater. Preferably, the value can be reduced by about eighty or ninety percent and greater, depending upon the embodiment.

Abstract: A first method of reducing semiconductor device substrate effects comprising the following steps. O+ or O2+ are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices.

Abstract: Disclosed is a process for fabricating luminescent porous material, the process comprising pre-treating a substrate (e.g. crystalline silicon) with laser radiation (e.g from a Nd:YAG laser) in a predetermined pattern followed by exposing the irradiated substrate to a chemical stain etchant (e.g. HF:HNO3:H2O) to produce a luminescent nanoporous material. Luminescent porous material having a luminescence maximum greater than about 2100 meV may be produced by this method. Such nanoporous materials are useful in optoelectronic and other semiconductor devices.

Abstract: A high-K thin film patterning solution is disclosed to address structural and process limitations of conventional patterning techniques. Subsequent to formation of gate structures adjacent a high-K dielectric layer, a portion of the high-K dielectric layer material is reduced, preferably via exposure to hydrogen gas, to form a reduced portion of the high-K dielectric layer. The reduced portion may be selectively removed utilizing wet etch chemistries to leave behind a trench of desirable geometric properties.

Abstract: A method of making a semiconductor device 10 by forming a first dielectric layer 140 on a substrate, etching through the first dielectric layer to form a trench 150 having a channel region 135 on a sidewall 160 of the trench, and laterally removing a portion of the first dielectric layer adjacent to the sidewall of the trench above the channel region for defining a source region 280 of the semiconductor device.

Abstract: Disclosed is a method for forming an isolation region in a semiconductor device. Pad oxide and nitride films are sequentially formed on a silicon substrate. Photoresist pattern is formed on the pad nitride film, the photoresist pattern. Respectively predetermined parts of the pad oxide and nitride films and the silicon substrate are etched by using the photoresist pattern as a mask to form a shallow trench. Field implant process is performed on a lower surface of the shallow trench, by using the photoresist pattern as a mask to form a field stop implant film. Photoresist pattern is removed. The inside of the shallow trench is washed. The inside of the shallow trench is thermally enlarged to form a first oxide film. Second oxide film is deposited on the first oxide film and chemical mechanical polishing process for the second oxide film is performed to form the isolation region.