Abstract: The present invention is provided to a method of manufacturing a flash memory, comprising the steps of: performing an ion implantation process for adjusting a threshold voltage on a semiconductor substrate; forming a tunnel oxide film, a first polysilicon film and a pad oxide film on the semiconductor substrate, sequentially; etching the pad oxide film, the first polysilicon film, the tunnel oxide film and the semiconductor substrate to form a trench defining an active region and a device isolation region; forming a side wall oxide film on the side wall of the trench while suppressing diffusion of the implanted ion for adjusting the threshold voltage into the device isolation region to the maximum extent; performing an ion implantation process on the side wall of the trench and the active region adjacent to the device isolation region in order to compensate for ions for adjusting a threshold voltage which have diffused from the active region into the side wall oxide film; and forming a device isolation film b

Abstract: Etch uniformity is improved in that a specified material layer to be etched is exposed to an ion beam so as to implant an ion species, wherein at least one implantation parameter is varied in conformity with local etch rates of the specified material layer. In this way, etch non-uniformities, induced by tool non-uniformities and recipe specific characteristics, may be significantly reduced.

Abstract: A method of determining the endpoint of an etch layer in a semiconductor element fabrication, wherein said element is comprised of at least a first material layer, a second material layer on said first material layer, said endpoint determining method comprises the steps of (i) determining the total emission intensity wavelength of the first material layer; (ii) determining the total emission intensity wavelength of the second material layer; (iii) plotting the scalar of the wavelength differential of the upper and lower layers; and (iv) choosing the highest peak of wavelength differential as the best range of endpoint detection wavelength.

Abstract: A method for forming a gate electrode in the semiconductor device is disclosed. The disclosed methods for forming a gate electrode in a semiconductor includes forming a polysilicon film and a metal silicide film sequentially on an upper portion of a semiconductor substrate; performing an annealing process to crystallize the metal silicide film, so that etch rate of the crystallized metal silicide film is similar to that of the polysilicon film; and forming a gate electrode by performing an etching process at one time on the metal silicide film and the polysilicon film using the similar etch rates of the crystallized metal silicide film and the polysilicon film. According to the disclosed methods, the tungsten silicide film is crystallized by an annealing process and the polysilicon film and the crystallized tungsten suicide film are etched at one time to prevent any formation of recesses of the polysilicon film, so that it is possible to form the gate electrode pattern having the vertical profile.

Abstract: A process for manufacturing a membrane sensor over a silicon substrate, preferably a thermal membrane sensor. A thin layer of silicon carbide or silicon nitride is deposited over an area of porous silicon formed in the surface of the substrate, and then openings that extend as far as the layer of porous silicon are formed in the silicon carbide or silicon nitride layer via a dry etching process. Next, semiconductor structures and conductor path structures are implanted into the upper surface of the membrane layer via lithographic steps, and then the sacrificial layer of porous silicon is removed using a suitable solvent such as ammonia. Thus an empty space that thermally isolates the sensor membrane from the substrate is created beneath the membrane layer.

Abstract: A method of forming a copper oxide film includes forming a copper oxide film including an ammonia complex by causing a mixed solution of aqueous ammonia and aqueous hydrogen peroxide, which has been adjusted to have pH of 8 to 10 or pH of 9 to 10, to contact a surface of a copper film. A method of fabricating a semiconductor device includes burying a copper film to be a wiring or a contact wiring in a wiring groove or a contact hole formed in a surface of an insulating film formed on a semiconductor substrate, or in both the wiring groove and the contact hole, forming a copper oxide film including an ammonia complex on a surface of the copper film by using the copper oxide film forming method, and removing the copper oxide film from the copper film using acid or alkali.

Abstract: An integrated circuit fabrication process is disclosed herein. The process includes exposing a photoresist layer to a plasma, and transforming the top surface and the side surfaces of the photoresist layer to form a hardened surface. The process further includes etching the substrate in accordance with the transformed feature, wherein an etch stability of the feature is increased by the hardened surface. The photoresist layer is provided at a thickness less than 0.25 &mgr;m, for use in deep ultraviolet lithography, or for use in extreme ultraviolet lithography.

Abstract: A process for fabricating a complimentary metal oxide semiconductor (CMOS), device featuring composite insulator spacer shapes which allow P channel (PMOS), short channel effects to be minimized, and allow reductions in resistance for N channel (NMOS), source/drain extension regions to be realized, has been developed. The process features initial composite insulator spacers formed in the sides of gate structures after definition of the NMOS and PMOS source/drain extension regions. The initial composite insulator spacer, comprised of an underlying silicon oxide component, an L-shaped silicon nitride component, and an overlying doped oxide component, is then used for definition of the PMOS heavily doped source/drain region, allowing for adequate space between the heavily doped source/drain and channel regions, thus reducing the risk of short channel effects.

Abstract: A silicon nitride comprising layer formed over a semiconductor substrate includes Al, Ga or a mixture thereof. A silicon dioxide comprising layer is formed proximate thereto. The silicon dioxide comprising layer is removed substantially selectively relative to the silicon nitride comprising layer, with the Al, Ga or a mixture thereof enhancing selectivity to the silicon nitride comprising layer during the removal. A substantially undoped silicon dioxide comprising layer formed over a semiconductor substrate includes B, Al, Ga or mixtures thereof. A doped silicon dioxide comprising layer is formed proximate thereto. The doped silicon dioxide comprising layer is removed substantially selectively relative to the substantially undoped silicon dioxide comprising layer, with the B, Al, Ga or mixtures thereof enhancing selectivity to the substantially undoped silicon dioxide comprising layer during the removal. Integrated circuitry is also disclosed.

Abstract: In accordance with embodiments of the methods of the present invention, a sacrificial layer provides an etch speed modification to effectively etch multiple semiconductor devices having dissimilar materials to a common layer or substrate with a common etch process. The time to etch remove a second exposed portion is compared with the time to etch remove a first exposed portion, and a sacrificial layer is deposited on the first exposed portion having a time to etch remove substantially equal to the difference. The sacrificial layer is provided to have predetermined material composition, material property and layer thickness, among other things, to provide a desired time to etch remove. The methods also provide for self-aligned via formation providing highly defined vias by the etch removal of sacrificial material rather than direct etching of the vie. The methods also provide planarization between two or more devices.

Abstract: A chemical vapor deposition method includes providing a semiconductor substrate within a chemical vapor deposition chamber. At least one liquid deposition precursor is vaporized with a vaporizer to form a flowing vaporized precursor stream. The flowing vaporized precursor stream is initially bypassed from entering the chamber for a first period of time while the substrate is in the deposition chamber. After the first period of time, thc flowing vaporized precursor stream is directed to flow into the chamber with the substrate therein under conditions effective to chemical vapor deposit a layer over the substrate. A method of etching a contact opening over a node location on a semiconductor substrate is disclosed.

Abstract: A method and apparatus to form a high-concentration, indium-fluorine retrograde well within a substrate. The indium-fluorine retrograde well includes an indium concentration greater than about 3E18/cm3.

Abstract: The present invention relates to a method of manufacturing a nano transistor. The present invention manufactures the nano transistor without changing a conventional method of forming the nano transistor formed on a SOI substrate. Further, the present invention includes forming a N well and a P well at giving regions of an underlying silicon substrate so that a given voltage can be individually applied to a NMOS transistor and a PMOS transistor. Therefore, the present invention can control the threshold voltage to prevent an increase of the leakage current.

Abstract: Disclosed herein is a method of semiconductor device isolation, which forms a device isolation film on an isolation region of a substrate using a trench process. The method comprises the steps of providing a semiconductor substrate where a device isolation region was defined; forming a mask on the substrate in such a manner that the device isolation region is exposed through the mask; etching the substrate using the mask to form a trench; thermally treating an inner wall of the trench using the mask under a hydrogen atmosphere; forming a first insulating layer covering the resulting inner wall of the trench; forming a second insulating layer on the mask in such a manner that the second insulating film covers the first insulating film; firstly etching the second insulating layer to expose a surface of the mask; removing the mask; secondly etching the remaining second insulating layer until a surface of the substrate is exposed, thereby forming a device isolation film.

Abstract: Ions are implanted into a resist pattern for forming a wiring pattern. Argon is employed as the ion species, for performing ion implantation under 50 keV at 1×1016/cm2. Due to the ion implantation, the thickness of the resist pattern contracts to about 334 nm, i.e., about 75% of the thickness of 445 nm before ion implantation, while the composition of the resist pattern changes for improving resistance against etching for a silicon nitride film and a polysilicon layer. Thus obtained is a method of manufacturing a semiconductor device capable of suppressing critical dimension shift density difference (difference between a critical dimension shift on a rough region having a relatively large space width and that on a dense region having a relatively small space width).

Abstract: A surface of a multicrystalline silicon substrate is etched with an alkaline aqueous solution in a condition so that a surface area-to-planar surface area ratio R is smaller than 1.1. A multiplicity of fine textures are formed over the irregularities by dry etching. This allows fine textures to be formed uniformly, and a solar cell with high efficiency can thus be produced.

Abstract: An operating semiconductor layer is formed in such a manner that amorphous silicon layer is formed to be shaped so that it has a wide region and a narrow region and the narrow region is connected to the wide region at a position asymmetric to the wide region, and the amorphous silicon layer is crystallized by scanning a CW laser beam from the wide region toward the narrow region in a state that a polycrystalline silicon layer as a heat-retaining layer encloses the narrow region from a side face through the silicon oxide layer.

Abstract: A method for suppressing the cutting of bonds between organic radical (for example, CH3-radical) or H-radical and Si atom in SOG film during an ashing process, thereby maintaining a low dielectric constant, after wiring gutters are formed through etching on organic or inorganic SOG film of low dielectric constant using a patterned resist film(s) thereon as a mask, the resist film(s) is removed by treating with the ashing process by use of a plasma ashing apparatus of a sheet-fed down-stream type under an atmospheric pressure of 1.2 Torr, for example, and thereafter barrier metal is formed and Cu is filled into the wiring gutters, so as to form the wiring.

Abstract: A method for forming a trimmed gate in a transistor comprises the steps of forming a polysilicon gate conductor on a semiconductor substrate and trimming the polysilicon portion by a film growth method chosen from among selective surface oxidation and selective surface nitridation. The trimming step may selectively compensate n-channel and p-channel devices. Also, the trimming film may optionally be removed by a method chosen from among anisotropic and isotropic etching. Further, gate conductor spacers may be formed by anisotropic etching of the grown film. The resulting transistor may comprise a trimmed polysilicon portion of a gate conductor, wherein the trimming occurred by a film growth method chosen from among selective surface oxidation and selective surface nitridation.

Abstract: The invention relates to a DRAM integration method that does away with the alignment margins inherent to the photoetching step of the upper electrode of the capacitance for inserting the bit line contact. The removal of the upper electrode is self-aligned on the lower electrode of the capacitance. This is accomplished by forming a difference in topography at the point where the opening of the upper electrode is to be made, and depositing a non-doped polysilicon layer on the upper electrode. An implantation of dopants is performed on this layer, and the part of the non-doped layer located in the lower part of the zone showing the difference in topography is selectively etched. The remainder of the polysilicon layer and the part of the upper electrode located in the lower layer are also etched.

Abstract: A method for improving the etch behavior of disposable features in the fabrication of a semiconductor device is disclosed. The semiconductor device comprises a bottom anti-reflective coating layer and/or a disposable sidewall spacer which are to be removed in a subsequent etch removal process. The bottom anti-reflective coating layer and/or the disposable sidewall spacer are irradiated by heavy inert ions to alter the structure of the irradiated features and to increase concurrently the etch rate of the employed materials, for example, silicon nitride or silicon reacted nitride.

Abstract: An object of the present invention is to provide a method of manufacturing a semiconductor wafer in which the manufacturing efficiency of grinding using a double-headed grinding machine is improved, minute surface undulations arising through the grinding are reduced, and the yield of the manufacturing process is improved. By processing a sliced wafer using a double-headed grinding machine, a strained layer and a macroscopic undulation component formed on the wafer surfaces during the slicing are removed, and the degree of flatness of the wafer is improved, and by subsequently carrying out both-surfaces lapping, minute surface undulations that arose during the double-headed grinding are removed.

Abstract: After forming an insulating film on an underlying layer, a resist pattern is formed on the insulating film. The insulating film is etched by using the resist pattern as a mask, thereby forming an insulating film pattern. Without removing the resist pattern, exposed portions of the underlying layer and the insulating film pattern are subjected to a plasma treatment, cleaning, a heat treatment or the like, so that a deposition grown during the formation of the insulating film pattern can be removed. Thereafter, the underlying layer is etched by using at least the insulating film pattern as a mask. As a result, even when a strict pattern rule is employed, pattern defects can be prevented from being caused in etching a multi-layer film.

Abstract: A first metal film is deposited on a bottom and a wall of a recess formed in an insulating film on a semiconductor substrate. A second metal film is filled in the recess on the first metal film. The second metal film is formed from a polycrystalline tungsten film having a crystal plane of a (110) orientation.

Abstract: The method of the present invention comprises the steps of: (a) laying on a prior layer, a first oxide layer doped in one form; (b) laying on said first oxide layer, a second oxide layer doped in a different form; (c) patterning said layers; (d) etching the second layer with an etchant having high selectivity to said second doped oxide layer; and (e) etching the first layer with an etchant having high selectivity to said first doped oxide layer.

Abstract: A method of manufacturing semiconductor devices using an improved chemical mechanical planarization process for the planarization of the surfaces of the wafer on which the semiconductor devices are formed. The improved chemical mechanical planarization process includes the formation of a flat planar surface from a deformable coating on the surface of the wafer filling in between the surface irregularities prior to the planarization of the surface through a chemical mechanical planarization process.

Abstract: A method for forming silicon quantum dots and a method for fabricating a nonvolatile memory device using the same, suitable for high speed and high packing density. The method for forming silicon quantum dots includes the steps of forming a first insulating film on a semiconductor substrate, forming a plurality of nano-crystalline silicons on the first insulating film, forming a second insulating film on the first insulating film including the nano-crystalline silicons, partially etching the second insulating film and the nano-crystalline silicons, and oxidizing surfaces of the nano-crystalline silicons.

Abstract: A method of fabricating a barrier layer includes oxidizing a silicon-containing substrate to form a substrate oxide layer on the surface of the substrate, producing an oxygen-impervious layer at an interface between the substrate oxide layer and the substrate, and etching the substrate oxide layer until the underlying oxygen-impervious layer is uncovered.

Abstract: An impurity precipitation region is formed by introducing an impurity, e.g., oxygen, into a silicon substrate or a silicon layer and thermally treating it, and performing high selectivity anisotropic etching with the precipitation region used as a micro mask. Thus, a cone (conic body or truncated conic body having an annular leading end) having a very sharp and slender needle shape with an aspect ratio of about 10 and a diameter of about 10 nm to 30 nm in the vicinity of its leading end is obtained with the micro mask used as the top. By forming an insulation layer and a drive electrode such as a gate electrode around the cone, the cone can be used for a field emission device, a single electron transistor, a memory device, a high frequency switching device, a probe of a scanning type microscope or the like.

Abstract: A method of fabricating a semiconductor memory device, particularly a mask ROM. A sacrificial oxide layer is formed on a silicon substrate and then a photoresist layer is formed on the sacrificial oxide layer. The photoresist layer is patterned to form a plurality of openings where bit lines are to extend respectively. Taking the patterned photoresist layer as a mask, arsenic ions are implanted into the silicon substrate through the openings and then boron ions are implanted into the silicon substrate through the openings. The implantation depth of boron ions are deeper than arsenic ions. The photoresist layer and the sacrificial oxide layer are removed after implantation. A gate oxide and a field oxide are grown simultaneously on the non-implanted and the implanted regions of the semiconductor layers respectively and a gate conductive layer is deposited on the silicon substrate.

Abstract: A method for forming bottle trenches. The method comprises providing a substrate formed with a pad stack layer on the top, and a deep trench with protective layer on the upper portions of sidewalls thereof, implanting ions into the lower portions of sidewalls and bottom of the trench not covered by the protective layer to amorphize the atomic structure of the sidewalls and bottom, oxidizing the amorphous sidewalls and bottom of the trench to form a bottle-shaped oxide layer thereon, and removing the bottle-shaped oxide layer.

Abstract: A method is disclosed for filling a depression between two vertically adjoining semiconductor layers, in particular an edge depression arising in the context of an isolation trench formation. A covering layer, preferably made of silicon oxide, is deposited in a large-area manner and is then doped with doping material, preferably nitrogen, essentially right over the entire depth of the layer. The doping material provides for an increased rate of removal of the covering layer, so that, after the removal process, the covering layer material only remains in the depressions.

Abstract: A substrate is provided, and a dielectric layer is formed, thereon. Then a photoresist layer is formed on the dielectric layer and defined a predetermined region for ion implantation. Next, a dense region of dielectric layer is formed by retrograde implantation with photoresist layer as an ion implanted mask, wherein the dense region is a predetermined region for trench. A hard mask layer is formed on the dielectric layer after the photoresist layer is removed. Afterward forming and defining another photoresist layer on the hard mask layer to expose a partial surface of the hard mask layer as a trench region, wherein the partial surface of the hard mask layer comprises the dense region. Subsequently, an etching process is performed by means of the photoresist layer as the etched mask to etch through the hard mask layer and the dielectric layer until the substrate surface is exposed for patterning the dual damascene.

Abstract: A process and apparatus for locally removing any material, such as a refractory metal, in particular tungsten, from any desired area of a wafer, such as an alignment mark area of a silicon wafer in process during the formation of integrated circuits thereon.

Abstract: A first method of reducing semiconductor device substrate effects comprising the following steps. O+ or O2+ are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices.

Abstract: A method of masking and etching a semiconductor substrate includes forming a layer to be etched over a semiconductor substrate. An imaging layer is formed over the layer to be etched. Selected regions of the imaging layer are removed to leave a pattern of openings extending only partially into the imaging layer. After the removing, the layer to be etched is etched using the imaging layer as an etch mask. In one implementation, an ion implant lithography method of processing a semiconductor includes forming a layer to be etched over a semiconductor substrate. An imaging layer of a selected thickness is formed over the layer to be etched. Selected regions of the imaging layer are ion implanted to change solvent solubility of implanted regions versus non-implanted regions of the imaging layer, with the selected regions not extending entirely through the imaging layer thickness.

Abstract: A method of removing contaminants from a silicon wafer after chemical-mechanical polishing (CMP). After a copper chemical-mechanical polishing and a subsequent barrier chemical-mechanical polishing operation, an aqueous solution of ozone in de-ionized water is applied to clean the silicon wafer so that contaminants on the wafer are removed. Alternatively, an ozone/de-ionized water buffer-polishing process is conducted after copper and barrier CMP and then the wafer is cleaned using a chemical solution or de-ionized water. Alternatively, an ozone/de-ionized water buffer-polishing process is conducted after both copper-CMP and barrier-CMP and then the wafer is cleaned using a chemical solution or de-ionized water.

Abstract: A process for removing at least one thin-film layer from a surface of a workpiece pursuant to manufacturing a microelectronic interconnect or component is set forth. Generally stated, the process comprises the oxidation of at least a portion of the at least one thin-film layer and the etching of the oxidized thin-film layer using an etchant that selectively etches primarily the oxidized thin-film layer.

Abstract: A patterning method includes providing a first material (e.g., copper) and transforming at a least a surface region of the first material to a second material (e.g., copper oxide). One or more portions of the second material (e.g., copper oxide) are converted to one or more converted portions of first material (e.g., copper) while one or more portions of the second material (e.g., copper oxide) remain. One or more portions of the remaining second material (e.g., copper oxide) are removed selectively relative to converted portions of first material (e.g., copper). Further, a thickness of the converted portions may be increased. Yet further, a diffusion barrier layer may be used for certain applications.

Abstract: An etching back process to improve topographic planarization of a polysilicon layer. First, a polysilicon layer is formed to fill a contact hole between two adjacent insulating structures and cover the entire surface of a semiconductor substrate to a predetermined height, in which a sunken portion is formed in the polysilicon layer over the contact hole. Then, a bottom antireflective coating (BARC) layer is formed to fill the sunken portion and cover the entire surface of the polysilicon layer. Next, in a first etching step, the BARC layer outside the sunken portion of the polysilicon layer is removed and the BARC layer in the sunken portion of the polysilicon layer is retained to flatten the bottom of the sunken portion.

Abstract: A method of fabricating high aspect ratio ceramic structures in which a selected portion of perovskite or perovskite-like crystalline material is exposed to a high energy ion beam for a time sufficient to cause the crystalline material contacted by the ion beam to have substantially parallel columnar defects. Then selected portions of the material having substantially parallel columnar defects are etched leaving material with and without substantially parallel columnar defects in a predetermined shape having high aspect ratios of not less than 2 to 1. Etching is accomplished by optical or PMMA lithography. There is also disclosed a structure of a ceramic which is superconducting at a temperature in the range of from about 10° K. to about 90° K. with substantially parallel columnar defects in which the smallest lateral dimension of the structure is less than about 5 microns, and the thickness of the structure is greater than 2 times the smallest lateral dimension of the structure.

Abstract: There is provided a high quality liquid crystal panel having a thickness with high accuracy, which is designed, without using a particulate spacer, within a free range in accordance with characteristics of a used liquid crystal and a driving method, and is also provided a method of fabricating the same. The shape of a spacer for keeping a substrate interval constant is made such that it is a columnar shape, a radius R of curvature is 2 &mgr;m or less, a height H is 0.5 &mgr;m to 10 &mgr;m, a diameter is 20 &mgr;m or less, and an angle &agr; is 65° to 115°. By doing so, it is possible to prevent the lowering of an opening rate and the lowering of light leakage due to orientation disturbance.

Abstract: Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize localized masking of holes for protection of the inside of the holes during non-mechanical removal of exposed surface layers. The localized masking is accomplished through differential exposure of a resist layer to electromagnetic or thermal energy. The methods further include modifying the removal selectivity of the surface material relative to material protected by the localized masking. Modification of the removal selectivity eases or quickens removal of the surface material. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: A multiplicity of components form a photodiode array on a substrate. Each of the components consists of a transistor of the p-n-p type with the outermost p-doped layer being transformed into an optical filter by control of the anodic etching operation utilizing transistor characteristics of the respective transistor. The result can provide red, blue and green filters in a color camera.

Abstract: A process is disclosed for planarizing a semiconductor substrate after filling isolation trenches in the substrate with dielectric material wherein the respective thicknesses of a liner layer of dielectric material blanket deposited over the upper surface of the substrate and in the trenches, and/or a filler layer of dielectric material blanket deposited over the liner layer to fill the trenches, may not be uniform.

Abstract: A method for forming a semiconductor device comprises forming a first layer over a semiconductor substrate. At least one hole is formed through the first layer. A bottom anti-reflective coating (BARC) layer is formed in the at least one hole. A first heating is performed to heat the BARC layer to a flow temperature. A second heating is performed to heat the BARC layer to a hardening temperature so that the BARC layer hardens, wherein the hardening temperature is greater than the flow temperature. An etch is performed to form a trench in the first layer and over the at least one hole, wherein the hardened BARC layer in the at least one hole acts as an etch resistant layer during the etch. As an alternative to the second heating step, the BARC may be simply hardened. The first and second heating may be performed within a heating chamber without removing the semiconductor substrate.

Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

Abstract: A composite layer comprising a non-homogenous layer is etched by continuously varying a process parameter, such as the amount of reactive agent in an etchant mixture. Embodiments include etching a silicon oxide film having a varying concentration of carbon through the film with an etchant mixture containing a fluorinated organic, oxygen and an inert gas and continuously increasing and/or decreasing the amount of oxygen in the etchant mixture during etching through the silicon oxide film.

Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

Abstract: A method of making ink jet printer head body provides a silicon wafer forming a restrictor plate over the silicon wafer by doping an impurity component. A nozzle plate is formed under the silicon wafer by doping an impurity component and a nozzle is formed by etching after the forming of the nozzle plate. A channel going through the restrictor plate and silicon wafer is formed by etching after the forming of the restrictor plate. The channel is formed of a wide upper portion and a narrow lower portion by patterning the silicon wafer and restrictor plate narrowly and etching the silicon wafer and restrictor plate, and then patterning the silicon wafer and restrictor plate widely and etching the silicon wafer and restrictor plate, except for the lower end of the silicon wafer. A restrictor at the restrictor plate is formed by etching after the patternings of the restrictor plate.