Abstract: Provided is a compound semiconductor single crystal and a fabrication process for a compound semiconductor device capable of forming a prescribed pattern without requirement of many steps. A group V element component in a III-V compound semiconductor single crystal or a group VI element component in the II-VI compound semiconductor single crystal is reduced less than a composition ratio expressed by a chemical formula of a corresponding compound semiconductor single crystal in a pattern-shaped portion.

Abstract: Heavily concentrated impurities are selectively introduced into a portion outside a polysilicon region of a region of a tunnel window area of an EEPROM memory cell, a polysilicon portion where impurities are not introduced is selectively etched, and then a tunnel oxide film is formed in a tunnel window area by oxidizing residual polysilicon.

Abstract: A process for polishing a semiconductor body according to an embodiment of the present invention includes the steps of providing a semiconductor body, forming a barrier layer over a portion of the semiconductor body, and forming at least one layer including copper over a portion of the barrier layer. The process further includes the steps of polishing at least a portion of the layer including copper with a first polishing slurry composition and changing the polishing composition from the first slurry composition to a second polishing slurry composition. The process also includes the steps of polishing at least a portion of the layer including copper with the second slurry composition and polishing at least a portion of the barrier layer with the second slurry composition. Moreover, the second slurry composition includes an effective amount of a copper oxide inhibitor to substantially inhibit copper oxide formation. In an embodiment, the effective amount of the copper oxide inhibitor is between about 0.

Abstract: A method used to fabricate a semiconductor device comprises etching a dielectric which results in an undesirable charge buildup along a sidewall formed in the dielectric during the etch. The charge buildup along a top and a bottom of the sidewall can reduce the etch rate thereby resulting in excessive etch times and undesirable etch opening profiles. To remove the charge, a sacrificial conductive layer is formed which electrically shorts the upper and lower portions of the sidewall and eliminates the charge. In another embodiment, a gas is used to remove the charge. After removing the charge, the dielectric etch may continue. Various embodiments of the inventive process and in-process structures are described.

Abstract: A method for limiting divot formation in shallow trench isolation structures. The method includes: providing a trench formed in a silicon region with a deposited oxide; oxidizing a top layer of the silicon region to form a layer of thermal oxide on top of the silicon region; and selectively etching the thermal oxide with respect to the deposited oxide.

Abstract: A method and structure for forming a notched gate structure having a gate conductor layer on a gate dielectric layer. The gate conductor layer has a first thickness. The inventive method includes patterning a mask over the gate conductor layer, etching the gate conductor layer in regions not protected by the mask to a reduced thickness, (the reduced thickness being less than the first thickness), depositing a passivating film over the gate conductor layer, etching the passivating film to remove the passivating film from horizontal portions of the gate conductor layer (using an anisotropic etch), selectively etching the gate conductor layer to remove the gate conductor layer from all regions not protected by the mask or the passivating film. This forms undercut notches within the gate conductor layer at corner locations where the gate conductor meets the gate dielectric layer. The passivating film comprises a C-containing film, a Si-containing film, a Si—C-containing film or combinations thereof.

Abstract: A method of forming a vertical transistor in an integrated circuit using copolymer lithography includes providing a dielectric layer over a semi-conductor substrate and depositing a layer of copolymer over the dielectric layer. The copolymer has a first polymer type and a second polymer type. The method further includes removing a portion of the first polymer type from the copolymer layer to form a void in the copolymer layer and removing a portion of the dielectric layer underlying the void to form an aperture in the dielectric layer. The method further includes providing a semiconductor material in the aperture.

Abstract: A method of fabricating a semiconductor device is advantageous in preventing occurrence of an erroneous short-circuit and a withstand voltage failure in a connection hole and preventing occurrence of a failure at the time of burying a connection hole with a metal. A silicon carbo-nitride film is formed on a conductor or an interconnection of a Damascene structure formed on a silicon substrate (S1), the silicon carbo-nitride film is taken as a side wall or an interlayer insulating film (S2), a silicon oxide film is formed on the silicon carbo-nitride film (S3), the upper side silicon oxide film is etched using the lower side silicon carbo-nitride film as an etching stopper layer (S4), and a connection hole is formed (S5).

Abstract: The present invention is an improved method for etching away portions of epitaxial layers in a multi-layer wafer to form a semiconductor. The method includes implanting ions throughout select portions of an epitaxial layer that are to be removed through etching. The ion implantation weakens the molecular structure of the implanted portions of the epitaxial layer and increases the vulnerability of the implanted portions to select liquid etchants or etching solutions. As such, the etching process has less impact on those portions of the epitaxial layer that were not subjected to ion implantation.

Abstract: A first silicon film is so formed as to extend along the inner surface of trenches 52 formed in a silicon oxide film 50, an oxide film is formed on the surface of the first silicon film, and a second amorphous silicon film is further deposited. Heat-treatment is applied to the surface of the second amorphous silicon film for seeding silicon nuclei and for promoting grain growth, and a granular silicon crystal 57 is grown from the second amorphous silicon film. In this way, the resistance of a lower electrode 59 of a capacitance device can be lowered.

Abstract: A silicon nitride comprising layer formed over a semiconductor substrate includes Al, Ga or a mixture thereof. A silicon dioxide comprising layer is formed proximate thereto. The silicon dioxide comprising layer is removed substantially selectively relative to the silicon nitride comprising layer, with the Al, Ga or a mixture thereof enhancing selectivity to the silicon nitride comprising layer during the removal. A substantially undoped silicon dioxide comprising layer formed over a semiconductor substrate includes B, Al, Ga or mixtures thereof. A doped silicon dioxide comprising layer is formed proximate thereto. The doped silicon dioxide comprising layer is removed substantially selectively relative to the substantially undoped silicon dioxide comprising layer, with the B, Al, Ga or mixtures thereof enhancing selectivity to the substantially undoped silicon dioxide comprising layer during the removal. Integrated circuitry is also disclosed.

Abstract: Semiconductor processing methods of forming integrated circuitry, and in particular, dynamic random access memory (DRAM) circuitry are described. In one embodiment, a single masking step is utilized to form mask openings over a substrate, and both impurities are provided and material of the substrate is etched through the openings. In one implementation, openings are contemporaneously formed in a photo masking layer over substrate areas where impurities are to be provided, and other areas where etching is to take place. In separate steps, the substrate is doped with impurities, and material of the substrate is etched through the mask openings. In another implementation, two conductive lines are formed over a substrate and a masking layer is formed over the conductive lines. Openings are formed in the masking layer in the same step, with one of the openings being received over one conductive line, and another of the openings being received over the other conductive line.

Abstract: A method for manufacturing a membrane in which an n-doped epitaxy layer is applied on a p-doped silicon substrate. Disposed between the silicon substrate and the epitaxy layer is a p-doping which leads to a reduction of the membrane thickness during a subsequent etching process.

Abstract: The invention includes a method of etching silicon dioxide, comprising doping a layer of silicon dioxide to form a layer of doped silicon dioxide and etching the doped silicon dioxide layer with phosphoric acid.

Abstract: Deep profile and highly doped impurity regions can be formed by diffusing from a solid source or doped silicon glass and using a patterned nitride layer. An oxide etch stop and polysilicon sacrificial layer are left in place in the patterned regions and the dopant is diffused through those layers. The polysilicon provides sacrificial silicon that serves to prevent the formation of boron silicon nitride on the substrate surface and also protects the oxide layer during etching of the silicon glass layer. The oxide layer then acts as an etch stop during removal of the polysilicon layer. In this way, no damage done to the substrate surface during the diffusion or subsequent etch steps and the need for expensive ion implanter steps is avoided.

Abstract: A method enhances selectivity between a film of a light-sensitive material and a layer to be subjected to etching in the course of fabrication processes of an electronic semiconductor device starting from a semiconductor material wafer. The method includes radiating the wafer with an ion beam subsequently to depositing the layer to be etched and defining a circuit pattern on the film of light-sensitive material. An alternative method exposes the wafer to a non-reactive gas medium under plasma rather than radiating the wafer with an ion beam.

Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

Abstract: A method of masking and etching a semiconductor substrate includes forming a layer to be etched over a semiconductor substrate. An imaging layer is formed over the layer to be etched. Selected regions of the imaging layer are removed to leave a pattern of openings extending only partially into the imaging layer. After the removing, the layer to be etched is etched using the imaging layer as an etch mask. In one implementation, an ion implant lithography method of processing a semiconductor includes forming a layer to be etched over a semiconductor substrate. An imaging layer of a selected thickness is formed over the layer to be etched. Selected regions of the imaging layer are ion implanted to change solvent solubility of implanted regions versus non-implanted regions of the imaging layer, with the selected regions not extending entirely through the imaging layer thickness.

Abstract: A method of forming a generally T-shaped structure. The method comprises forming a poly/amorphous silicon layer stack which comprises a polysilicon layer and a generally amorphous silicon layer overlying the polysilicon layer. The method further comprises selectively etching the poly/amorphous silicon layer stack, wherein an etch rate associated with the generally amorphous silicon layer in an over etch step associated therewith is less than an etch rate associated with the polysilicon layer, thereby causing a lateral portion of the generally amorphous silicon layer to extend beyond a corresponding lateral portion of the polysilicon layer.

Abstract: A method of forming an electrical contact to semiconductive material includes forming an insulative layer over a contact area of semiconductive material. A contact opening is etched through the insulative layer to the semiconductive material contact area. Such etching changes an outer portion of the semiconductive material exposed by the etching. The change is typically in the form of modifying crystalline structure of only an outer portion from that existing prior to the etch. The changed outer portion of the semiconductive material is etched substantially selective relative to semiconductive material therebeneath which is unchanged. The preferred etching chemistry is a tetramethyl ammonium hydroxidde solution. A conductive material within the contact opening is formed in electrical connection with the semiconductive material.

Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and the high stress masked portion of the material is selectively removed, preferably by an etching process. The low stress portion of the material remains and forms a shaped structure. One preferred selective etching process uses a basic etchant. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

Abstract: An integrated circuit fabrication process is disclosed herein. The process includes exposing a photoresist layer to a plasma, and transforming the top surface and the side surfaces of the photoresist layer to form a hardened surface. The process further includes etching the substrate in accordance with the transformed feature, wherein an etch stability of the feature is increased by the hardened surface. The photoresist layer is provided at a thickness less than 0.25 &mgr;m, for use in deep ultraviolet lithography, or for use in extreme ultraviolet lithography.

Abstract: A method for removing organometallic and organosilicate residues remaining after a dry etch process from semiconductor substrates. The substrate is exposed to a conditioning solution of phosphoric acid, hydrofluoric acid, and a carboxylic acid, such as acetic acid, which removes the remaining dry etch residues while minimizing removal of material from desired substrate features. The approximate proportions of the conditioning solution are typically 80 to 95 percent acetic acid, 1 to 15 percent phosphoric acid, and 0.01 to 5.0 percent hydrofluoric acid.

Abstract: A method for making reliable low-resistance contacts between closely spaced FET gate electrodes having high-aspect-ratio spacings. Polysilicon gate electrodes are formed. A conformal insulating layer is deposited and anisotropically etched back to form sidewall spacers on the gate electrodes. During conventional etch-back, the etch rate of the insulating layer between the closely spaced gate electrodes is slower resulting in a residual oxide that prevents the formation of reliable low-resistance contacts. This residual oxide requires an overetch in a hydrofluoric acid solution prior to forming silicide contacts. The wet overetch results in device degradation. A nitrogen or germanium implant is used to amorphize the oxide and to increase the wet etch rate of the residual oxide. Using this amorphization the wet etch that is commonly used as a pre-clean prior to forming silicide contacts can be used to remove the residual silicon oxide without overetching.

Abstract: Methods of forming an interface in a dielectric material to act as an indicator for terminating an etching process, and products produced thereby.

Abstract: The invention provides a method for the production of high quality thermally grown oxide on top of silicon carbide. The high quality oxide is obtained by selectively removing the carbon from the silicon carbide in the areas where oxide formation is desired or required.

Abstract: A surface having exposed doped silicon dioxide such as BPSG is cleaned with a solution that etches thermal oxide at least one-third as fast as it etches the exposed doped silicon dioxide, resulting in more thorough cleaning with less removal of the exposed doped silicon dioxide. Specific applications to formation of container capacitors are disclosed. Preferred cleaning solutions include about 46 parts ammonium fluoride, about 9.5 parts hydrogen fluoride, and about 8.5 parts ammonium hydroxide in about 100 parts water by weight; and about 670 parts ammonium fluoride and about 3 parts hydrogen fluoride in about 1000 parts water by weight. The latter solution is also useful in cleaning methods in which a refractory metal silicide is exposed to the cleaning solution such as in cleaning prior to spacer formation or prior to a gate stack contact fill, in which case about 670 parts ammonium fluoride and about 1.6 parts hydrogen fluoride in about 1000 parts water is most preferred.

Abstract: A method for treating a film of material, which can be defined on a substrate, e.g., silicon. The method includes providing a substrate comprising a cleaved surface, which had a porous silicon layer thereon. The substrate may have a distribution of hydrogen bearing particles defined from the cleaved surface to a region underlying said cleaved surface. The method also includes increasing a temperature of the cleaved surface to greater than about 1,000 Degrees Celsius while maintaining the cleaved surface in a etchant bearing environment to reduce a surface roughness value by about fifty percent and greater. Preferably, the value can be reduced by about eighty or ninety percent and greater, depending upon the embodiment.

Abstract: An etching method for use in integrated circuit fabrication includes providing a metal nitride layer on a substrate assembly, providing regions of cobalt silicide on first portions of the metal nitride layer, and providing regions of cobalt on second portions of the metal nitride layer. The regions of cobalt and the second portions of the metal nitride layer are removed with at least one solution including a mineral acid and a peroxide. The mineral acid may be selected from the group including HCl, H2SO4, H3PO4, HNO3, and dilute HF (preferably the mineral acid is HCl) and the peroxide may be hydrogen peroxide. Further, the removal of the regions of cobalt and the second portions of the metal nitride layer may include a one step process or a two step process. In the one step process, the regions of cobalt and the second portions of the metal nitride layer are removed with a single solution including the mineral acid and the peroxide.

Abstract: A plurality of buried conductors and/or buried plate patterns formed within a monocrystalline substrate is disclosed. A plurality of empty-spaced buried patterns are formed by drilling holes in the monocrystalline substrate and annealing the monocrystalline substrate to form empty-spaced patterns of various geometries. The empty-spaced patterns are then connected through vias with surfaces of the monocrystalline substrate. The empty-spaced patterns and their respective vias are subsequently filled with conductive materials.

Abstract: A method is disclosed for fabricating a semiconductor device structure which include a thin foot charge drain beneath the device on a silicon substrate. The structures retain high speed operation of SOI devices. In various embodiments, the invention includes forming a first diffusion-barrier layer on a semiconductor substrate, patterning the said first diffusion-barrier layer and the said silicon substrate to certain depth to form a trench, forming a second diffusion-barrier layer and patterning the said second diffusion-barrier layer to form a first spacer on the sidewall of the trench. Performing a directional etching to expose a portion of the sidewall of the trench. Introducing dopants into the said exposed sidewall to form a doped regions near the sidewall. Performing an isotropic etching using halogen gas plasma.

Abstract: Low current leakage DRAM structures are achieved using a selective silicon epitaxial growth over an insulating layer on memory cell (device) areas. An insulating layer, that also serves as a stress-release layer, and a Si3N4 hard mask are patterned to leave portions over the memory cell areas. Shallow trenches are etched in the substrate and filled with a CVD oxide which is polished back to the hard mask to form shallow trench isolation (STI) around the memory cell areas. The hard mask is selectively removed to form recesses in the STI aligned over the memory cell areas exposing the underlying insulating layer. Openings are etched in the insulating layer to provide a silicon-seed surface from which is grown a selective epitaxial layer extending over the insulating layer within the recesses. After growing a gate oxide on the epitaxial layer, FETs and DRAM capacitors can be formed on the epitaxial layer.

Abstract: In one aspect, the invention includes a method of etching, comprising: a) forming a material over a substrate, the material comprising a lower portion near the substrate and an upper portion above the lower portion; b) providing a quantity of detectable atoms within the material, the detectable atoms being provided at a different concentration in the lower portion than in the upper portion; c) etching into the material and forming etching debris; and d) detecting the detectable atoms in the debris. In another aspect, the invention includes a method of etching, comprising: a) providing a semiconductor wafer substrate, the substrate having a center and an edge; b) forming a material over the substrate, the material comprising detectable atoms; c) etching into the material and forming etching debris; d) detecting the detectable atoms in the debris; and e) estimating a degree of center-to-edge uniformity of the etching from the detecting.

Abstract: The invention defines a method for fabricating a semiconductor insulation layer: A semiconductor substrate is first provided; an insulation layer is applied by way of region-by-region or whole-area application to the semiconductor substrate; impurity ions are selectively implanted into at least one predetermined zone of the insulation layer; then the insulation layer is selectively etched, and the insulation layer is thereby patterned in accordance with the zone or zones of the selectively implanted impurity ions.

Abstract: During liquid chemical cleaning treatment, leaching of buried plugs occurs from a portion where the buried plugs are exposed locally to result in increase of resistance, lowering of electric conduction yield, lowering of device yield and deterioration of reliability. In a method of manufacturing a semiconductor device by forming upper layer interconnections on buried plugs formed in an interlayer insulating film, the upper layer interconnections are formed by patterning using etching and then plasma processing using an oxygen series gas with addition of a fluorine series gas is applied to the surface of the buried plugs formed being extended out of the upper layer interconnections, before removing the resist film 19 used as an etching mask at least by the organic stripping liquid, thereby forming a protection film on the surface of the buried plugs.

Abstract: In one aspect, the invention encompasses a method of forming an insulating material around a conductive component. A first material is chemical vapor deposited over and around a conductive component. Cavities are formed within the first material. After the cavities are formed, at least some of the first material is transformed into an insulative second material. In another aspect, the invention encompasses a method of forming an insulating material. Polysilicon is deposited proximate a substrate. A porosity of the polysilicon is increased. After the porosity is increased, at least some of the polysilicon is transformed into silicon dioxide.

Abstract: A tungsten silicide (WSi) film is formed of tungsten hexafluoride (WF6) and dichlorosilane (SiCl2) as main raw material on a polysilicon film by the CVD method. At the final stage of this film forming process, supply of tungsten hexafluoride is terminated to relax internal stresses. As a result, on the tungsten silicide film, an Si-rich tungsten silicide film containing chlorine ions in a high concentration is formed. Then, before coating a chemical amplification photoresist, these films along with a silicon substrate are soaked in an etching liquid containing hydrogen peroxide to remove the Si-rich tungsten silicide film so that generation of ammonia chloride, which suppresses an alkali developing action, can be controlled. Thus the tungsten silicide film can be patterned by photolithography without pattern defects.

Abstract: Sub-micron-dimensioned, asymmetrically-configured MOS and/or CMOS transistors are fabricated using removable sidewall spacers made of a material, such as UV-nitride, one of which is selectively treated subsequent to deposition, e.g., by ion implantation, to augment the etch rate thereof with a room temperature etchant, e.g., dilute aqueous HF. The treated spacer is removed with the dilute, aqueous HF prior to implantation of asymmetrically-configured, moderately or heavily-doped source/drain regions but prior to any post-implantation annealing processing, in order not to increase the etch resistance of the spacer material by thermally-induced densification.

Abstract: A process for manufacturing polished-like first-grade semiconductor wafers is disclosed. The process greatly simplifies the amount of polishing required while producing high quality semiconductor wafers. After a semiconductor wafer is sliced from a single crystal ingot, lapped and ground, the wafer is subjected to a double side fine grinding operation, a micro-etching operation, and an annealing operation to significantly improve the quality of the front surface. To complete to process the semiconductor wafer is flash polished to impart a specular finish on the front surface. In accordance with the present invention the semiconductor wafers may also be produced having a denuded zone capable of internal gettering.

Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and the high stress masked portion of the material is selectively removed, preferably by an etching process. The low stress portion of the material remains and forms a shaped structure. One preferred selective etching process uses a basic etchant. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

Abstract: In a method of etching an Al or Al alloy layer, an Al or Al alloy layer is formed on an underlying surface, the surface of the Al or Al alloy layer is processed with TMAH, a resist pattern is formed on the surface of the Al or Al alloy layer processed with TMAH, and by using the resist pattern as an etching mask, the Al or Al alloy layer is wet-etched.

Abstract: A method of manufacturing semiconductor devices using an improved chemical mechanical planarization process for the planarization of the surfaces of the wafer on which the semiconductor devices are formed. The improved chemical mechanical planarization process includes the formation of a flat planar surface from a deformable coating on the surface of the wafer filling in between the surface irregularities prior to the planarization of the surface through a chemical mechanical planarization process.

Abstract: A substrate is coated with a chemically amplified negative resist, thereby forming a resist film on the substrate. The chemically amplified negative resist includes: a polymer containing an acrylic acid as a polymerization unit; an acid generator for generating an acid when irradiated with extreme ultraviolet radiation; and a cross-linking agent for cross-linking the polymer in the presence of an acid. Next, the resist film is exposed to extreme ultraviolet radiation to generate an acid in exposed portions of the resist film. Thereafter, the resist film is heated to generate cross-linkage in the exposed portions of the resist film. Subsequently, a silylation reagent is supplied onto the surface of the resist film to form a silylated layer on the surface of non-exposed portions of the resist film. And then the resist film is dry-etched using the silylated layer as a mask, thereby forming a resist pattern out of the non-exposed portions of the resist film.

Abstract: A method and apparatus for endpointing a planarization process of a microelectronic substrate. In one embodiment, the apparatus may include a species analyzer that receives a slurry resulting from the planarization process and analyzes the slurry to determine the presence of an endpointing material implanted beneath the surface of the microelectronic substrate. The species analyzer may include a mass spectrometer or a spectrum analyzer. In another embodiment, the apparatus may include a radiation source that directs impinging radiation toward the microelectronic substrate, exciting atoms of the substrate, which in turn produce an emitted radiation. A radiation detector is positioned proximate to the substrate to receive the emitted radiation and determine the endpoint by determining the intensity of the radiation emitted by the endpointing material.

Abstract: A process for etching a dielectric layer, including the steps of forming, over the dielectric layer, a layer of polysilicon, forming over the layer of polysilicon a photoresist mask layer, etching the layer of polysilicon using the photoresist mask layer as an etching mask for selectively removing the layer of polysilicon, removing the photoresist mask layer from over the layer of polysilicon, etching the dielectric layer using the layer of polysilicon as a mask. Subsequently, the layer of polysilicon is converted into a layer of a transition metal silicide, and the layer of transition metal silicide is etched for selectively removing the latter from over the dielectric layer.

Abstract: Methods are disclosed for forming shaped structures of silicon-containing material with ion implantation and an etching process which is selective to silicon-containing material implanted to a certain concentration of ions or with an etching process which is selective to relatively unimplanted silicon-containing material. In general, the methods initially involve providing a layer of silicon-containing material such as polysilicon or epitaxial silicon on a semiconductor substrate. The layer of silicon-containing material is then masked, and ions are implanted into exposed portions of the layer of silicon-containing material. The mask is removed, and the aforementioned selective etching process is conducted to result in one of an implanted and a relatively unimplanted portion of the layer of silicon-containing material being etched away and the other left standing to form a shaped structure of silicon-containing material.

Abstract: A homogeneous compositions containing a fluorinated solvent, hydrogen fluoride, and a co-solvent, and the use of these compositions for cleaning and etching of substrates is described.

Abstract: The present invention provides semiconductor devices having at least one silicon region in a silicon carbide wafer in which is fabricated a low voltage semiconductor device such as for example, MOSFET devices, BiCMOS devices, Bipolar devices, etc., and on the same chip, at least one silicon carbide region in which is fabricated a high voltage (i.e., >1000V) semiconductor device using techniques well known in the art, such as for example, LDMOSFET, UMOSFET, DMOSFET, IGBT, MESFET, and JFET devices.

Abstract: A method of manufacturing semiconductor devices or precursors to semiconductor devices by hydrophobically modifying a device layer to thereby decrease the rate of polishing of the layer by at least 15%. The hydrophobically modified layer can be used as a stop layer to thereby allow for improved planarization of at least one layer of the device.

Abstract: In a method for manufacturing a semiconductor device, a barrier metal disposed on a metallic thin film for forming a thin film resistor is patterned by wet-etching. The wet-etching produces a residue of the barrier metal. The residue is removed after the oxidation thereof. Accordingly the residue is completely removed. As a result, the patterning of the thin film resistor is stably performed, and short-circuit does not occur to a wiring pattern disposed above the barrier metal.