Abstract: A method of forming an electrical contact to semiconductive material includes forming an insulative layer over a contact area of semiconductive material. A contact opening is etched through the insulative layer to the semiconductive material contact area. Such etching changes an outer portion of the semiconductive material exposed by the etching. The change is typically in the form of modifying crystalline structure of only an outer portion from that existing prior to the etch. The changed outer portion of the semiconductive material is etched substantially selective relative to semiconductive material therebeneath which is unchanged. The preferred etching chemistry is a tetramethyl ammonium hydroxide solution. A conductive material within the contact opening is formed in electrical connection with the semiconductive material.

Abstract: The sidewall nitride etch is modified to leave a thin layer of nitride covering the silicon in a DRAM array. The nitride layer prevents damage to the silicon and improves the integrity and refresh time of the array.

Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and the high stress masked portion of the material is selectively removed, preferably by an etching process. The low stress portion of the material remains and forms a shaped structure. One preferred selective etching process uses a basic etchant. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

Abstract: A method for forming nuclear tracks having a width on the order of 100-200 nm in nuclear trackable materials, such as polycarbonate (LEXAN) without causing delamination of the LEXAN. The method utilizes an adhesion film having a inert oxide which allows the track to be sufficiently widened to >200 nm without delamination of the nuclear trackable materials. The adhesion film may be composed of a metal such as Cr, Ni, Au, Pt, or Ti, or composed of a dielectric having a stable surface, such as silicon dioxide (SiO2), silicon nitride (SiNx), and aluminum oxide (AlO). The adhesion film can either be deposited on top of the gate metal layer, or if the properties of the adhesion film are adequate, it can be used as the gate layer. Deposition of the adhesion film is achieved by standard techniques, such as sputtering or evaporation.

Abstract: A method for forming a patterned shape from a noble metal, in accordance with the present invention, includes forming a noble metal layer over a dielectric layer and patterning a hard mask layer on the noble metal layer. The hard mask layer includes a mask material that is selectively removable relative to the noble metal layer and the dielectric layer and capable of withstanding plasma etching. Alternately, the hard mask material may be consumable during the noble metal layer plasma etching. Plasma etching is performed on the noble metal layer in accordance with the patterned hard mask layer. The hard mask layer is removed such that a patterned shape formed in the noble metal layer remains intact after the plasma etching and the hard mask removal.

Abstract: A method for removal of post reactive ion etch sidewall polymer rails on a Al/Cu metal line of a semiconductor or microelectronic composite structure comprising:

Abstract: The present invention provides a method for fabricating a submicron metal-oxide semiconductor field-effect transistor (MOSFET). The method includes providing a gate on a substrate, the substrate having a source side and a drain side, the drain side having a spacer area; forming a spacer at the spacer area; and performing a halo implant at the source side and the drain side, wherein the spacer prevents implantation in the spacer area, wherein the spacer facilitates formation of a lateral asymmetric channel. In the preferred embodiment, the spacer is formed by depositing an oxide layer on the gate and substrate, and then avoiding nitrogen implantation of the oxide layer in the spacer area while implanting nitrogen in the remainder of the oxide layer. The difference in the etch rates of oxide implanted with nitrogen and oxide not implanted with nitrogen allows for a selective etch of the oxide layer, resulting in the spacer in the spacer area.

Abstract: A silicate glass is selectively etched employing a composition containing a fluoride containing compound and certain organic solvents. Preferred compositions also include water.

Abstract: The invention encompasses methods for cleaning surfaces of wafers or other semiconductor articles. Oxidizing is performed using an oxidation solution which is wetted onto the surface. The oxidation solution can include one or more of: water, ozone, hydrogen chloride, sulfuric acid, or hydrogen peroxide. A rinsing step removes the oxidation solution and inhibits further activity. The rinsed surface is thereafter preferably subjected to a drying step. The surface is exposed to an oxide removal vapor to remove semiconductor oxide therefrom. The oxide removal vapor can include one or more of: acids, such as a hydrogen halide, for example hydrogen fluoride or hydrogen chloride; water; isopropyl alcohol; or ozone. The processes can use centrifugal processing and spraying actions.

Abstract: A method for providing semiconductor openings having a substantially straight wall or other desired etch profile. An etchable material layer is formed having target dopant levels or other etch rate varying characteristics to compensate for the characteristics of a selected etching process to achieve the desired etch profile. The etching process may also be varied to further match the characteristics of the etchable material layer.

Abstract: A semiconductor device is provided with a gate electrode having a substantially rectangular profile by depositing a layer of amorphous or microcrystalline silicon. The amorphous or microcrystalline silicon is doped with impurities, before patterning to form the gate electrode, to reduce gate depletion. The doped gate electrode layer is then patterned to form a gate electrode having a substantially rectangular profile.

Abstract: A method of forming a PE-CVD silicon nitride spacer having a good profile in the fabrication of a self-aligned contact wherein a two-step etching process forms the spacer is described. Semiconductor device structures are formed on a semiconductor substrate. A layer of silicon nitride is deposited by plasma-enhanced chemical vapor deposition over the surface of the substrate and overlying the semiconductor device structures. The silicon nitride layer is etched away using a two-step etching process to leave silicon nitride spacers on the side surfaces of the semiconductor device structures. The two-step process comprises a first etching away of 70% of the silicon nitride layer using Cl2/He chemistry and a second etching away of the remaining silicon nitride on top surface of the semiconductor device strucutures using SF6/CHF3/He chemistry.

Abstract: In one aspect, the invention encompasses a semiconductor processing method. Two silicon-comprising masses are provided. A first of the two masses comprises a higher dopant concentration than a second of the two masses. The two masses are exposed to common conditions which etch the second mass faster than the first mass. In another aspect, the invention encompasses another embodiment semiconductor processing method. A substrate is provided. The substrate has at least one doped polysilicon mass formed thereover, and has regions not proximate the at least one doped polysilicon mass. Roughened polysilicon is formed along the at least one doped polysilicon mass and over said regions of the substrate. A dopant concentration in the roughened polysilicon is increased along the at least one doped polysilicon mass relative to any dopant concentration in the roughened polysilicon over said regions of the substrate.

Abstract: A method for recovering the original properties of a silicon oxide film that has suffered a high energy implantation of dopants in the underlying silicon substrate, includes a brief heat treatment without causing an excessive lateral diffusion in the silicon substrate of the implanted dopants. Heat treating in an oven at a temperature of 800° C. for few minutes per wafer, which was subjected to high energy implantation, makes it possible to recover etch rate characteristics that are practically similar to those of the original non-implanted silicon oxide.

Abstract: A plasma process is described which produces an undamaged and uncontaminated silicon surface by consuming silicon by continuous oxidation through a surface oxide layer and a simultaneous etch of the exposed silicon oxide surface. The surface silicon dioxide layer thickness is controlled as an equilibrium between oxide growth from oxygen atoms reaching the silicon surface and etching of the oxide surface. The silicon dioxide protects the silicon surface from plasma damage and from contamination.

Abstract: The invention defines a method for fabricating a semiconductor insulation layer: A semiconductor substrate is first provided; an insulation layer is applied by way of region-by-region or whole-area application to the semiconductor substrate; impurity ions are selectively implanted into at least one predetermined zone of the insulation layer; then the insulation layer is selectively etched, and the insulation layer is thereby patterned in accordance with the zone or zones of the selectively implanted impurity ions. Likewise, the present invention provides a method for fabricating a semiconductor component containing this semiconductor insulation layer.

Abstract: A semiconductor device is manufactured by forming a thin layer over a semiconductor substrate, coating photoresist on the thin layer, forming a photoresist pattern over the semiconductor substrate, injecting ions into the photoresist pattern so as to harden the photoresist pattern, and etching the thin layer by using the hardened photoresist pattern as an etch mask. The hardened photoresist pattern has an increased etch selectivity with respect to an underlying layer, allowing the use of thinner photoresist layers and improved etching.

Abstract: A method of patterning a brittle material, and particularly a semiconductor material, is provided comprising ion implantation induced selective area exfoliation. The method includes steps of masking the material, implanting unmasked regions of the material, with light ions of Hydrogen or Helium, and rapid thermal annealing at the temperature causing exfoliation of the material from the implanted regions. As a result, the material is patterned to a depth determined by the depth of ion implantation. The method allows patterning through crystalline or non-crystalline materials, or several layers of different materials at the same time. When the mask has straight sharp edges aligned parallel to natural cleavage planes of the semiconductor material, the exfoliation results in formation of high quality sidewall-facets of exfoliated material and of the remaining patterned material at the boundaries of exfoliated regions.

Abstract: A multi-step polishing process for producing dopant-striation-free semiconductor wafers. The process includes polishing a surface of the wafer using a sodium stabilized colloidal silica slurry, an amine accelerant, and an alkaline etchant, polishing the surface of the wafer using a sodium stabilized colloidal silica slurry and an alkaline etchant which is substantially free of amine accelerants, and polishing the surface of the wafer using an ammonia stabilized colloidal silica slurry and an alkaline etchant which is substantially free of amine accelerants.

Abstract: An improved photolithography technique is provided whereby the beneficial effects of using an anti-reflective coating may be realized while maintaining critical dimensions in each subsequent step. This improvement is realized by the treatment of the anti-reflective coating with a gaseous plasma or a solution of sulfuric acid and hydrogen peroxide. By treating the anti-reflective coating with gaseous plasma or solution of sulfuric acid and hydrogen peroxide, no “footing” results and the critical dimensions as set by the photoresist mask are preserved to provide an accurately patterned mask for subsequent steps.

Abstract: An improved delineation pattern for epitaxial depositions is created by forming a mask on a single-crystal silicon substrate which leaves an area (10) of the substrate exposed, doping the area with a dopant to create a doped region defined by a periphery, anisotropically, vertically etching the doped region to create a delineation pattern corresponding to the periphery, and then forming an epitaxial layer over the substrate and doped region. The periphery of the delineation pattern has a squared-off delineation step including a first step wall generally perpendicular to the surface of the substrate and a second step wall generally parallel to the surface of the substrate. The squared-off delineation step helps prevent wash-out of the delineation pattern as one or more epitaxial layers are deposited on the substrate.

Abstract: A method of manufacturing a semiconductor device having a fuse conductive pattern is disclosed. The method includes forming a fuse conductive pattern on a silicon substrate and forming a first insulation layer on the fuse conductive pattern and the silicon substrate. The first insulation layer has a first etching speed. The method further includes forming a stopper pattern on a first region of the first insulation layer to cover the fuse conductive pattern and forming a second insulating layer on the stopper pattern and the first insulation layer. The stopper pattern has a second etching speed and the second insulation layer has a third etching speed. A second region of the second insulating layer is etched to form an opening. The second region is within the first region. An etching condition is set such that the first etching speed is higher than the second etching speed so that the stopper pattern is exposed at a bottom of the opening.

Abstract: The present invention proposes a method for fabricating a non-volatile memory device using nano-crystals with an increased etching rate and an increased oxidation rate at the grain boundary, which is used in high-speed and low power consumption device. The method for fabricating a non-volatile memory device using nano-crystal dots comprises following processes. First process is to fabricate a tunneling dielectric 204 and a thin amorphous silicon continuous film. Second process is to fabricate a poly-silicon layer by poly-crystallizing the amorphous silicon film. Third process is to fabricate nano-crystals 212 by etching the poly-silicon layer. Fourth process is to fabricate an interlayer dielectric 214 on the nano-crystals 212. Fifth process is to attach a poly-silicon film to the interlayer dielectric 214 and fabricate a gate 216 and interconnects 220.

Abstract: A method of forming hemispherical grain (HSG) silicon is disclosed. The method comprises the steps of: forming a doped amorphous silicon layer on a substrate; seeding and annealing the amorphous silicon layer until HSG silicon is formed; enlarging the HSG silicon grains during the annealing stage; and performing a chemical dry etch on the HSG silicon to remove an undoped silicon layer from the surface of the HSG silicon.

Abstract: A method for forming a fine pattern in a semiconductor device removes roughness from a pattern produced in a fine pattern fabrication process using a silylation process as being one kind of a TSI process, eliminates smoothly a photosensitive film residue caused by a residue silylation layer remained on a-non-pattern area, and increases a margin of a lithography process. To achieve the foregoing, the method performs an etching process with a fluorine/oxygen mixture gas so as to remove a thin oxide film being formed on the non-pattern area after a silylation process, enables an edge portion of a silylation region to be planarized so as to prevent the pattern from becoming rough, and forms a photosensitive film pattern by developing the photosensitive film with oxygen plasma. Thereafter, the photosensitive film residue is etched again with a mixture gas of fluorine/oxygen, thereby increasing a fabrication margin of the fine pattern.

Abstract: A process of growing silicon oxide to a highly calibrated thickness is provided. In one embodiment, a silicon precursor material is deposited to a first thickness on a substrate, such as a fused glass substrate used for forming microlithography masks. The precursor material is then selectively exposed to ionization and the non-ionized portions of the precursor material are then selectively etched leaving only the implanted portion of the precursor material of the first thickness. The implanted material is then oxidized resulting in an oxide structure having a thickness that is directly correlated to the initial thickness and the coefficient of oxidation. In one embodiment, a selective etch, such as TMAH, is used to remove unimplanted silicon which results in less than one percent etching of the implanted silicon.

Abstract: Disclosed is a method for making a programmable structure on a semiconductor substrate. The semiconductor structure has a first dielectric layer. The method includes plasma patterning a first metallization layer over the first dielectric layer. Forming a second dielectric layer over the first metallization layer and the first dielectric layer. Forming a plurality of tungsten plugs in the second dielectric layer. Each of the plurality of tungsten plugs are in electrical contact with the first metallization layer. Plasma patterning a second metallization layer over the second dielectric layer and the plurality of tungsten plugs, such that at least a gap over each of the tungsten plugs is not covered by the second metallization layer. Applying a programming electron dose to a portion of the second metallization layer.

Abstract: In one aspect, the invention encompasses a semiconductor processing method. Two silicon-comprising masses are provided. A first of the two masses comprises a higher dopant concentration than a second of the two masses. The two masses are exposed to common conditions which etch the second mass faster than the first mass. In another aspect, the invention encompasses another embodiment semiconductor processing method. A substrate is provided. The substrate has at least one doped polysilicon mass formed thereover, and has regions not proximate the at least one doped polysilicon mass. Roughened polysilicon is formed along the at least one doped polysilicon mass and over said regions of the substrate. A dopant concentration in the roughened polysilicon is increased along the at least one doped polysilicon mass relative to any dopant concentration in the roughened polysilicon over said regions of the substrate.

Abstract: A layer of silicon dioxide is formed conformably over a substrate having a surface with non-planar topography. The layer of silicon dioxide is then implanted with a species that affects the etch rate of the silicon dioxide when etched in an HF based etchant. The implant energy, dose, and direction are chosen such that only a selected portion of the layer of silicon dioxide is implanted with the implant species. The layer of silicon dioxide is then etched in an HF based etchant. The HF etchant etches both doped and undoped silicon dioxide, but the implanted silicon dioxide is removed at a faster rate or slower rate, depending on the implant species, than the unimplanted silicon dioxide. This allows the formation of specialized silicon dioxide structures due to the selectivity of the etch as between the implanted and unimplanted portions of the layer of silicon dioxide, without any damage to silicon.

Abstract: A method of fabricating a self-aligned contact window includes forming an undoped dielectric layer on a substrate having a least gate structure. The dopants are implanted into a pre-determined region of the undoped dielectric layer and the dielectric layer with the dopants is then removed. A self-aligned contact is therefore completed.

Abstract: A method of fabricating a semiconductor wafer is disclosed.

Abstract: A method for producing a via hole to a doped region in a semiconductor device, including the steps of: producing the doped region in a substrate such that the doped region is limited by insulating regions at least at a surface of the substrate; depositing an undoped silicon layer surface-wide on the substrate; producing a doped region in the silicon layer that overlaps a region for the via hole; selectively removing the undoped silicon of the silicon layer relative to the doped region of the silicon layer; producing an insulating layer surface-wide; and forming the via hole in the insulating layer by selective anisotropic etching relative to the doped region of the silicon layer.

Abstract: A method of forming a copper conductor for a thin film electronic device comprises: forming layers over a conductor into a stack of barrier layer superjacent on top of the substrate, a copper layer on top of the barrier layer, and a hard mask layer on top of the copper layer. The forming a mask on top of the hard mask layer and pattern the stack by etching through the layers down to the substrate on the sides of the mask forming the copper layer into a copper conductor line and leaving sidewalls of the copper conductor line exposed. Grow a copper germanide (Cu.sub.3 Ge) compound passivation layer is selectively grown only on the sidewalls of the copper conductor line.

Abstract: A method for fabricating a semiconductor substrate comprises the steps of employing a diffusion method to diffuse, in a silicon substrate, an element, which is capable of controlling a conductive type, and to form a diffused region, forming a porous layer in the diffused region, forming a non-porous single crystal layer on the porous layer, bonding the non-porous single crystal layer to a base substrate, while an insulation layer is provided either on a surface to be bonded of the non-porous single crystal layer or on a surface to be bonded of the base substrate, and removing the porous layer.

Abstract: The rapid thermal oxidation (RTO) and rapid thermal annealing(RTA) were used to improve the photo-current and photoresponsivity of porous silicon photodetector. In addition, we remove the surface oxide of the porous silicon under the metal grid using the same mask, and enhance the photo-current of porous silicon photodetector at zero bias voltage. This invention removes the limitation of application of the porous silicon photodetector.

Abstract: A chemical vapor deposition (CVD) method for forming a doped silicate glass dielectric layer within a microelectronics fabrication. There is first positioned within a reactor chamber a substrate employed within a microelectronics fabrication. There is then stabilized within the reactor chamber with respect to the substrate a first flow of a silicon source material absent a flow of a dopant source material. There is then deposited upon the substrate within the reactor chamber a doped silicate glass dielectric layer through a chemical vapor deposition (CVD) method. The doped silicate glass dielectric layer is formed employing a second flow of the silicon source material, a flow of an oxidant source material and the flow of the dopant source material. There may subsequently be formed through the doped silicate glass dielectric layer an anisotropically patterned via through an anisotropic patterning method.

Abstract: A self-aligned dielectric spacer is etched by providing capped gate structure along a second layer of dielectric material located above the gate cap material. Dopant material at an increased doping level is provided in the second layer of dielectric material where the self-aligned spacer is to be located. The second layer of dielectric material is then etched selective to the dopant to define the self-aligned dielectric spacer.

Abstract: The present invention provides a substrate treatment method to be performed after the steps of forming a desired resist pattern on a substrate and etching thereof, wherein said method comprises steps of: (I) removing the resist pattern on the substrate using a remover solution principally containing a salt derived from hydrofluoric acid and a metal-free base; (II) rinsing said substrate with a lithographic rinsing solution containing a water-soluble organic solvent and water; and (III) washing said substrate with water. According to the present invention, metallic films on the substrate are not corroded in the substrate treatment method, and the method can be performed at a low cost and with a reduced volume of labor for disposal of waste solution used for washing the substrate.

Abstract: This invention relates to methods for treatment of semiconductor substrates and in particular a method of etching a trench in a semiconductor substrate in a reactor chamber using alternatively reactive ion etching and depositing a passivation layer by chemical vapour deposition, wherein one or more of the following parameters: gas flow rates, chamber pressure, plasma power, substrate bias, etch rate, deposition rate, cycle time and etching/deposition ratio vary with time.

Abstract: The present invention provides a method of etching microelectronic structures. The method utilizes an ion implantation device projecting ions into a silicon semiconductor or conducting substrate to selectively damage the surface causing damage differential. This process is highly controllable and directable, allowing fine manipulation of the substrate surface. After the ion implantation has destroyed selected portions of the surface, standard etching techniques known in the art can be used to selectively remove the damaged portions of the surface. The advantage of this technique is that it confers upon relatively imprecise prior art etching techniques a high degree of precision. Such techniques can be used to create isolation trenches by filling the surface with electrically isolating materials which isolate one semiconductor device from another.

Abstract: In order to study an etching rate difference of a layer formed mainly with silicon dioxide on a wafer, a thermal oxide film (113) and layers of BSG (117), BPSG (125), and PSG (129) are laminated on a wafer and are etched in a gaseous etching atmosphere consisting essentially of hydrogen fluoride or a mixture of hydrogen fluoride and water vapor. The layers are etched with various etching rates which are higher than that of the thermal oxide film. The etching rate difference is a difference between the etching rate of each layer and an etching rate of the thermal oxide film. The layers may include impurities, such as boron and phosphorus, collectively as a part of a layer material of each layer. The etching rate difference depends on the layer material. Preferably, the gaseous etching atmosphere should have a reduced pressure. Alternatively, a water vapor partial pressure should not be greater than 2000 Pa. As a further alternative, either the layer or the gaseous etching atmosphere should be heated.

Abstract: A method for forming a patterned layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate an oxygen containing plasma etchable layer, where the oxygen containing plasma etchable layer is formed of a material which is also susceptible to etching within a fluorine containing plasma. There is then formed upon the oxygen containing plasma etchable layer a hard mask layer. There is then formed upon the hard mask layer a patterned photoresist layer. There is then etched through use of a first anisotropic plasma etch method the hard mask layer to form a patterned hard mask layer while simultaneously reaching the oxygen containing plasma etchable layer and while employing the patterned photoresist layer as a first etch mask layer. The first anisotropic plasma etch method employs an etchant gas composition appropriate for etching the hard mask material.

Abstract: A room temperature wet chemical digital etching technique for, gallium arsenide or other semiconductor material. Hydrogen peroxide and an acid are used in a two step etching cycle to remove the gallium arsenide in approximately 15 .ANG. limited increments. In the first step of the cycle, gallium arsenide is oxidized by, for example, 30% hydrogen peroxide to form an oxide layer that is diffusion limited to a thickness of, for example, 14-17 .ANG. for time periods from 15 seconds to 120 seconds. The second step of the cycle removes this oxide layer with an acid that does not attack unoxidized gallium arsenide. These steps are repeated in succession using new reactant materials and cleaning after each reactant (to prevent reactant contamination) until the desired etch depth is obtained. Experimental results are presented demonstrating the etch rate and process invariability with respect to hydrogen peroxide and acid exposure times.

Abstract: This invention discloses a method of planarizing a top surface with variations of profile heights above a substrate of a semiconductor chip. The method includes a step producing a polish-differentiating surface which has polishing rates proportional to the variations of the profile heights of the polish-differentiating surface above the substrate provided for performing a planarization process by applying a polishing process thereon. With the polishing differentiating surface the dishing effects of the semiconductor chip is substantially reduced when a one-time chemical mechanical polishing (CMP) process is applied for semiconductor chip planarization.

Abstract: A method of manufacturing a semiconductor device comprising the steps of forming an organic insulating film of a low dielectric constant on a surface of a silicon wafer, forming a photoresist film on the organic insulating film, exposing the photoresist film to light to form a pattern, reacting a silicon containing compound with the photoresist film pattern-exposed to silylate a light exposed portion of the photoresist film, thereby making etching resistance of the light-exposed portion higher than a non-light-exposed portion of the photoresist film, and performing reactive ion etching using a silylated photoresist film as a mask, thereby dry-developing the non light-exposed portion of the photoresist film simultaneously with etching the organic insulating film.

Abstract: A method for etching metal which can increase the metal-to-photoresist etching selectivity of a metal layer aimed to be etched with respect to a photoresist layer overlaying the metal layer. The method includes a first step of forming a cap oxide layer over the metal layer; a second step of forming a photoresist layer with a desired pattern over the cap oxide layer; a third step of conducting an ion implantation process on the photoresist layer; and a final step of conducting an etching process on the semiconductor wafer by using the photoresist layer as a mask so as to etch away exposed portions of the metal layer that are uncovered by the photoresist layer. Through experiments, it is found that the invention provides a significantly improved etching selectivity over the prior art.

Abstract: The cleavage of semiconductor crystalline wafers into laser diodes or laser diode bars is carried out at a low temperature at which both the semiconductor crystal substrate and the laser-forming laminate structure thereon are imbrittled. Cleavage at such low temperatures permits the cleavage planes to be closer together than was hitherto possible. A thickness to cavity length ratio of the resulting laser diodes or laser diode bars is approximately 1 as a result compared to 3/4 by prior art techniques. Also, the energy required for cleaving is reduced thus ensuring mirror surfaces at the cleavage planes.

Abstract: Methods are disclosed for manufacturing silicon stencil masks for use in charged-particle-beam microlithography. According to the method, a boron-doped layer is formed on a silicon substrate, a mask pattern is formed on the boron doped layer, and the boron-doped layer is etched according to the mask pattern to form voids in the boron-doped layer. The voids do not extend completely through the thickness of the boron-doped layer. In subsequent steps, a silicon nitride layer is applied and etched to form openings in which the silicon substrate is etched away to form struts. Because the boron-doped layer is not completely etched through in the earlier etching step, the mask is much more resistant to fracture in a subsequent cleaning step. In a final step after cleaning, the boron-doped layer is etched to extend the voids completely through the thickness of the boron-doped layer.

Abstract: An oxide etch process that is highly selective to nitride, thereby being beneficial for a self-aligned contact etch of silicon dioxide to an underlying thin layer of silicon nitride. The process uses difluoromethane (CH.sub.2 F.sub.2) for its strong polymer forming and a greater amount of trifluoromethane (CHF.sub.3) for its strong etching, and with a high diluent fraction of argon (Ar). The etch process is performed at a low pressure of about 20 milliTorr in a high-density plasma etching chamber.

Abstract: Disclosed is a method for forming a local interconnect with a self-aligned titanium silicide process on a semiconductor substrate. The initial step of the method is to form a thin titanium layer over the electronic devices to be provided with electrical communication. A polysilicon layer is then formed over the thin titanium layer, and in a further step, an implant mask is formed over portions of the polysilicon layer so as to pattern an area where the local interconnect is desired to be formed. Ions are then implanted into the polysilicon layer exposed by the implant mask, and the implant mask is then removed. In a further step, an etch process that etches either implanted or unimplanted polysilicon and is selective to the other is conducted. The remaining implanted polysilicon and titanium layers are then annealed to form titanium silicide, and the titanium that is not converted to titanium silicide is removed.