Abstract: A semiconductor device and a method of making the same are provided. A first die and a second die are placed over a carrier substrate. A first molding material is formed adjacent to the first die and the second die. A first redistribution layer is formed overlying the first molding material. A through via is formed over the first redistribution layer. A package component is on the first redistribution layer next to the copper pillar. The package component includes a second redistribution layer. The package component is positioned so that it overlies both the first die and the second die in part. A second molding material is formed adjacent to the package component and the first copper pillar. A third redistribution layer is formed overlying the second molding material. The second redistribution layer is placed on a substrate and bonded to the substrate.

Abstract: Apparatus for processing substrates can include a gas distribution plate that includes an upper plate and a lower plate and a solid disk between the upper plate and the lower plate. Each of the upper plate and the lower plate has a central region and an outer region surrounding the central region, the central region being solid and the outer region having a plurality of through holes. The upper plate and the lower plate are coaxially aligned along a central axis extending through a center of the central region of the upper plate and a center of the central region of the lower plate. The solid disk is coaxially aligned with the upper plate and the lower plate. The solid disk is configured to block transmission of ultraviolet radiation through the solid disk.

Abstract: The present disclosure provides a liner, a reaction chamber, and a semiconductor processing device. The liner is disposed in the reaction chamber and includes a liner body being arranged around an inner side wall of the reaction chamber and is grounded; a first separator being arranged to surround a periphery of a base disposed in the reaction chamber, a lower end of the first separator being grounded through the base; a dielectric ring being arranged between an inner peripheral wall of the first separator and an outer peripheral wall of the base; and a second separator being arranged to be around a lower end of the liner body and an outer peripheral wall of the first separator. The liner provided in the present disclosure can prevent the system from generating resonance, thereby enhancing the process stability.

Abstract: According to one embodiment, a polymer material is disclosed. The polymer material contains a polymer. The polymer contains a first monomer unit having a lone pair and an aromatic ring at a side chain, and a second monomer unit including a crosslinking group at a terminal of the side chain, with its molar ratio of 0.5 mol % to 10 mol % to all monomer units in the polymer. The polymer material can be used for manufacturing a composite film as a mask pattern for processing a target film on a substrate. The composite film can be formed by a process including, forming an organic film on the target film with the polymer material, patterning the organic film, and forming the composite film by impregnating a metal compound into the patterned organic film.

Abstract: Plasma processing apparatus and associated methods are provided. In one example, a plasma processing apparatus can include a plasma chamber configured to be able to hold a plasma. The plasma processing apparatus can include a dielectric window forming at least a portion of a wall of the plasma chamber. The plasma processing apparatus can include an inductive coupling element located proximate the dielectric window. The inductive coupling element can be configured to generate a plasma from the process gas in the plasma chamber when energized with radio frequency (RF) energy. The plasma processing apparatus can include a processing chamber having a workpiece support configured to support a workpiece. The plasma processing apparatus can include an electrostatic shield located between the inductive coupling element and the dielectric window. The electrostatic shield can be grounded via a tunable reactive impedance circuit to a ground reference.

Abstract: A remote plasma source (RPS) for generating etchants leverages symmetrical hallow cathode cavities to increase etchant rates. The RPS includes an upper electrode with a first hollow cavity configured to induce a hollow cathode effect within the first hollow cavity, a lower electrode with a second hollow cavity configured to induce a hollow cathode effect within the second hollow cavity, wherein the first hollow cavity and the second hollow cavity are symmetrical, a first gap positioned between and electrically separating the upper electrode and the lower electrode, and an annular dielectric cover in direct contact with the lower electrode in the first gap and forms a second gap between an uppermost surface of the annular dielectric cover and a lowermost surface of the upper electrode. The annular dielectric cover fills approximately 50% to approximately 95% of a height of the first gap.

Abstract: Exemplary semiconductor processing chambers may include a gasbox. The chambers may include a substrate support. The chambers may include a blocker plate positioned between the gasbox and the substrate support. The blocker plate may define a plurality of apertures through the plate. The chambers may include a faceplate positioned between the blocker plate and substrate support. The faceplate may be characterized by a first surface facing the blocker plate and a second surface opposite the first surface. The second surface of the faceplate and the substrate support may at least partially define a processing region within the semiconductor processing chamber. The faceplate may be characterized by a central axis, and the faceplate may define a plurality of apertures through the faceplate. The faceplate may define a central recess about the central axis extending from the second surface of the faceplate to a depth less than a thickness of the faceplate.

Abstract: The present disclosure discloses a reaction chamber, including a chamber body, the chamber body being connected to an upper cover by an insulation member, the chamber body and the upper cover forming an inner chamber, and the upper cover being provided with a through-hole that is communicated with the inner chamber; a gas inlet mechanism including an insulation body at least partially arranged in the through-hole, a gas inlet channel being arranged in the insulation body, a flange part being arranged on one side of the insulation body facing away from the inner chamber, the flange part being grounded and configured to communicate a gas inlet end of the gas inlet channel with a gas output end of a gas inlet pipe configure to transfer a reaction gas, a gas outlet end of the gas inlet channel being communicated with the inner chamber.

Abstract: Systems and methods for material processing using wafer scale waves of precisely controlled electrons in a DC plasma is presented. The anode and cathode of a DC plasma chamber are respectively connected to an adjustable DC voltage source and a DC current source. The anode potential is adjusted to shift a surface floating potential of a stage in a positive column of the DC plasma to a reference ground potential of the DC voltage/current sources. A conductive plate in a same region of the positive column opposite the stage is used to measure the surface floating potential of the stage. A control loop can be activated throughout various processing steps to maintain the surface floating potential of the stage to the reference ground potential. A signal generator referenced to the ground potential is capacitively coupled to the stage to control a surface potential at the stage for provision of kinetic energy to free electrons in the DC plasma.

Abstract: Systems and methods for material processing using wafer scale waves of precisely controlled electrons in a DC plasma is presented. The anode and cathode of a DC plasma chamber are respectively connected to an adjustable DC voltage source and a DC current source. The anode potential is adjusted to shift a surface floating potential of a stage in a positive column of the DC plasma to a reference ground potential of the DC voltage/current sources. A conductive plate in a same region of the positive column opposite the stage is used to measure the surface floating potential of the stage. A signal generator referenced to the ground potential is capacitively coupled to the stage to control a surface potential at the stage for provision of kinetic energy to free electrons in the DC plasma.

Abstract: Systems and methods for material processing using wafer scale waves of precisely controlled electrons in a DC plasma is presented. The anode and cathode of a DC plasma chamber are respectively connected to an adjustable DC voltage source and a DC current source. The anode potential is adjusted to shift a surface floating potential of a stage in a positive column of the DC plasma to a reference ground potential of the DC voltage/current sources. A control loop can be activated throughout various processing steps to maintain the surface floating potential of the stage to the reference ground potential. A signal generator referenced to the ground potential is capacitively coupled to the stage to control a surface potential at the stage for provision of kinetic energy to free electrons in the DC plasma.

Abstract: A plasma processing method includes a mounting process of mounting a holding sheet holding a substrate in a stage provided in a plasma processing apparatus, and a fixing process of fixing the holding sheet to the stage. The plasma processing method further includes a determining process of determining whether or not a contact state of the holding sheet with the stage is good or bad after the fixing process, and a plasma etching process of etching the substrate by exposing a surface of the substrate to plasma on the stage, in a case in which the contact state is determined to be good in the determining process.

Abstract: A plasma etching method capable of oblique etching with a high aspect ratio and high uniformity is provided. In the plasma etching method, a base body is etched with a high aspect ratio by the following process: An electric-field control device having an ion-introducing orifice penetrating therethrough in a direction inclined from the normal to the surface of a base body is placed on or above the surface of this base body. Plasma is generated on the surface of the base body on or above which the electric-field control is placed. A potential difference is formed between the plasma and the base body so as to attract ions in the plasma toward the base body.

Abstract: The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a cover ring disposed above the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.

Abstract: A method of reducing roughness in an opening in a surface of a resist material disposed on a substrate, comprises generating a plasma having a plasma sheath and ions therein. The method also includes modifying a shape of a boundary defined between the plasma and the plasma sheath with a plasma sheath modifier so that a portion of the boundary facing the resist material is not parallel to a plane defined by the surface of the substrate. The method also includes providing a first exposure of ions while the substrate is in a first position, the first exposure comprising ions accelerated across the boundary having the modified shape toward the resist material over an angular range with respect to the surface of the substrate.

Abstract: The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a cover ring disposed above the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.

Abstract: A plasma processing system. The processing system comprises a process chamber having first and second ends arranged such that the first end opposes the second end. A substrate support is positioned at the first end of the process chamber and is configured to support a substrate. An exhaust system is positioned proximate the second end of the process chamber and draws a vacuum on the process chamber. Between the exhaust system and substrate support there is a plurality of super-Debye openings, and between the exhaust system and the plurality of super-Debye openings is a plurality of sub-Debye openings. The super-Debye openings are configured to limit diffusion of plasma while the sub-Debye openings are configured to quench plasma.

Abstract: An integrated circuit (IC) comprising a shielding mesh in at least one layer of the IC, the shielding mesh having a first plurality of lines which are designed to provide a first reference voltage and having a second plurality of lines which are designed to provide a second reference voltage and wherein the shielding mesh comprises a window in which signal lines are routed with less shielding than signal lines which are routed in the shielding mesh. The IC further comprising power supply lines in at least a first layer of the IC, the first layer being different than the at least one layer which contains the shielding mesh, the power supply lines being coupled to the shielding mesh and being larger in width than the first plurality of lines and the second plurality of lines.

Abstract: The present invention provides a method for plasma processing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; loading a work piece onto the work piece support, the work piece having a support film, a frame and the substrate; providing a cover ring above the work piece, the cover ring having at least one perforated region, and at least one non-perforated region; generating a plasma using the plasma source; and processing the work piece using the generated plasma.

Abstract: A plurality of stacked semiconductor wafers each contain a plurality of semiconductor die. The semiconductor die each have a conductive via formed through the die. A gap is created between the semiconductor die. A conductive material is deposited in a bottom portion of the gap. An insulating material is deposited in the gap and over the semiconductor die. A portion of the insulating material in the gap is removed to form a recess between each semiconductor die extending to the conductive material. A shielding layer is formed over the insulating material and in the recess to contact the conductive material. The shielding layer isolates the semiconductor die from inter-device interference. A substrate is formed as a build-up structure on the semiconductor die adjacent to the conductive material. The conductive material electrically connects to a ground point in the substrate. The gap is singulating to separate the semiconductor die.

Abstract: A method and apparatus for etching photomasks is provided herein. In one embodiment, the apparatus comprises a process chamber having a support pedestal adapted for receiving a photomask. An ion-neutral shield is disposed above the pedestal and a deflector plate assembly is provided above the ion-neutral shield. The deflector plate assembly defines a gas flow direction for process gases towards the ion-neutral shield, while the ion-neutral shield is used to establish a desired distribution of ion and neutral species in a plasma for etching the photomask.

Abstract: The present invention is related shielding integrated devices using CMOS fabrication techniques to form an encapsulation with cavity. The integrated circuits are completed first using standard IC processes. A wafer-level hermetic encapsulation is applied to form a cavity above the sensitive portion of the circuits using IC-foundry compatible processes. The encapsulation and cavity provide a hermetic inert environment that shields the sensitive circuits from EM interference, noise, moisture, gas, and corrosion from the outside environment.

Abstract: A corrosion resistant component of a plasma chamber includes a liquid crystalline polymer. In a preferred embodiment, the liquid crystalline polymer (LCP) is provided on an aluminum component having an anodized or non-anodized surface. The liquid crystalline polymer can also be provided on an alumina component. The liquid crystalline polymer can be deposited by a method such as plasma spraying. The liquid crystalline polymer may also be provided as a preformed sheet or other shape adapted to cover the exposed surfaces of the reaction chamber. Additionally, the reactor components may be made entirely from liquid crystalline polymer by machining the component from a solid block of liquid crystalline polymer or molding the component from the polymer. The liquid crystalline polymer may contain reinforcing fillers such as glass or mineral fillers.

Abstract: A process for surface preparation of a substrate (2), which comprises introducing or running a substrate (2) into a reaction chamber (6, 106). A dielectric barrier (14, 114) is placed between electrodes (1, 10, 110). A high-frequency electrical voltage is generated, to generate filamentary plasma (12, 112). Molecules (8, 108) are introduced into the reaction chamber (6, 106). Upon contact with the plasma, they generate active species typical of reacting with the surface of the substrate. An adjustable inductor (L) placed in parallel with the inductor of the installation is employed to reduce the phase shift between the voltage and the current generated and to increase the time during which the current flows in the plasma (12, 112).

Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.

Abstract: Apparatus and methods for shielding a feature projecting from a first area on a substrate to a plasma while simultaneously removing extraneous material from a different area on the substrate with the plasma. The apparatus includes at least one concavity positioned and dimensioned to receive the feature such that the feature is shielded from the plasma. The apparatus further includes a window through which the plasma removes the extraneous material. The method generally includes removing the extraneous material while shielding the feature against plasma exposure.

Abstract: In one embodiment, a method of removing film materials on an edge area of a substrate in a plasma etching apparatus is disclosed. The apparatus includes a chamber, a substrate support, a shield disposed with a gap on the substrate such that plasma is not generated therein while allowing an edge portion of the substrate to be exposed, and an antenna disposed on an outer wall of the chamber to apply plasma-generating power to an area between the edge portion of the substrate and an inner wall of the chamber. The method includes spraying a curtain gas to a space between the shield and the substrate, using a curtain gas passageway; and spraying a reaction gas to an area between a side surface of the shield and an inner sidewall of the chamber formed within the shield, using a reaction gas supply passageway.

Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.

Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.

Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.

Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.

Abstract: A plurality of stacked semiconductor wafers each contain a plurality of semiconductor die. The semiconductor die each have a conductive via formed through the die. A gap is created between the semiconductor die. A conductive material is deposited in a bottom portion of the gap. An insulating material is deposited in the gap and over the semiconductor die. A portion of the insulating material in the gap is removed to form a recess between each semiconductor die extending to the conductive material. A shielding layer is formed over the insulating material and in the recess to contact the conductive material. The shielding layer isolates the semiconductor die from inter-device interference. A substrate is formed as a build-up structure on the semiconductor die adjacent to the conductive material. The conductive material electrically connects to a ground point in the substrate. The gap is singulating to separate the semiconductor die.

Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.

Abstract: A process is provided for removing polymer from a backside of a workpiece and/or photoresist from a front side of the workpiece. For backside polymer removal, the wafer is positioned near the ceiling to above a localized or remote plasma source having a side outlet through the sidewall of the chamber, and backside polymer is removed by rotating the workpiece while flowing plasma by-products from the side outlet to the wafer backside. For front side photoresist removal, the wafer is positioned away from the ceiling and below the side outlet of the localized plasma source, and front side photoresist is remove by rotating the workpiece while flowing plasma by-products from the side outlet to the wafer front side.

Abstract: A method and apparatus for etching photomasks is provided herein. In one embodiment, the apparatus comprises a process chamber having a support pedestal adapted for receiving a photomask. An ion-neutral shield is disposed above the pedestal and a deflector plate assembly is provided above the ion-neutral shield. The deflector plate assembly defines a gas flow direction for process gases towards the ion-neutral shield, while the ion-neutral shield is used to establish a desired distribution of ion and neutral species in a plasma for etching the photomask.

Abstract: An integrated circuit package system comprising: providing a lead frame; forming an integrated circuit package including the lead frame; providing a selectively exposed area on the lead frame; and coating a conductive shielding layer on the integrated circuit package for coupling the selectively exposed area.

Abstract: A method of etching a wafer using resonant infrared energy and a filter to control non-uniformities during plasma etch processing. The filter includes a predetermined array or stacked arrangement of variable transmission regions that mirror the spatial etch distortions caused by the plasma etching process. By spatially attenuating the levels of IR energy that reach the wafer, the filter improves uniformity in the etching process. Filters may be designed to compensate for edge fast etching due to macro-loading, asymmetric pumping in a plasma chamber, and magnetic field cusping.

Abstract: Provided is a method of manufacturing a semiconductor device. After a semiconductor wafer is placed over a wafer stage with which a dry cleaning chamber of a film forming apparatus is equipped, dry cleaning treatment is given over the surface of the semiconductor wafer with a reducing gas. Then, the semiconductor wafer is heat treated at a first temperature of from 100 to 150° C. by using a shower head kept at 180° C. The semiconductor wafer is then vacuum-transferred to a heat treatment chamber, wherein the semiconductor wafer is heat treated at a second temperature of from 150 to 400° C. A product remaining over the main surface of the semiconductor wafer is thus removed. The present invention makes it possible to manufacture a semiconductor device having improved reliability and production yield by reducing variations in the electrical properties of a nickel silicide layer.

Abstract: Atomic oxygen generated in oxygen stripping plasmas reacts with and damages low-k dielectric materials during stripping of dielectric post etch residues. While damage of low-k dielectric materials during stripping of dielectric post etch residues is lower with hydrogen stripping plasmas, hydrogen stripping plasmas exhibit lower strip rates. Inclusion of oxygen in a hydrogen stripping plasma improves both photoresist strip rate and uniformity, while maintaining a hydrogen to oxygen ratio avoids low-k dielectric material damage.

Abstract: A plasma etch process with in-situ backside polymer removal begins with a workpiece having a porous or non-porous carbon-doped silicon oxide dielectric layer and a photoresist mask on a surface of the workpiece. The workpiece is clamped onto an electrostatic chuck in an etch reactor chamber. The process includes introducing a fluoro-carbon based process gas and applying RF bias power to the electrostatic chuck and RF source power to an overhead electrode to etch exposed portions of the dielectric layer while depositing protective fluoro-carbon polymer on the photoresist mask. The process further includes removing the fluoro-carbon based process gas and introducing a hydrogen-based process gas and applying RF source power to the overhead electrode.

Abstract: A feature in a layer is provided. A photoresist layer is formed over the layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls, where the photoresist features have a first critical dimension. A fluorine-containing conformal layer is deposited over the sidewalls of the photoresist features to reduce the critical dimensions of the photoresist features. Fluorine is removed from the conformal layer, while the remaining conformal layer is left in place. Features are etched into the layer, wherein the layer features have a second critical dimension, which is less than the first critical dimension.

Abstract: In accordance with the objectives of the invention a new arrangement is provided for ESD protection of mounted flip chips. In a first embodiment of the invention, the Input/Output cells and power cells are provided with ESD protection that is connected to a dedicated bump pad. The substrate of the flip chip package interconnects all of the dedicated bump pads, completing the ESD network. Under the second embodiment of the invention, the Input/Output cells and power cells are provided with ESD protection that is connected to a dedicated bump pad, a last metal layer interconnects all of the dedicated bump pads, completing the ESD network.

Abstract: A coaxial shield for a semiconductor chip includes: a top vertical shield wire formed in a top metal layer of a semiconductor chip wherein the top vertical shield wire has a selected length for providing a coaxial shield; a first side shield wire formed in an intermediate metal layer of the semiconductor chip; a first upper via formed in a first dielectric layer of the semiconductor chip that extends lengthwise parallel to the first side shield wire to electrically connect the first side shield wire to the top vertical shield wire along the selected length; a second side shield wire formed in the intermediate metal layer of the semiconductor chip having a length corresponding to the selected length wherein the second side shield wire extends lengthwise parallel to the first side shield wire; and a second upper via formed in the first dielectric layer that extends lengthwise parallel to the second side shield wire to electrically connect the second side shield wire to the top vertical shield wire along the len

Abstract: A method of photoresist removal is described. A substrate is located in a processing chamber. A mixture of gases is excited, the mixture comprising a majority component of a reducing process gas and a minority component of between 0.1% and 10% by volume of an oxidizing process gas. Reactive gas species are thereby generated. A photoresist layer with an exposed dielectric layer on the substrate in the chamber is then exposed to the reactive gas mixture to selectively remove the photoresist layer from the dielectric layer.

Abstract: An apparatus for controlling the voltage applied to a shield interposed between an induction coil powered by a power supply via a matching network, and the plasma it generates, comprises a shield, a first feedback circuit, and a second feedback circuit. The power supply powers the shield. The first feedback circuit is connected to the induction coil for controlling the power supply. The second feedback circuit is connected to the shield for controlling the voltage of the shield. Both first and second feedback circuits operate at different frequency ranges. The first feedback circuit further comprises a first controller and a first sensor. The first sensor sends a first signal representing the power supplied to the inductive coil to the first controller. The first controller adjusts the power supply such that the power supplied to the inductor coil is controlled by a first set point. The second feedback circuit further comprises a second sensor, a second controller, and a variable impedance network.

Abstract: An etching apparatus has a chamber enclosing a first electrode, a second electrode, confinement rings, a focus ring, and a shield. The first electrode is coupled to a source of a fixed potential. The second electrode is coupled to a dual frequency RF power source. The confinement rings are disposed between the first electrode and the second electrode. The chamber is formed of an electrically conductive material coupled to the source. The focus ring substantially encircles the second electrode and electrically insulates the second electrode. The shield substantially encircles the focus ring. The distance between an edge of the second electrode and an edge of the shield is at least less than the distance between the edge of the second electrode and an edge of the first electrode. The shield is formed of an electrically conductive material coupled to the source of fixed potential.

Abstract: A semiconductor die carrier includes a radiation shielding base having a radiation shielding integrated base flange extending orthogonally from an upper surface of the base, the integrated base flange having an upper surface. A substrate is disposed on the radiation shielding base and around the integrated base flange, the substrate has an uppermost tier with an upper surface that is not higher than the upper surface of said integrated base flange. A radiation shielding seal lid has a radiation shielding integrated seal lid flange, the radiation shielding integrated seal lid flange has a lower surface disposed on the upper surface of the uppermost tier of the substrate.

Abstract: A method and apparatus for transferring heat from an outer edge of a substrate holder to a temperature-controlled shield ring surrounding the substrate in a plasma reactor. Additionally, heat may be transferred from an edge of the substrate to the shield ring as well.

Abstract: A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to an electric field.

Abstract: A semiconductor device (10) having a gate (15), a source (19), and a drain (20) with a gate bus (25) and first ground shield (24) patterned from a first metal layer and a second ground shield (31) patterned from a second metal layer. The first ground shield (24) and the second ground shield (31) lower the capacitance of device (10) making it suitable for high frequency applications and housing in a plastic package.