By Creating Electric Field (e.g., Plasma, Glow Discharge, Etc.) Patents (Class 438/710)
  • Patent number: 10790313
    Abstract: The present disclosure relates to an array substrate. The array substrate includes a substrate; an outer connection wiring formed on the substrate. The outer connection wiring includes an outer connection section and a wire changing section located on an inner side of the outer connection section. An inorganic film covers the outer connection wiring. The inorganic film is provided with a via hole configured to expose a part of the wire changing section, and a groove configured to expose the outer connection section. And a metal layer is formed on the inorganic film, the metal layer includes a plurality of metal wirings electrically connected to the wire changing section through the via hole.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: September 29, 2020
    Inventor: Yao Li
  • Patent number: 10790153
    Abstract: Embodiments described herein relate to apparatus and methods for performing electron beam etching process. In one embodiment, a method of etching a substrate includes delivering a process gas to a process volume of a process chamber, applying a RF power to an electrode formed from a high secondary electron emission coefficient material disposed in the process volume, generating a plasma comprising ions in the process volume, bombarding the electrode with the ions to cause the electrode to emit electrons and form an electron beam, applying a negative DC power to the electrode, accelerating electrons emitted from the bombarded electrode toward a substrate disposed in the process chamber, and etching the substrate with the accelerated ions.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: September 29, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Yue Guo, Yang Yang, Kartik Ramaswamy, Kenneth S. Collins, Steven Lane, Gonzalo Monroy, Lucy Zhiping Chen
  • Patent number: 10741452
    Abstract: Methods for forming semiconductor fins include forming a sacrificial semiconductor structure around a hardmask fin on an underlying semiconductor layer. A first etch is performed that partially etches away a portion of the hardmask fin and the sacrificial semiconductor structure with a first etch chemistry. A second etch is performed that etches away remaining material of the portion of the hardmask fin and partially etches remaining material of the sacrificial semiconductor structure with a second etch chemistry. A semiconductor fin is etched from the semiconductor layer using the etched hardmask fin as a mask.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eric R. Miller, Stuart A. Sieg, Yann Mignot, Indira Seshadri, Christopher J. Waskiewicz
  • Patent number: 10734241
    Abstract: A semiconductor device includes a semiconductor body, and first and second electrodes provided on front and back surfaces of the semiconductor body, respectively. The semiconductor body includes a first semiconductor layer and a second semiconductor layer selectively provided between the first electrode and the first semiconductor layer. A method of manufacturing the semiconductor device includes forming a mask layer on a first insulating film provided on the front surface of the semiconductor body, the mask layer including an opening above the first semiconductor layer; selectively removing the first insulating film to expose the semiconductor body, the mask layer being entirely removed together with the first insulative film; and forming a second insulating film to contact the first insulating film and the semiconductor body. The first insulative film is selectively removed through the opening. The second insulating film is formed to be semi-insulative and contact the first semiconductor layer.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: August 4, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Tsuyoshi Fujita
  • Patent number: 10734205
    Abstract: In a cleaning method according to an exemplary embodiment, a plasma is formed from a cleaning gas in a chamber of a plasma processing apparatus. A focus ring is mounted on a substrate support in the chamber to extend around a central axis of the chamber. While the plasma is formed, a magnetic field distribution is formed in the chamber by an electromagnet. The magnetic field distribution has a maximum horizontal component in a location on the focus ring or a location outside the focus ring in a radial direction with respect to the central axis.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: August 4, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Mitsuhiro Iwano, Masanori Hosoya
  • Patent number: 10692945
    Abstract: A manufacturing method for an inkjet printing AMOLED display panel is disclosed. The method includes steps of: manufacturing a TFT backplane, and manufacturing an anode on the TFT backplane; manufacturing a spacer layer for isolating the anode from a pixel definition layer on the anode; manufacturing a pixel definition layer on the TFT backplane, and the pixel definition layer covers the spacer layer; patterning the pixel definition layer to form a notch on the pixel definition layer in order to expose the spacer layer; etching the spacer layer below the notch by an etching solution; and forming an ink layer on the anode by an inkjet printing method. The invention can improve the cleanliness of the anode surface in the AMOLED display panel, reduce the residue, and make the printed light-emitting layer easier to spread evenly, prevent the AMOLED display panel from displaying abnormality.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: June 23, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD
    Inventors: Kunpeng He, Xiaoxing Zhang
  • Patent number: 10679867
    Abstract: A capacitively-coupled plasma processing apparatus includes: at least one chamber body providing chambers separated from each other; upper electrodes respectively installed in upper spaces within the chambers; lower electrodes respectively installed in lower spaces within the chambers; a high frequency power supply; a transformer including a primary coil electrically connected to the high frequency power supply, and secondary coils each of which coils having a first end and a second end; first condensers respectively connected between each of the first ends of the secondary coils and the upper electrodes; and second condensers respectively connected between each of the second ends of the secondary coils and the lower electrodes. The primary coil extends around a central axis. The secondary coils are configured to be coaxially disposed with respect to the primary coil. A self-inductance of each of the secondary coils is smaller than that of the primary coil.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: June 9, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Yohei Yamazawa
  • Patent number: 10658190
    Abstract: Extreme ultraviolet (EUV) lithographic patterning methods are provided which implement directional deposition on the EUV resist mask to improve selectivity and critical dimension control during the patterning of features in multiple layers. A hard mask material is deposited on a substrate structure using directional deposition. The hard mask material forms a hard mask layer that covers patterning features of an EUV resist mask of the substrate structure. The hard mask material is etched selective to a layer underlying the EUV resist mask to remove portions of the hard mask material that were deposited on the underlying layer during the directional deposition without uncovering the patterning features of the EUV resist mask. At least one layer of the substrate structure is patterned based on the EUV resist mask and the hard mask layer.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yongan Xu, Ekmini Anuja De Silva, Su Chen Fan, Yann Mignot
  • Patent number: 10651077
    Abstract: An etching method of silicon-containing oxide film is provided. The etching method includes a first step of forming an etching pattern on the silicon-containing oxide film by etching the silicon-containing oxide film using a first plasma generated from a first gas supplied to the processing vessel, according to a pattern of a mask layered on the silicon-containing oxide film, and a second step of removing a reaction product adhering to vicinity of an opening of the etching pattern and to the mask using a second plasma generated from a second gas supplied to the processing vessel, by applying a first high frequency electric power for generating plasma and a second high frequency electric power for generating bias voltage.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: May 12, 2020
    Assignee: Tokyo Electron Limited
    Inventor: Hideki Mizuno
  • Patent number: 10636675
    Abstract: A method of removing a metal-containing layer (e.g., tungsten) from a substrate is provided. The method includes generating a first plasma in a process volume of a plasma chamber when a patterned device is disposed on a substrate support in the process volume. The patterned device includes a patterned region and an unpatterned region; a substrate; a tungsten-containing layer formed over the substrate; a supporting layer disposed between the tungsten-containing layer and the substrate. The patterned region includes exposed surfaces of the supporting layer and the unpatterned region does not include any exposed surfaces of the supporting layer. The method further includes depositing a first film over the patterned region of the tungsten-containing layer with the first plasma; and removing portions of the unpatterned region of the tungsten-containing layer with the first plasma without depositing the first film over the unpatterned region.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: April 28, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Akhil Mehrotra, Gene Lee, Abhijit Patil, Shan Jiang, Zohreh Hesabi
  • Patent number: 10615368
    Abstract: Embodiments described herein generally relate to a method and apparatus for encapsulating an OLED structure, more particularly, to a TFE structure for an OLED structure with desired profile control of the TFE structure. In one example, a method for forming a thin film encapsulation structure over an OLED structure includes forming a thin film encapsulation structure over an OLED structure disposed on a substrate, and performing a plasma treatment process to the thin film encapsulation structure by supplying a treatment gas mixture including a halogen containing gas to the thin film encapsulation structure.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: April 7, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jrjyan Jerry Chen, Soo Young Choi, Xiangxin Rui
  • Patent number: 10559467
    Abstract: Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical dimensions to a desired final layer using a selective gas etching process. The first block is a first hardmask material that can be plasma etched using a first gas, and the second block is a second hardmask material that can be plasma etched using a second gas separate from the first gas. The first hardmask material is not plasma etched using the second gas, and the second hardmask material is not plasma etched using the first gas.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: February 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES COPORATION
    Inventors: John Christopher Arnold, Sean D. Burns, Yann Alain Marcel Mignot, Yongan Xu
  • Patent number: 10541147
    Abstract: A method for selectively etching a first region of silicon oxide with respect to a second region of silicon nitride, includes: preparing a target object including the first region and the second region in a processing chamber of a plasma processing apparatus; and generating a plasma of a processing gas containing a fluorocarbon gas and a rare gas in the processing chamber. In the generating the plasma of the processing gas, a self-bias potential of a lower electrode on which the target object is mounted is greater than or equal to 4V and smaller than or equal to 350V and a flow rate of the rare gas in the processing gas is 250 to 5000 times of a flow rate of the fluorocarbon gas in the processing gas.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: January 21, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Masahiro Tabata, Takayuki Katsunuma, Masanobu Honda
  • Patent number: 10515892
    Abstract: A method for forming a through-substrate-via structure includes forming a via hole in a substrate, depositing a conductive material in the via hole, forming an annular groove in the substrate surrounding the conductive material, and depositing a dielectric material in the annular groove with overhang portions of the deposited dielectric material at a top surface of the groove forming an air gap in an interior portion of the groove.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: December 24, 2019
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Weihai Bu, Hanming Wu
  • Patent number: 10515985
    Abstract: A transistor display panel including a substrate, a gate line disposed on the substrate and extending in a first direction, a gate electrode protruding from the gate line, a gate insulating layer disposed on the gate line and the gate electrode, a semiconductor layer and an auxiliary layer disposed on the gate insulating layer and spaced apart from each other, a data line disposed on the gate insulating layer and extending in a second direction which is a direction crossing the gate line, a drain electrode disposed on the gate insulating layer and the semiconductor layer and spaced apart from the data line, and a pixel electrode connected to the drain electrode, in which the auxiliary layer overlaps an edge of the gate electrode in a plan view.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: December 24, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byung Hwan Chu, Sho Yeon Kim, Wan-Soon Im, Yong Tae Cho
  • Patent number: 10460946
    Abstract: A technique capable of removing a natural oxide film formed on a surface of a semiconductor layer which contains a compound of indium and an element other than indium as a main ingredient, without making a temperature of the semiconductor layer relatively high. The technique includes supplying a first etching gas which is ?-diketone to the semiconductor layer and heating the semiconductor layer to remove an oxide of the indium constituting the natural oxide film; and supplying a second etching gas to the semiconductor layer and heating the semiconductor layer to remove an oxide of the element constituting the natural oxide film. By using the first etching gas, it is possible to remove the indium oxide even if the temperature of the semiconductor layer is relatively low. This eliminates the need to increase the temperature to a relatively high level when removing the natural oxide film.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: October 29, 2019
    Assignees: TOKYO ELECTRON LIMITED, CENTRAL GLASS CO., LTD.
    Inventors: Jun Lin, Koji Takeya, Shinichi Kawaguchi, Mitsuhiro Tachibana, Akifumi Yao, Kunihiro Yamauchi
  • Patent number: 10460951
    Abstract: Methods, systems, and computer programs are presented for controlling gas flow in a semiconductor manufacturing chamber. The method includes flowing a reactant gas thorough an inner feed and a tuning gas through an outer feed surrounding the inner feed, such that the gases do not mix until both are introduced in the chamber. Further, the flow of the reactant gas is convective, and the flow of the tuning gas is directed at an angle from the direction of the reactant gas, providing a delivery of the tuning gas in closer proximity to the RF power before further mixing with the reactant gas. Radio frequency power is provided to the electrode to ignite a plasma using the reactant and tuning gases. The diffusive flow of the tuning gas enables the tuning gas to be dissociated by the RF power allowing for control of the local residence time variation and preferential spatial dissociation patterns with respect to the local residence time of the reactant gas.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: October 29, 2019
    Assignee: Lam Research Corporation
    Inventors: Saravanapriyan Sriraman, Monica Titus, Alex Paterson
  • Patent number: 10453719
    Abstract: Disclosed herein is a plasma etching method for plasma-etching a ground surface of a wafer after the wafer with a tape attached to its lower surface is ground. The plasma etching method includes a drying step of applying heat to the tape to remove water present in the tape, an electrostatic holding step of electrostatically holding the wafer by an electrostatic force generated by supplying DC power to electrodes of an electrostatic chuck, after the drying step, and an etching step of reducing the pressure of a reduced-pressure chamber and plasma-etching the ground surface of the wafer by a reaction gas brought into a plasma state, after the electrostatic holding step.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: October 22, 2019
    Assignee: DISCO CORPORATION
    Inventor: Kenta Chito
  • Patent number: 10424487
    Abstract: Processing methods may be performed to remove unwanted materials from a substrate. The methods may include forming a remote plasma of an inert precursor in a remote plasma region of a processing chamber. The methods may include forming a bias plasma of the inert precursor within a processing region of the processing chamber. The methods may include modifying a surface of an exposed material on a semiconductor substrate within the processing region of the processing chamber with plasma effluents of the inert precursor. The methods may include extinguishing the bias plasma while maintaining the remote plasma. The methods may include adding an etchant precursor to the remote plasma region to produce etchant plasma effluents. The methods may include flowing the etchant plasma effluents to the processing region of the processing chamber. The methods may also include removing the modified surface of the exposed material from the semiconductor substrate.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: September 24, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Jungmin Ko, Tom Choi, Junghoon Kim, Sean Kang, Mang-Mang Ling
  • Patent number: 10403516
    Abstract: Etching characteristics in a case where a workpiece contains a nitrogen compound and an etching gas such as a CHxFy-based gas contains hydrogen are obtained. In a flux calculation step, an information processing apparatus calculates a plurality of fluxes in a surface reaction model, a processed surface of a workpiece including a protection film layer and a reaction layer in the surface reaction model. In a protection film layer calculation step, the information processing apparatus calculates a thickness of the protection film layer by using a calculation equation for calculating a thickness of an etched protection film layer based on the basis of a removal term for describing removal of the protection film layer, the removal term being selected depending on a comparison result of comparing the plurality of fluxes.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: September 3, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Nobuyuki Kuboi, Tetsuya Tatsumi
  • Patent number: 10364509
    Abstract: In a rotating disk reactor for growing epitaxial layers on substrate or other CVD reactor system, gas directed toward the substrates at gas inlets at different radial distances from the axis of rotation of the disk has both substantially the same gas flow rate/velocity and substantially the same gas density at each inlet. The gas directed toward portions of the disk remote from the axis may include a higher concentration of a reactant gas than the gas directed toward portions of the disk close to the axis, so that portions of the substrate surfaces at different distances from the axis receive substantially the same amount of reactant gas per unit area, and a combination of carrier gases with different relative molecular weights at different radial distances from the axis of rotation are employed to substantially make equal the gas density in each region of the reactor.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: July 30, 2019
    Assignee: Veeco Instruments Inc.
    Inventors: Michael Murphy, Richard Hoffman, Jonathan Cruel, Lev Kadinski, Jeffrey C. Ramer, Eric A. Armour
  • Patent number: 10354861
    Abstract: Methods for the deposition of a SiCON film by molecular layer deposition using a multi-functional amine and a silicon containing precursor having a reactive moiety.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: July 16, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Mark Saly, David Thompson, Lakmal C. Kalutarage
  • Patent number: 10354837
    Abstract: The invention is an plasma processing system with a plasma chamber for processing semiconductor substrates, comprising: a radio frequency or microwave power generator coupled to the plasma chamber; a low pressure vacuum system coupled to the plasma chamber; and at least one chamber surface that is configured to be exposed to a plasma, the chamber surface comprising: a YxOyFz layer that comprises Y in a range from 20 to 40%, O in a range from greater than zero to less than or equal to 60%, and F in a range of greater than zero to less than or equal to 75%. Alternatively, the YxOyFz layer can comprise Y in a range from 25 to 40%, O in a range from 40 to 55%, and F in a range of 5 to 35% or Y in a range from 25 to 40%, O in a range from 5 to 40%, and F in a range of 20 to 70%.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: July 16, 2019
    Assignee: Tokyo Electron Limited
    Inventor: Jianping Zhao
  • Patent number: 10347540
    Abstract: Semiconductor devices and methods of forming the same include forming gate stacks across a semiconductor fin, each gate stack having a gate conductor. An interlayer dielectric is formed between the gate stacks. A protective layer is formed on the interlayer dielectric that leaves the gate stacks exposed. The gate conductor of at least one gate stack is etched away. A dielectric liner is formed in a gap left by the etched gate conductor.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: July 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew M. Greene, Ekmini Anuja De Silva, Siva Kanakasabapathy
  • Patent number: 10347500
    Abstract: Systems and methods discussed herein are directed towards processing of substrates, including forming a plurality of features in a target layer on a substrate. The formation of the plurality of features includes a main etch operation that forms the plurality of features to a first depth in the target layer. The main etch operation is followed by a phase shift sync pulsing (PSSP) operation, and these two operations are repeated iteratively to form the features to a predetermined depth. The PSSP operation includes one or more cycles of RF source power and RF bias power, this cycle deposits a protective coating in and on the features and then etches a portion of the protective coating to expose portions of the feature.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: July 9, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chang Wook Doh, Zhibin Wang, Byungkook Kong, Sang Wook Kim, Sang-Jun Choi
  • Patent number: 10309014
    Abstract: A method of cleaning a chamber of a plasma processing device with radicals includes creating a plasma within a remote plasma source which is separated from the chamber, the plasma including radicals and ions, cleaning the chamber by allowing radicals to enter the chamber from the remote plasma source while preventing the majority of the ions created in the remote plasma source from entering the chamber, detecting a DC bias developed on a component of the chamber during cleaning; and using the detected DC bias to determine an end-point of the cleaning and, on determination of the end-point, to stop the cleaning.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: June 4, 2019
    Assignee: SPTS Technologies Limited
    Inventors: Kathrine Crook, Mark Carruthers, Andrew Price
  • Patent number: 10242864
    Abstract: Atomic layer deposition (ALD) process formation of silicon oxide with temperature >500° C. is disclosed. Silicon precursors used have a formula of: R1R2mSi(NR3R4)nXp??I. wherein R1, R2, and R3 are each independently selected from hydrogen, a linear or branched C1 to C10 alkyl group, and a C6 to C10 aryl group; R4 is selected from, a linear or branched C1 to C10 alkyl group, and a C6 to C10 aryl group, a C3 to C10 alkylsilyl group; wherein R3 and R4 are linked to form a cyclic ring structure or R3 and R4 are not linked to form a cyclic ring structure; X is a halide selected from the group consisting of Cl, Br and I; m is 0 to 3; n is 0, 1 or 2; and p is 0, 1 or 2 and m+n+p=3; and R1R2mSi(OR3)n(OR4)qXp??II.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: March 26, 2019
    Assignee: VERSUM MATERIALS US, LLC
    Inventors: Haripin Chandra, Meiliang Wang, Manchao Xiao, Xinjian Lei, Ronald Martin Pearlstein, Mark Leonard O'Neill, Bing Han
  • Patent number: 10103323
    Abstract: The inventive concepts provide a method for forming a hard mask pattern. The method includes forming a hard mask layer on an etch target layer disposed on a substrate, forming a photoresist pattern having an opening exposing one region of the hard mask layer, performing an oxygen ion implantation process on the one region using the photoresist pattern as a mask to form an oxidized portion in the one region, and patterning the hard mask layer using the oxidized portion as an etch mask.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: October 16, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong-Seok Chung, Yoonjong Song, Yongkyu Lee, Gwanhyeob Koh
  • Patent number: 10090147
    Abstract: Implementations described herein generally provide a method of processing a substrate. Specifically, the methods described are used for cleaning and etching source/drain regions on a silicon substrate in preparation for precise Group IV source/drain growth in semiconductor devices. Benefits of this disclosure include precise fin size control in devices, such as 10 nm FinFET devices, and increased overall device yield. The method of integrated clean and recess includes establishing a low pressure processing environment in the processing volume, and maintaining the low pressure processing environment while flowing a first gas over a substrate in a processing volume, depositing a salt on the substrate, heating the processing volume to greater than 90° C., purging the processing volume with a second inert gas, and recessing a source/drain region disposed on the substrate.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: October 2, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Chun Yan, Xinyu Bao, Melitta Manyin Hon, Hua Chung, Schubert S. Chu
  • Patent number: 9953843
    Abstract: Apparatuses suitable for etching substrates at various pressure regimes are described herein. Apparatuses include a process chamber including a movable pedestal capable of being positioned at a raised position or a lowered position, showerhead, and optional plasma generator. Apparatuses may be suitable for etching non-volatile metals using a treatment while the movable pedestal is in the lowered position and a high pressure exposure to organic vapor while the movable pedestal is in the raised position.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: April 24, 2018
    Assignee: Lam Research Corporation
    Inventors: Meihua Shen, Shuogang Huang, Thorsten Lill, Theo Panagopoulos
  • Patent number: 9953862
    Abstract: A plasma processing method performs an etching process of supplying a fluorine-containing gas into a plasma processing space and etching a target substrate, in which a silicon oxide film or a silicon nitride film is formed on a surface of a metal silicide film, with plasma of the fluorine-containing gas (process S101). Then, the plasma processing method performs a reduction process of supplying a hydrogen-containing gas into the plasma processing space and reducing, with plasma of the hydrogen-containing gas, a metal-containing material deposited on a member, of which a surface is arranged to face the plasma processing space, after the etching process (process S102). Thereafter, the plasma processing method performs a removal process of supplying an oxygen-containing gas into the plasma processing space and removing metal, which is obtained by reducing the metal-containing material in the reduction process, with plasma of the oxygen-containing gas (process S103).
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: April 24, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Akitoshi Harada, Yen-Ting Lin, Chih-Hsuan Chen, Ju-Chia Hsieh, Shigeru Yoneda
  • Patent number: 9941123
    Abstract: A method for etching features in a stack comprising a patterned hardmask over a carbon based mask layer is provided. A pattern is transferred from the patterned hardmask to the carbon based mask layer, comprising providing a flow of a transfer gas comprising an oxygen containing component and at least one of SO2 or COS, forming the transfer gas into a plasma, providing a bias of greater than 10 volts, and stopping the flow of the transfer gas. A post treatment is provided, comprising providing a flow of a post treatment gas comprising at least one of He, Ar, N2, H2, or NH3, wherein the flow is provided to maintain a processing pressure of between 50 mTorr and 500 mTorr inclusive, forming the post treatment gas into a plasma, providing a bias of greater than 20 volts, and stopping the flow of the post treatment gas.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: April 10, 2018
    Assignee: Lam Research Corporation
    Inventors: Mirzafer Abatchev, Qian Fu, Yasushi Ishikawa
  • Patent number: 9885117
    Abstract: A method for conditioning a semiconductor chamber component may include passivating the chamber component with an oxidizer. The method may also include performing a number of chamber process operation cycles in a semiconductor processing chamber housing the chamber component until the process is stabilized. The number of chamber operation cycles to stabilize the process may be less than 10% of the amount otherwise used with conventional techniques.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: February 6, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Dmitry Lubomirsky, Sung Je Kim
  • Patent number: 9851389
    Abstract: A method for identifying a faulty component in a plasma tool is described. The method includes accessing a measurement of a parameter received from a frequency generator and measurement device. The measurement is generated based on a plurality of radio frequency (RF) signals that are provided to a portion of a plasma tool. The RF signals have one or more ranges of frequencies. The method further includes determining whether the parameter indicates an error, which indicates a fault in the portion of the plasma tool. The method includes identifying limits of the frequencies in which the error occurs and identifying based on the limits of the frequencies in which the error occurs one or more components of the portion of the plasma tool creating the error.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: December 26, 2017
    Assignee: Lam Research Corporation
    Inventor: Seyed Jafar Jafarian-Tehrani
  • Patent number: 9793472
    Abstract: The inventive concepts provide a method for forming a hard mask pattern. The method includes forming a hard mask layer on an etch target layer disposed on a substrate, forming a photoresist pattern having an opening exposing one region of the hard mask layer, performing an oxygen ion implantation process on the one region using the photoresist pattern as a mask to form an oxidized portion in the one region, and patterning the hard mask layer using the oxidized portion as an etch mask.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: October 17, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong-Seok Chung, Yoonjong Song, Yongkyu Lee, Gwanhyeob Koh
  • Patent number: 9793130
    Abstract: In a method according to one embodiment, a first processing gas is supplied into a processing container of a plasma processing apparatus, and a plasma of the first processing gas is generated to etch an upper magnetic layer by the plasma of the first processing gas. Subsequently, a deposit, which is generated due to the etching of the upper magnetic layer, is removed. The removal of the deposit includes allowing a reduction reaction to occur in the deposit by a plasma of a second processing gas that contains H2 gas, and removing a product, which is generated by the reduction reaction, by using a third processing gas that contains hexafluoroacetylacetone.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: October 17, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Jun Sato, Eiichi Nishimura
  • Patent number: 9748091
    Abstract: In one embodiment, a substrate treatment apparatus includes a housing configured to house a substrate. The apparatus further includes a chemical supplying module configured to supply one or more chemicals in a gas state to the substrate in the housing, the one or more chemicals including a first chemical that contains a silylation agent. The apparatus further includes a cooling module configured to cool the substrate in the housing while any of the one or more chemicals is supplied to the substrate in the housing.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: August 29, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinsuke Kimura, Tatsuhiko Koide, Yoshihiro Ogawa
  • Patent number: 9735027
    Abstract: Disclosed is a method for etching an organic film. Plasma of a processing gas containing hydrogen gas and nitrogen gas is generated within a processing container of a plasma processing apparatus that accommodates a workpiece. A partial region of the organic film that is exposed from a hard mask is changed into a denatured region by the generation of the plasma of the processing gas. Subsequently, plasma of a rare gas is generated within the processing container. The denatured region is removed by the plasma of the rare gas, and a substance released from the denatured region is deposited on the surface of the hard mask. In this method, the generation of the plasma of the processing gas and the generation of the plasma of the rare gas are repeated alternately.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: August 15, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Chungjong Lee, Takayuki Katsunuma, Masanobu Honda
  • Patent number: 9728422
    Abstract: Disclosed is a dry etching method for a laminated film in which at least one silicon layer and at least one silicon oxide layer are laminated together. The dry etching method includes generating a plasma gas from a dry etching agent and etching the laminated film with the plasma gas under the application of a bias voltage. The dry etching agent contains an unsaturated hydrofluorocarbon represented by the following formula: C3HxFy where x is an integer of 1 to 5; y is an integer of 1 to 5; and x and y satisfy a relationship of x+y=4 or 6, and iodine heptafluoride. The volume of the iodine heptafluoride in the dry etching agent is 0.1 to 1.0 times the volume of the unsaturated hydrofluorocarbon in the dry etching agent.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: August 8, 2017
    Assignee: Central Glass Company, Limited
    Inventors: Hiroyuki Oomori, Akiou Kikuchi
  • Patent number: 9722048
    Abstract: A semiconductor device includes a source including a first doped semiconductor layer arranged on a substrate, a layer of metal arranged on the first doped semiconductor layer, and a second doped semiconductor layer arranged on the layer of metal; a channel extending from the second doped semiconductor layer to a drain including an epitaxial growth; a gate disposed on sidewalls of the channel between the second doped semiconductor layer and the drain; an interlayer dielectric (ILD) disposed on the second doped semiconductor layer and the gate; and a source contact extending from a surface of the ILD to abut the layer of metal of the source.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: August 1, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 9632516
    Abstract: A gas-supply system includes a gas container filled with gas, a gas flow controller coupled to the gas container, and an operation device electrically connected to the gas flow controller. The gas-supply system further includes a buffer tank coupled to the gas flow controller and configured to receive the gas from the gas container via the gas flow controller. Furthermore, a pressure transducer disposed on the buffer tank and configured to generate a pressure signal to the operation device according to the pressure of the gas in the buffer tank. The operation device is configured to generate a control signal to the gas flow controller according the pressure signal, and the gas flow controller is configured to adjust the flow rate of the gas according to the control signal to keep the pressure of the gas in the buffer tank in a predetermined pressure range.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: April 25, 2017
    Assignee: TAWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Yung-Long Chen, Chun-Feng Hsu, Heng-Yi Tseng, Chieh-Jan Huang, Chin-Hsing Su, Yung-Ching Chen
  • Patent number: 9608112
    Abstract: The present disclosure provides, in accordance with some illustrative embodiments, a method of forming a semiconductor device, the method including providing an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which is in turn formed on a base substrate material, forming a gate structure on the active semiconductor layer in an active region of the SOI substrate, partially exposing the base substrate for forming at least one bulk exposed region after the gate structure is formed, and forming a contact structure for contacting the at least one bulk exposed region.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: March 28, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Elliot John Smith, Sven Beyer, Tom Hasche, Jan Hoentschel
  • Patent number: 9607843
    Abstract: A method of patterning a silicon containing ARC (anti-reflective coating) layer underlying a patterned layer is described that includes establishing a flow of a process gas to a plasma processing system, selecting a process condition that increases an etch selectivity of the silicon containing ARC layer relative to the patterned layer, igniting plasma from the process gas using a plasma source in accordance with the process condition, and exposing the substrate to the plasma to extend the feature pattern of the patterned layer into the silicon containing ARC layer. The composition of the process gas and the flow rate(s) of the gaseous constituents in the process gas are selected to adjust the carbon-fluorine content.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: March 28, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Vinayak Rastogi, Alok Ranjan
  • Patent number: 9583371
    Abstract: An ESC may include a dielectric layer, an electrode, a pedestal, a heater, an adhesive and a protecting ring. The dielectric layer may be configured to support a substrate. The electrode may be disposed in the dielectric layer and is configured to form plasma over the substrate. The pedestal may be disposed under the dielectric layer. The heater may be disposed between the pedestal and the dielectric layer and is configured to heat the substrate. The adhesive may be disposed between the pedestal and the heater, and between the heater and the dielectric layer. The protecting ring may be configured to surround the adhesive. The protecting ring may include a plasma-resistant material.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: February 28, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jea-Eun Jess Shim, Jin-Man Kim, Hee-Sam Kim, Jong-Bum Park, Kwang-Bo Sim, Sang-Young Lee
  • Patent number: 9577028
    Abstract: A capacitor in a semiconductor device may include a lower electrode, a dielectric layer including a metal oxide and disposed on the lower electrode, a first material layer including aluminum oxide (AlxOy) and disposed on the dielectric layer, a second material layer including titanium oxynitride (TixOyNz) and disposed on the first material layer, and an upper electrode disposed on the second material layer, wherein the first material layer is between the dielectric layer and the second material layer, and the dielectric layer is between the lower electrode and the first material layer.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: February 21, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dongwon Lim, Kweonjae Lee
  • Patent number: 9564362
    Abstract: A method for forming at least one Ag or Ag based alloy feature in an integrated circuit, including providing a blanket layer of Ag or Ag based alloy in a multi-layer structure on a substrate. The method further includes providing a hard mask layer over the blanket layer of Ag or Ag based alloy. The method further includes performing an etch of the blanket layer of Ag or Ag based alloy, wherein a portion of the blanket layer of Ag or Ag based alloy that remains after the etch forms one or more conductive lines. The method further includes forming a liner that surrounds the one or more conductive lines. The method further includes depositing a dielectric layer on the multi-layer structure.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: February 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Brett C. Baker-O'Neal, Eric A. Joseph, Hiroyuki Miyazoe
  • Patent number: 9514919
    Abstract: Provided is a substrate treating apparatus, which includes a plasma generating part configured to generate plasma, a housing disposed under the plasma generating part, and having a space therein, a susceptor disposed within the housing and supporting a substrate, and a baffle including injection holes injecting the plasma supplied from the plasma generating part, to the substrate. The baffle includes a base in which the injection holes are formed, and a central portion of the base is thicker than an edge thereof.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: December 6, 2016
    Assignee: PSK INC.
    Inventors: Seung-Kook Yang, Jung-Hyun Kang
  • Patent number: 9494865
    Abstract: Novel polymer monolith structures and methods for fabrication of the same are disclosed in a variety of embodiments. In an illustrative embodiment, a method includes forming a pattern of features on a wafer, thereby forming a patterned wafer; forming a polymer layer on the patterned wafer; using a first plasma to remove at least a portion of the polymer layer; and using a second plasma to etch off at least a portion of the pattern of features, thereby providing a structured polymer monolith. The pattern of features may include an array of pillars. Providing the structured polymer monolith may include providing a structured polymer monolith filter having an array of channels formed by the pillars. The structured polymer monolith may be composed of polypropylene.
    Type: Grant
    Filed: December 31, 2010
    Date of Patent: November 15, 2016
    Assignee: CORNELL UNIVERSITY
    Inventors: Juan P Hinestroza, Huaning Zhu
  • Patent number: 9493879
    Abstract: Methods of patterning conductive layer with a mask are described. The methods include low-ion-mass sputtering of the conductive layer by accelerating (e.g. helium or hydrogen containing ions) toward a substrate which includes the patterned mask and the underlying conductive layer. The sputtering processes described herein selectively remove conductive layers while retaining mask material.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: November 15, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Mark Hoinkis, Hiroyuki Miyazoe, Eric Joseph
  • Patent number: 9412588
    Abstract: A method of growing a nitride semiconductor layer includes forming a plurality of nano-structures on a substrate, forming a first buffer layer on the substrate such that upper portions of each of the nano-structures are exposed, removing the nano-structures to form voids in the first buffer layer, and growing a nitride semiconductor layer on the first buffer layer including the voids.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: August 9, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moon-sang Lee, Sung-soo Park