Using Magnet (e.g., Electron Cyclotron Resonance, Etc.) Patents (Class 438/732)
  • Publication number: 20030017709
    Abstract: First and second electrodes at opposite ends and magnets between the electrodes define an enclosure. Inert gas (e.g. argon) molecules pass into the enclosure through an opening near the first electrode and from the enclosure through an opening near the second electrode. A ring near the first electrode, a plate near the second electrode and the magnets are at a reference potential (e.g. ground). The first electrode is biased at a high voltage by a high alternating voltage to produce a high intensity negative electrical field. The second electrode is biased at a low negative voltage by a low alternating voltage to produce a low intensity negative electrical field. Electrons movable in a helical path in the enclosure near the first electrode ionize inert gas molecules. A wafer having a floating potential and an insulating layer is closely spaced from the second electrode.
    Type: Application
    Filed: April 9, 2001
    Publication date: January 23, 2003
    Inventor: Pavel N. Laptev
  • Patent number: 6506687
    Abstract: A technique of dry etching the surface of a wafer by using a dry etching apparatus in which the distance between a wafer and a surface facing the wafer is set to the half or less of the diameter of the wafer is disclosed. Even in the case of using, especially, a wafer having a large diameter, the incident amount of etching reaction by-products in the peripheral portion of the wafer and that in the center portion of the wafer are uniformed. Thus, a uniform etching process over the whole surface of the wafer can be realized.
    Type: Grant
    Filed: December 20, 2000
    Date of Patent: January 14, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Masaru Izawa, Shinichi Tachi
  • Patent number: 6500357
    Abstract: An integrated in situ etch process performed in a multichamber substrate processing system having first and second etching chambers. The process includes transferring a substrate having formed thereon in a downward direction a patterned photoresist mask, a dielectric layer, a stop layer and a feature in the substrate to be contacted into the first etching chamber to etch the dielectric layer. The substrate is then transferred from the first etching chamber to the second etching chamber under vacuum conditions and, in the second etching chamber, is exposed to an oxygen plasma or similar environment to strip away the photoresist mask deposited over the substrate. After the photoresist mask is stripped, the stop layer is etched through to the feature to be contacted in either the second or a third etching chamber of said multichamber substrate processing system. All three etching steps are performed in a system level in situ process so that the substrate is not exposed to an ambient between steps.
    Type: Grant
    Filed: March 29, 2000
    Date of Patent: December 31, 2002
    Assignee: Applied Materials Inc.
    Inventors: Lee Luo, Claes H. Bjorkman, Brian Sy Yuan Shieh, Gerald Zheyao Yin
  • Patent number: 6488863
    Abstract: An etching gas is supplied into a process chamber and turned into plasma so as to etch a silicon nitride film arranged on a field silicon oxide film on a wafer (w). A mixture gas containing at least CH2F2 gas and O2 gas is used as the etching gas. Parameters for planar uniformity, by which the etching apparatus is set in light of a set value of the planar uniformity, include the process pressure and the mixture ratio (CH2F2/O2) of the mixture gas. As the set value of the planar uniformity is more strict, either one of the process pressure and the mixture ratio is set higher.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: December 3, 2002
    Assignee: Tokyo Electron Limited
    Inventors: Koichi Yatsuda, Tetsuya Nishiara, Kouichiro Inazawa, Shin Okamoto
  • Publication number: 20020173162
    Abstract: An oxide etch process practiced in a plasma etch reactor, such as a magnetically enhanced reactive ion etch (MERIE) reactor. The etching gas includes approximately equal amounts of a hydrogen-free fluorocarbon, most preferably C4F6, and oxygen and a much larger amount of argon diluent gas. The magnetic field is preferably maintained above about 50 gauss and the pressure at 40 milliTorr or above with chamber residence times of less than 70 milliseconds. A two-step process may be used for etching holes with very high aspect ratios. In the second step, the magnetic filed and the oxygen flow are reduced. Other fluorocarbons may be substituted which have F/C ratios of less than 2 and more preferably no more than 1.6 or 1.5.
    Type: Application
    Filed: May 13, 2002
    Publication date: November 21, 2002
    Inventors: Jingbao Liu, Takehiko Komatsu, Hongqing Shan, Keiji Horioka, Bryan Y. Pu
  • Patent number: 6475918
    Abstract: An etching method capable of obtaining a fine fabricated shape, particularly, a vertical fabricated shape with less bowing upon fabrication of insulation films in the production of semiconductors, the method comprising controlling the incident amount of O, F or N radicals, gas flow rate or consumption amount of O, F and N on the inner wall surface with etching time to suppress excessive O, F and N which become excessive in the initial stage of etching, the method also including control for the flow rate or the consumption amount based on the result of measurement for plasmas during etching so as to obtain a stable etching shape. Since bowing can be reduced upon fabrication of insulation film hole and insulation film while maintaining the etching rate and the selectivity, finer semiconductor device can be produced easily.
    Type: Grant
    Filed: October 5, 2000
    Date of Patent: November 5, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Masaru Izawa, Kenetsu Yokogawa, Nobuyuki Negishi, Yoshinori Momonoi, Shinichi Tachi
  • Patent number: 6461972
    Abstract: A dual plasma process generates a microwave neutral plasma remote from a semiconductor wafer and a radio frequency (RF) ionized plasma adjacent to the wafer for simultaneous application to the wafer. A first gas flows through a microwave plasma generation area, without a second gas in the gas flow, to generate the neutral microwave plasma. The second gas is added to the gas flow downstream of the microwave plasma generation area prior to an RF plasma generation area.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: October 8, 2002
    Assignee: LSI Logic Corporation
    Inventor: Alex Kabansky
  • Publication number: 20020142615
    Abstract: An etching apparatus has (a) a processing unit to ionize a reactive gas and generate plasma to process a semiconductor wafer, (b) a bed on which the semiconductor wafer is set, (c) a first magnet arranged below the semiconductor wafer in the vicinity of the periphery of a semiconductor chip forming area defined on the semiconductor wafer, and (d) a second magnet arranged above the semiconductor wafer in the vicinity of the periphery of the semiconductor chip forming area.
    Type: Application
    Filed: March 27, 2002
    Publication date: October 3, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Masahiro Kanno
  • Patent number: 6429140
    Abstract: A method of forming a patterned photoresist layer is performed in a nitrogen gas atmosphere. The method includes the steps of sequentially forming a layer to be etched and first photoresist layer on a semiconductor substrate, and sequentially forming an intermediate barrier layer and second photoresist layer on the first photoresist layer. The second photoresist layer is patterned, and the intermediate barrier layer is etched using the patterned second photoresist layer as a mask. The first photoresist layer is etched in a nitrogen gas atmosphere, and the first photoresist layer is etched using the patterned intermediate barrier layer as a mask.
    Type: Grant
    Filed: March 5, 1997
    Date of Patent: August 6, 2002
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Jae Hee Ha, Dong Hyen Yi, Myung Ho Yim
  • Publication number: 20020098710
    Abstract: The invention encompasses a method of incorporating nitrogen into a silicon-oxide-containing layer. The silicon-oxide-containing layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer. The nitrogen is subsequently thermally annealed within the layer to bond at least some of the nitrogen to silicon within the layer. The invention also encompasses a method of forming a transistor. A gate oxide layer is formed over a semiconductive substrate. The gate oxide layer comprises silicon dioxide. The gate oxide layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer, and the layer is maintained at less than or equal to 400° C. during the exposing. Subsequently, the nitrogen within the layer is thermally annealed to bond at least a majority of the nitrogen to silicon. At least one conductive layer is formed over the gate oxide layer.
    Type: Application
    Filed: January 15, 2002
    Publication date: July 25, 2002
    Inventors: Gurtej S. Sandhu, John T. Moore, Neal R. Rueger
  • Patent number: 6376388
    Abstract: A method of manufacturing a semiconductor device having an insulated gate type field effect transistor. A gate insulating film, a gate electrode layer having a predetermined area and facing the semiconductor substrate with the gate insulating film being interposed therebetween, an interlayer insulating film, and a wiring layer connected to the gate electrode layer, are formed on a semiconductor substrate in the order recited. A conductive material layer and a resist layer are formed on the wiring layer. The resist layer is patterned to form a resist mask forming a wiring pattern having an antenna ratio of about ten times or more of the predetermined area of the gate electrode layer. At least the conductive material layer is plasma-etched by using the resist mask as an etching mask, and thereafter, the resist mask is removed and the wiring layer is plasma-etched.
    Type: Grant
    Filed: January 22, 1997
    Date of Patent: April 23, 2002
    Assignee: Fujitsu Limited
    Inventors: Koichi Hashimoto, Daisuke Matsunaga, Masaaki Aoyama
  • Patent number: 6372654
    Abstract: There is provided a method of fabricating a semiconductor device, including the steps of (a) generating plasma in the following conditions: (a1) an RF bias voltage has a frequency equal to or greater than 1 MHz, (a2) an RF source voltage has a frequency equal to or greater than 1 MHz, (a3) the RF source voltage is modulated by pulses in a cycle equal to or greater than 100 &mgr;sec, and (a4) pulse-on time is equal to or greater than 50 &mgr;sec, and (b) patterning multi-layered metal wirings by etching through the plasma The method makes it possible to reduce charging damage to a gate insulating film, even if wirings are further spaced away from adjacent ones and/or an antenna ratio of multi-layered metal wirings is further increased.
    Type: Grant
    Filed: April 5, 2000
    Date of Patent: April 16, 2002
    Assignee: NEC Corporation
    Inventor: Ken Tokashiki
  • Patent number: 6350701
    Abstract: A small, light-weight and highly maintainable etching system and an etching method for etching a large substrate with a homogeneous etching rate are provided. The etching system comprises an agitating electric field system disposed around the substrate, an agitating power source of high frequency, medium frequency or low frequency, agitating electrodes, amplifiers and a phase controller to agitate electrons or ions to increase the etching speed and the uniformity of the etching rate by promoting activation of reactive gas and uniformalizing a plasma density.
    Type: Grant
    Filed: September 29, 1999
    Date of Patent: February 26, 2002
    Assignee: Semiconductor Energy Laboratory Co., Ltd
    Inventor: Shunpei Yamazaki
  • Patent number: 6333246
    Abstract: A semiconductor device manufacturing method comprises the steps of placing a substrate to be processed on an electrostatic chuck on a substrate stand in a process chamber, and applying a negative voltage to the electrostatic chuck. After applying the negative voltage, the substrate is stuck onto the electrostatic chuck, a process gas is introduced into the process chamber, discharge plasma is generated, and the substrate is processed as predetermined.
    Type: Grant
    Filed: June 28, 2000
    Date of Patent: December 25, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaki Narita, Yukimasa Yoshida, Katsuaki Aoki, Hiroshi Fujita, Osamu Yamazaki, Toshimitsu Omine, Isao Matsui, Takashi O
  • Patent number: 6309979
    Abstract: A method in a high density plasma chamber for protecting a semiconductor substrate from charging damage from plasma-induced current through the substrate while etching through a selected portion of a conductive layer above the substrate. The method includes performing a bulk etch at least partially through the selected portion of the conductive layer using a first power setting for a plasma generating source of the high density plasma chamber. The method further includes performing a clearing etch through the selected portion of the conductive layer using a second power setting for the plasma generating source. In accordance with this embodiment, the second power setting is substantially minimized to reduce the charging damage.
    Type: Grant
    Filed: December 18, 1996
    Date of Patent: October 30, 2001
    Assignee: Lam Research Corporation
    Inventors: Roger Patrick, Stanley C. Siu, Luisarita Atzei
  • Patent number: 6287980
    Abstract: A plasma processing apparatus mainly comprises a processing chamber (10) formed by a vacuum vessel, a magnetic field forming coil (80) arranged around the processing chamber for forming a rotating magnetic field and gas supply means (101) supplying various gases to the processing chamber (10). The processing chamber (10) is divided into a reaction chamber (44) forming plasma with a partition wall (43) and a buffer chamber (45) discharging externally supplied gases with pressure difference. The reaction chamber (44) includes a high-frequency electrode arranged oppositely to the buffer chamber (45). The gas supply means (101) includes pulse gas valves (63a and 63b) for pulsatively supplying gases to the processing chamber (10). Thus provided are a plasma processing method and a plasma processing apparatus capable of uniformly processing a wafer having a large diameter and reducing RIE lag with respect to a fine etching pattern.
    Type: Grant
    Filed: October 12, 1999
    Date of Patent: September 11, 2001
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Co., Ltd.
    Inventors: Minoru Hanazaki, Takayuki Ikushima, Kenji Shirakawa, Shinji Yamaguchi, Masakazu Taki
  • Patent number: 6232218
    Abstract: A etch stop layer for use in a silicon oxide dry fluorine etch process is made of silicon nitride with hydrogen incorporated in it either in the form of N—H bonds, O—H bonds, or entrapped free hydrogen. The etch stop layer is made by either increasing the NH3 flow, decreasing the SiH4 flow, decreasing the nitrogen flow, or all three, in a standard PECVD silicon nitride fabrication process. The etch stop can alternatively be made by pulsing the RF field in either a PECVD process or an LPCVD process.
    Type: Grant
    Filed: August 19, 1999
    Date of Patent: May 15, 2001
    Assignee: Micron Technology, Inc.
    Inventors: David A. Cathey, J. Brett Rolfson, Valerie A. Ward, Karen M. Winchester
  • Patent number: 6210595
    Abstract: A method for producing structures having a high aspect ratio includes the following steps: a material of the structure to be produced is provided in the form of a layer, a mask is applied to the layer, the layer is subjected to dry etching using the mask, thereby forming redepositions of the layer material on side walls of the mask and the mask is removed, so that a structure having a high aspect ratio is left behind. The method enables very high (≧1 &mgr;m) and very thin (≦50 nm) structures to be produced in a relatively simple and rapid manner in only very few process steps and with only one mask technique. Structures having such large aspect ratios, particularly when they are composed of a conductive material, cannot be produced, or can be produced only with a high outlay, by using other methods.
    Type: Grant
    Filed: September 8, 1998
    Date of Patent: April 3, 2001
    Assignee: Infineon Technologies AG
    Inventors: Volker Weinrich, Manfred Engelhardt
  • Patent number: 6197699
    Abstract: The present invention provides a method for cleaning a contaminated chamber used in the manufacture of semiconductor devices. In one embodiment, the method comprises the steps of injecting, under pressure, a gas mixture of a fluorine-containing gas and an inert gas into the contaminated chamber, radiating the contaminated chamber with a radio frequency during the step of injecting, and removing volatile by-products or solid particulates from the contaminated chamber by performing pump-purge cycles within the contaminated chamber.
    Type: Grant
    Filed: January 20, 1998
    Date of Patent: March 6, 2001
    Assignee: Lucent Technologies Inc.
    Inventors: Larry B. Fritzinger, Cynthia C. Lee, Edward M. Middlebrook, John M. Sniegowski
  • Patent number: 6139647
    Abstract: A post-etch structure resulting in the inverse of a sidewall spacer etch, i.e. removal of the spacer. A vertical portion of a film is removed while leaving horizontal portions substantially intact. A facet is left in the film in register with an upper corner formed by the vertical and horizontal portions of the underlying body.
    Type: Grant
    Filed: April 2, 1998
    Date of Patent: October 31, 2000
    Assignee: International Business Machines Corporation
    Inventors: Michael David Armacost, Steven Alfred Grundon, David Laurant Harmon, Donald McAlpine Kenney
  • Patent number: 6132632
    Abstract: A method and apparatus for achieving etch rate uniformity in a reactive ion etcher. The reactive ion etcher generates a plasma within a vacuum chamber for etching a substrate disposed at a cathode of a reactor can within the chamber wherein the plasma emanates from a top plate of the reactor can, and is influenced by localized magnetic fields for locally controlling etch rates across the cathode to produce a uniform etch rate distribution across the cathode as a result of the localized magnetic field. The magnet array may be disposed between the top plate and the vacuum chamber for providing the localized magnetic fields. The magnet array includes a plurality of individual magnets and a grid plate for holding the individual magnets in position.
    Type: Grant
    Filed: September 11, 1997
    Date of Patent: October 17, 2000
    Assignee: International Business Machines Corporation
    Inventors: David Emery Haney, Robert James Huber, Cherngye Hwang, Diana Perez, John Wesley Williams
  • Patent number: 6110395
    Abstract: The present invention relates to a method and structure for controlling plasma uniformity in plasma processing applications. Electron thermal conductivity parallel and perpendicular to magnetic field lines differs by orders of magnitude for low magnetic fields (on the order of 10 gauss). This property allows the directing of heat flux by controlling the magnetic field configuration independent of ions since the effect of modest magnetic fields upon the transport of ions themselves is minimal. Heat is preferentially conducted along magnetic field lines with electron temperatures on the order of 0.1 to 1 eV/cm being sufficient to drive kilowatt-level heat fluxes across areas typical of plasma processing source dimensions.
    Type: Grant
    Filed: August 26, 1997
    Date of Patent: August 29, 2000
    Assignee: Trikon Technologies, Inc.
    Inventor: Gerald W. Gibson, Jr.
  • Patent number: 6085688
    Abstract: The present invention provides an apparatus and method for processing a workpiece in an inductively coupled plasma reactor. Inductive power is applied to the reactor to generate a plasma. A magnetic field is generated within the plasma reactor having lines of force oriented perpendicular to the workpiece surface. It is a feature of the invention to control the electron temperature near the surface of the workpiece by controlling the applied magnetic field. It is a further feature to increase average ion density near the workpiece without otherwise causing damage to the workpiece due to uneven charge build-up. The applied magnetic field can be time invariant or time variant. In both cases, processing can be optimized by adjusting the magnitude of the magnetic field to a level just below where damage due to uneven charge build-up occurs. With the time variant field, the average ion density can be adjusted with respect to average electron temperature.
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: July 11, 2000
    Assignee: Applied Materials, Inc.
    Inventors: Dimitris Lymberopoulos, Peter Loewenhardt, John Yamartino
  • Patent number: 6066568
    Abstract: An electron density at an ECR point, which is spaced from a substrate to be treated and which faces the substrate, is set to be higher than or equal to 0.46 nc (nc: an upper limit side cut-off density of an X wave) and lower than nc. Thus, a high chevron distribution of electron density is formed in end portions of a magnetic field forming region, and a distribution of electron density having a lower peak value than those in the end portions is formed in a central portion of the magnetic field forming region. In this case, the periphery of a magnetic field crosses the inner wall of a vacuum chamber once between the ECR point and the substrate, and a space of one fourth or more of the wavelength of the X wave is formed between the periphery of the magnetic field and the inner wall of the vacuum chamber as the magnetic field runs downstream. Thus, it is possible to achieve an inplane uniform treatment when carrying out a treatment, such as a thin film deposition or etching, with ECR plasmas for a wafer.
    Type: Grant
    Filed: May 12, 1998
    Date of Patent: May 23, 2000
    Assignee: Tokyo Electron Limited
    Inventors: Yoshinobu Kawai, Yoko Ueda, Nobuo Ishii, Satoru Kawakami, Hideaki Amano
  • Patent number: 6051151
    Abstract: An apparatus and method of producing a negative ion plasma for use in manufacturing of microelectronic devices, particularly etching of microelectronic patterns in semiconductor wafers. A negative ion plasma is produced from a hot electron plasma formed by a RF or UHF plasma source. The negative ion plasma includes positive ions, negative ions and relatively cold electrons, such electrons having an effective electron temperature or average energies less than that for maintaining the plasma. The fields producing the hot plasma are isolated from the negative ion plasma in a cold plasma region by a magnetic filter. The magnetic filter confines the plasmas to provide plasma uniformity at a work piece being etched by the negative ion plasma. The magnetic filter further prevents hot electrons originating in the hot electron plasma from diffusing into the negative ion plasma, while allowing positive ions and cold electrons to diffuse from the hot plasma to the negative ion plasma.
    Type: Grant
    Filed: November 12, 1997
    Date of Patent: April 18, 2000
    Assignee: International Business Machines Corporation
    Inventors: John H. Keller, Dennis K. Coultas
  • Patent number: 6022446
    Abstract: The present invention is embodied in a plasma reactor for processing a workpiece such as a semiconductor wafer having an axis of symmetry, the reactor including a reactor chamber with a ceiling, a pedestal for supporting the workpiece within the chamber under the ceiling, a processing gas supply inlet into the chamber, an RF plasma power source coupled to the pedestal, and a magnetic field source near the ceiling providing a radially symmetrical magnetic field relative to the axis of symmetry within a portion of the chamber near the ceiling. The magnetic field source can include an electromagnet or plural magnets disposed over the ceiling in a radially symmetrical fashion with respect to the axis of symmetry. The plural magnets may be permanent magnets or electromagnets. The radially symmetrical magnetic field penetrates from the ceiling into the chamber to a shallow depth, and the height of the ceiling above the workpiece exceeds the depth.
    Type: Grant
    Filed: August 21, 1995
    Date of Patent: February 8, 2000
    Inventors: Hongching Shan, Bryan Pu, Ji Ding, Michael Welch
  • Patent number: 6020268
    Abstract: In this invention is described a process for controlling the etching of side wall spacers to a prescribed width. A gaseous mixture of an inert gas, CF.sub.4 and CHF.sub.3 in a prescribed ratio, under pressure and with a plasma is flowed within a RIE chamber. A magnetic field in parallel with the surface of the wafer being etched is used to control the oxide/silicon selectivity. The shape and width of the side wall spacers are controlled by controlling the selectivity. Uniformity of the shape of side wall spacers over the surface of a wafer is also produced by the magnetic field which induces a higher etch rate at the edge of the wafer where the oxide coating is the thickest.
    Type: Grant
    Filed: July 13, 1998
    Date of Patent: February 1, 2000
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Min-Chih Cheng
  • Patent number: 5994236
    Abstract: The present invention uses the placement of ferromagnetic cores to improve the nonuniformity of plasma processing and to increase the energy transfer efficiency of plasma sources which couple energy to a plasma through the use of radio frequency current flowing through a coil adjacent to a dielectric window. In addition, eddy current conductive elements can be used either alone or in combination with ferromagnetic cores to increase the nonuniformity adjustment range.
    Type: Grant
    Filed: January 23, 1998
    Date of Patent: November 30, 1999
    Inventor: John Seldon Ogle
  • Patent number: 5981355
    Abstract: A method of forming an isolating region of a semiconductor device including the steps of: forming first insulating layers which vary in width on a substrate; forming trenches which vary in width on the substrate by using the first insulating layers as a mask; forming second insulating layers on the trenches and the first insulating layers; exposing the predetermined portions of the first insulating layers by etching the second insulating layers; and wet-etching the first insulating layers and the non-etched portions of the second insulating layers. In the present invention, an isolating region in the narrow trench is formed without voids by regulating the deposition/etching ratio during the formation of an insulating layer in a trench.
    Type: Grant
    Filed: July 7, 1997
    Date of Patent: November 9, 1999
    Assignee: LG Semicon Co., Ltd.
    Inventor: Seung Ho Lee
  • Patent number: 5945008
    Abstract: The present invention provides a method for plasma control, in which an electric field is generated in the direction perpendicular to the surface of an object to be processed in plasma atmosphere generated in a processing chamber and another electric field is generated in the direction parallel to the surface, and the direction of ion or electron in plasma atmosphere is controlled by controlling the composite electric field composed of both the electric fields. The invention provides also an apparatus for plasma control provided with a perpendicular electric field generating means for generating an electric field in the direction perpendicular to the surface of the object, and a parallel electric field generating means for generating an electric field in the direction parallel to the surface of the object.
    Type: Grant
    Filed: September 26, 1995
    Date of Patent: August 31, 1999
    Assignee: Sony Corporation
    Inventors: Toshiro Kisakibaru, Akira Kojima, Yasushi Kato, Isao Honbori, Satoshi Bannai, Tomohiro Chiba, Toshitaka Kawashima
  • Patent number: 5932488
    Abstract: A dry etching method utilizing electron cyclotron resonance excited by microwaves is divided into at least a first etching step for etching a region which extends to the vicinity of a boundary between the non-etching layer and the etching layer but does not reach the non-etching layer and a second etching step conducted after the first etching step.At least one among the four control factors of output power of the magnetron, electron cyclotron resonance point, etching pressure and magnetic field intensity distribution or a combination of five control factors including the foregoing four plus a high-frequency bias power applied to the rear surface of the object to be etched is changed as desired between the first etching step and the second etching step.
    Type: Grant
    Filed: February 7, 1997
    Date of Patent: August 3, 1999
    Assignee: Citizen Watch Co., Ltd.
    Inventors: Toru Takizawa, Kathuhiko Nishiwaki
  • Patent number: 5891807
    Abstract: A method for forming a bottle shaped trench 20 in a semiconductor substrate 10 includes reactive ion etching a trench having a tapered top portion 25 in the semiconductor device and continuing to reactive ion etch while increasing the temperature of the semiconductor device to impart a reentrant profile 22 to the trench.
    Type: Grant
    Filed: September 25, 1997
    Date of Patent: April 6, 1999
    Assignees: Siemens Aktiengesellschaft, International Business Machines Corporation
    Inventors: K. Paul Muller, Rajiv M. Ranade, Stefan Schmitz
  • Patent number: 5880034
    Abstract: Uniformity of plasma density and potential are increased by reducing plasma confinement through use of a non-uniform, graded magnetic field by asymmetric energization of electromagnets with a waveform including harmonics of a fundamental frequency. The magnetic field strength or intensity decreases in the direction of ExB drift of energetic electrons within the plasma which tends to cause additional ionization in the plasma and a gradient of plasma density and potential. Thus, increase in ionization due to ExB drift is balanced by reduction of plasma confinement. Uniformity of average exposure to the plasma is further increased by rotation of the magnetic field. Uniformity of plasma potential or wafer bias is further improved by modulation of the radio frequency (RF) power used to form the plasma in synchronism with decreases in the magnetic field during switching for magnetic field rotation.
    Type: Grant
    Filed: April 29, 1997
    Date of Patent: March 9, 1999
    Assignee: Princeton University
    Inventor: John H. Keller
  • Patent number: 5872058
    Abstract: A process for filling high aspect ratio gaps on substrates uses conventional high density plasma deposition processes while reducing the concentration of the inert gas, such as Ar, to 0-13% of the total process gas flow. By reducing the inert gas concentration, sputtering or etching is reduced, resulting in reduced sidewall deposition from the sputtered material. Consequently, gaps with aspect ratios of 3.0:1 and higher can be filled without the formation of voids and without damaging circuit elements.
    Type: Grant
    Filed: June 17, 1997
    Date of Patent: February 16, 1999
    Assignee: Novellus Systems, Inc.
    Inventors: Patrick A. Van Cleemput, Thomas W. Mountsier
  • Patent number: 5863841
    Abstract: A plasma diffusion control apparatus is provided with a plurality of wires through which current flows in parallel so that lines of magnetic force are generated in a direction parallel to the plasma wall of the diffusion chamber wall. It is preferable that the wires are located in the neighborhood of the diffusion chamber at equal intervals, and arranged so that the direction of the magnetic field generated by wires are parallel to the direction of movement of the plasma. Since the magnetic field is formed in a direction parallel to the inner wall of the diffusion chamber, it is possible to prevent the diffusion of the plasma to the chamber wall. As a result there is no region which is influenced by strong local magnetic fields perpendicular to the plasma chamber wall, so that it is possible to solve the problems caused by substantial amounts of polymer deposition on the inner wall of the plasma diffusion chamber.
    Type: Grant
    Filed: March 17, 1998
    Date of Patent: January 26, 1999
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kyeong-koo Chi
  • Patent number: 5854137
    Abstract: An improved method of plasma-activated reactive subtractive etching of polycide layers by mixtures of sulfur hexafluoride, hydrogen bromide, and oxygen gases is achieved. After the subtractive etching of the polycide layer is performed, a purging operation of the reaction chamber by admission of a non-reactive gas such as nitrogen followed by evacuation results in the removal of water vapor and other residual species. This purging step inhibits the formation of needle-like crystals of residual compounds thought to form by chemical reaction between hydrogen bromide and water vapor and other species. Such needle-like crystalline residues can be construed as defects in the etched polycide patterns, and their minimization results in increased manufacturing yields after visual inspection. Additionally, the reduced incidence of residual crystalline residues is beneficial in helping to improve subsequent integrated circuit reliability.
    Type: Grant
    Filed: April 29, 1996
    Date of Patent: December 29, 1998
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: So Wein Kuo
  • Patent number: 5830808
    Abstract: The present invention ameliorates the problem in a plasma reactor of plasma attacking an electrostatic chuck and the wafer periphery backside by placing a magnet in the quartz wall adjacent the wafer peripheral edge.
    Type: Grant
    Filed: October 7, 1996
    Date of Patent: November 3, 1998
    Assignee: Applied Materials, Inc.
    Inventor: Robert A. Chapman
  • Patent number: 5827436
    Abstract: A mixed etching gas consisting of boron trichloride, a rare gas, and chlorine is used for etching of an aluminum metal film by dry-etching. In the first step, high frequency power is used to etch and remove alloy grains which tend to form residues and to etch an aluminum metal film in an anisotropic mode. Just before the under-layered silicon film is exposed, the frequency power is lowered but is kept higher than the minimum power required for anisotropic etching to enable etching selectivity with respect to the silicon dioxide film to be achieved.
    Type: Grant
    Filed: March 15, 1996
    Date of Patent: October 27, 1998
    Assignee: Sony Corporation
    Inventors: Yukihiro Kamide, Yuji Takaoka, Yasuaki Yamamichi
  • Patent number: 5824602
    Abstract: A helicon plasma source is controlled by varying the axial magnetic field or rf power controlling the formation of the helicon wave. An energetic electron current is carried on the wave when the magnetic field is 90 G; but there is minimal energetic electron current when the magnetic field is 100 G in one particular plasma source. Similar performance can be expected from other helicon sources by properly adjusting the magnetic field and power to the particular geometry. This control for adjusting the production of energetic electrons can be used in the semiconductor and thin-film manufacture process. By applying energetic electrons to the insulator layer, such as silicon oxide, etching ions are attracted to the insulator layer and bombard the insulator layer at higher energy than areas that have not accumulated the energetic electrons. Thus, silicon and metal layers, which can neutralize the energetic electron currents will etch at a slower or non-existent rate.
    Type: Grant
    Filed: October 21, 1996
    Date of Patent: October 20, 1998
    Assignee: The United States of America as represented by the United States Department of Energy
    Inventors: Arthur W. Molvik, Albert R. Ellingboe
  • Patent number: 5824607
    Abstract: A plasma reactor chamber uses an antenna driven by RF energy (LF, MF, or VHF) which is inductively coupled inside the reactor dome to provide a plasma source. The antenna generates a high density, low energy plasma inside the chamber. The chamber includes a plurality of magnets for generating magnetic fields. Ion flux is concentrated in certain areas of the chamber and is diverted from other areas of the chamber by using these magnetic fields. Various magnetic and voltage processing enhancement techniques are disclosed, along with etch processes, deposition processes and combined etch/deposition processes. The disclosed invention provides a means of cleaning the deposition residues from the reactor walls while minimizing damage to the wafer pedestal.
    Type: Grant
    Filed: February 6, 1997
    Date of Patent: October 20, 1998
    Assignee: Applied Materials, Inc.
    Inventors: John Trow, Tetsuya Ishikawa
  • Patent number: 5783102
    Abstract: A method of manufacturing semiconductor chips uses negative plasma etching. The plasma may be produced by an inductive plasma source. A magnetic field is used to reduce diffusion of hot electrons, producing a uniform negative plasma to etch a work piece.
    Type: Grant
    Filed: February 5, 1996
    Date of Patent: July 21, 1998
    Assignee: International Business Machines Corporation
    Inventor: John Howard Keller
  • Patent number: 5776834
    Abstract: A method of forming low dielectric insulation between those pairs of conductive lines, of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a nonconformal source with a poor step function for the insulating material, such as silane (SiH.sub.4) as the silicon (Si) source for silicon dioxide (SiO.sub.2), so as to create, in the gap, a large void whose dielectric constant is slightly greater than 1. After the formation of the void in the 0.5 microns or less gaps, the deposited nonconformal material is etched either simultaneously or sequentially along with deposition to fill the remaining gaps with void free insulation. The surface of the deposited insulating material is planarized at the desired thickness. Alternatively, a thin conformal insulating layer is first deposited as a liner on the conductive lines.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: July 7, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Steven Avanzino, Darrell M. Erb, Robin Cheung, Rich Klein, Pervaiz Sultan
  • Patent number: 5700741
    Abstract: A method for limiting contaminant particle deposition upon integrated circuit layers within plasma assisted process reactor chambers. First, there is undertaken a plasma assisted process upon an integrated circuit layer within a plasma assisted process reactor chamber. The plasma assisted process employs a reactant gas composition, a first radio frequency power and a first reactor chamber pressure appropriate to the plasma assisted process and the integrated circuit layer. There is then undertaken a first plasma purge step for a first purge time immediately following the plasma assisted process. The first plasma purge step employs a first purge gas composition, a second radio frequency power and a second reactor chamber pressure. The second radio frequency power is lower than the first radio frequency power and the second reactor chamber pressure is higher than the first reactor chamber pressure.
    Type: Grant
    Filed: May 20, 1996
    Date of Patent: December 23, 1997
    Assignee: Vanguard International Semiconductor Corporation
    Inventor: Chin-Cherng Liao
  • Patent number: 5662819
    Abstract: Controlling ion/radical ratio and monoatomic/polyatomic radical ratio in a process plasma provides improved processing performance during inductively-coupled plasma and/or helicon wave plasma processing of substrate materials. In a plasma processing method employing inductively coupled plasma, high frequency current to a high frequency antenna is intermittently supplied in a controlled manner to control the state of gas dissociation to promote formation of polyatomic radicals. In a plasma processing method employing helicon wave plasma, current supplied to a magnetic field generator is intermittently supplied in a controlled manner to promote formation of ions. In a preferred method both the high frequency current and magnetic field generating current are varied in a controlled manner to provide a variable plasma composition, i.e., radical rich plasma or ion-rich plasma, as desired, for improved plasma processing especially improved selective anisotropic dry etching at high etch rate.
    Type: Grant
    Filed: February 3, 1995
    Date of Patent: September 2, 1997
    Assignee: Sony Corporation
    Inventor: Shingo Kadomura
  • Patent number: 5658440
    Abstract: A process called surface image transfer etching (SITE) is used to etch patterned photoresist so as to more completely transfer a well-defined pattern formed in the top surface (10a) of a material to the bulk of the material (12). The process uses no mask, but employs only a sputter etching process where the etching rates of surfaces not normal to the ion trajectories are greatly enhanced over the etching rates of surfaces normal to the ion trajectories.
    Type: Grant
    Filed: November 6, 1995
    Date of Patent: August 19, 1997
    Assignee: Advanced Micro Devices Incorporated
    Inventors: Michael K. Templeton, Subhash Gupta