Sequential Etching Steps On A Single Layer Patents (Class 438/734)
  • Patent number: 10504792
    Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Patent number: 10381355
    Abstract: A configuration of components formed on a semiconductor structure is provided. A non-limiting example of the configuration includes a substrate having a first section doped with a first dopant and a second section doped with a second dopant. The configuration further includes an insulator interposed between the first and second sections. A first fin extends upwardly from the first section, and second and third fins extend upwardly from the second section. A conductor is configured to be shared between proximal gates operably interposed between the first and second fins. A dielectric material is configured to separate proximal gates operably interposed between the second and third fins.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: August 13, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peng Xu, Kangguo Cheng, Zhenxing Bi, Juntao Li
  • Patent number: 9385030
    Abstract: Aspects of the present invention relate to approaches for preventing contact encroachment in a semiconductor device. A first portion of a contact trench can be etched partway to a source-drain region of the semiconductor device. A dielectric liner can be deposited in this trench. A second etch can be performed on the lined trench to etch the contact trench channel the remainder of the way to the source-drain region. This leaves a portion of the dielectric liner remaining in the trench (e.g., covering the vertical walls of the trench) after the second etch.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: July 5, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yong M. Lee, Yue Hu, Wen-Pin Peng
  • Patent number: 9371427
    Abstract: A pattern is formed by forming a first pattern on a first film, forming a block copolymer layer including a first block chain and a second block chain on the first pattern, forming a second pattern, forming a second film on the second pattern, selectively removing the second film until the second pattern is exposed, forming a third pattern, and processing the first film using the third pattern as a mask. The second pattern is formed by microphase-separating the block copolymer layer, and removing the first block chain or the second block chain. The second film is formed by applying a material having an etch rate that is less than an etch rate of a material of the first pattern and the second pattern. The third pattern is formed by selectively removing the second pattern and the first pattern using the second film as a mask.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: June 21, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Katsutoshi Kobayashi, Yusuke Kasahara, Hiroki Yonemitsu, Hitoshi Kubota, Ayako Kawanishi
  • Patent number: 9276063
    Abstract: The invention is drawn to novel nanostructures comprising hollow nanospheres and nanotubes for use as chemical sensors, conduits for fluids, and electronic conductors. The nanostructures can be used in microfluidic devices, for transporting fluids between devices and structures in analytical devices, for conducting electrical currents between devices and structure in analytical devices, and for conducting electrical currents between biological molecules and electronic devices, such as bio-microchips.
    Type: Grant
    Filed: October 29, 2011
    Date of Patent: March 1, 2016
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Jin Z. Zhang, Adam Schwartzberg, Tammy Y. Olson
  • Patent number: 9165878
    Abstract: Semiconductor packages and methods for forming a semiconductor package are presented. The method includes providing a package substrate having first and second major surfaces. The package substrate includes at least one substrate layer having at least one cavity. Interconnect structure is formed. At least one conductive stud is formed within the cavity and a conductive trace and a connection pad are formed over the first major surface of the package substrate and are coupled to top surface of the conductive stud. A package pad is formed and is directly coupled to the conductive stud. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structure. A cap is formed over the package substrate to encapsulate the die.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: October 20, 2015
    Assignee: UNITED TEST AND ASSEMBLY CENTER LTD.
    Inventors: Yong Bo Yang, Chun Hong Wo
  • Patent number: 9035305
    Abstract: Reducing hydrogen concentration in a channel formation region of an oxide semiconductor is important in stabilizing threshold voltage of a transistor including an oxide semiconductor and improving reliability. Hence, hydrogen is attracted from the oxide semiconductor and trapped in a region of an insulating film which overlaps with a source region and a drain region of the oxide semiconductor. Impurities such as argon, nitrogen, carbon, phosphorus, or boron are added to the region of the insulating film which overlaps with the source region and the drain region of the oxide semiconductor, thereby generating a defect. Hydrogen in the oxide semiconductor is attracted to the defect in the insulating film. The defect in the insulating film is stabilized by the presence of hydrogen.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: May 19, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Tsubuku, Yusuke Nonaka, Noritaka Ishihara, Masashi Oota, Hideyuki Kishida
  • Patent number: 9005463
    Abstract: A method of forming a substrate opening includes forming a plurality of side-by-side openings in a substrate. At least some of immediately adjacent side-by-side openings are formed in the substrate to different depths relative one another. Walls that are laterally between the side-by-side openings are removed to form a larger opening having a non-vertical sidewall surface where the walls were removed in at least one straight-line vertical cross-section that passes through the sidewall surface orthogonally to the removed walls.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: April 14, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Mark Kiehlbauch
  • Patent number: 8999177
    Abstract: Out-of-plane microneedle manufacturing process comprising the simultaneous creation of a network of microneedles and the creation of a polygonal shaped hat (2) above each microneedle (1) under formation, said process comprising the following steps: providing bridges (3) between the hats (3), maintaining the bridges (3) during the remaining microneedle manufacturing steps, removing the bridges (3), together with the hats (2), when the microneedles (1) are formed.
    Type: Grant
    Filed: October 17, 2008
    Date of Patent: April 7, 2015
    Assignee: Debiotech S.A.
    Inventors: Astrid Cachemaille, Francois Cannehan
  • Patent number: 8999777
    Abstract: The present disclosure discloses a method of fabricating a semiconductor device. A first layer is formed over a substrate. A patterned second layer is then formed over the first layer. The patterned second layer includes an opening. A spacer material is then deposited in the opening, thereby reducing the opening in a plurality of directions. A direction-specific trimming process is performed to the spacer material and the second layer. Thereafter, the first layer is patterned with the second layer.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming Chyi Liu, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 8993452
    Abstract: Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Matt Yeh, Shun Wu Lin, Chi-Chun Chen, Ryan Chia-Jen Chen, Yi-Hsing Chen, Chien-Hao Chen, Donald Y. Chao, Kuo-Bin Huang
  • Patent number: 8986556
    Abstract: A TAMR (Thermally Assisted Magnetic Recording) write head is formed with a narrow pole tip, a trailing edge magnetic shield and, optionally, a plasmon shield. The narrow pole tipped write head uses the energy of laser generated edge plasmons, formed in a plasmon generating layer, to locally heat a PMR magnetic recording medium slightly below its Curie temperature, Tc. When combined with the effects of the narrow tip, this local heating to a temperature below Tc is sufficient to create good transitions and narrow track widths in the magnetic medium. The write head is capable of writing effectively on state-of-the-art PMR recording media having Hk of 20 kOe or more.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: March 24, 2015
    Assignee: Headway Technologies, Inc.
    Inventors: Xuhui Jin, Yuchen Zhou, Kenichi Takano, Joe Smyth
  • Patent number: 8980762
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a film having different filling properties dependent on space width above the patterning film to cover the first line patterns and the second line patterns to form the film on the first line patterns and on the first inter-line pattern space while making a cavity in the first inter-line pattern space and to form the film on at least a bottom portion of the second inter-line pattern space and a side wall of each of the second line patterns. The method includes performing etch-back of the film to remove the film on the first line patterns and on the first inter-line pattern space while causing the film to remain on at least the side wall of the second line patterns.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazunori Iida, Yuji Kobayashi
  • Patent number: 8980756
    Abstract: Embodiments of a method for device fabrication by reverse pitch reduction flow include forming a first pattern of features above a substrate and forming a second pattern of pitch-multiplied spacers subsequent to forming the first pattern of features. In embodiments of the invention the first pattern of features may be formed by photolithography and the second pattern of pitch-multiplied spacers may be formed by pitch multiplication. Other methods for device fabrication are provided.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: March 17, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Luan C. Tran, Raghupathy Giridhar
  • Patent number: 8975088
    Abstract: Various embodiments of the invention relate to etching processes used in fabrication of MTJ cells in an MRAM device. The various embodiments can be used in combination with each other. The first embodiment adds a hard mask buffer layer between a hard mask and a top electrode. The second embodiment uses a multilayered etching hard mask. The third embodiment uses a multilayered top electrode structure including a first Cu layer under a second layer such as Ta. The fourth embodiment is a two-phase etching process used for the bottom electrode to remove re-deposited material while maintaining a more vertical sidewall etching profile. In the first phase the bottom electrode layer is removed using carbonaceous reactive ion etching until the endpoint. In the second phase an inert gas and/or oxygen plasma is used to remove the polymer that was deposited during the previous etching processes.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: March 10, 2015
    Assignee: Avalanche Technology, Inc.
    Inventors: Kimihiro Satoh, Yiming Huai, Jing Zhang, Rajiv Yadav Ranjan, Parviz Keshtbod, Roger K. Malmhall
  • Publication number: 20150064927
    Abstract: A surface planarization method of thin film and a preparing method of an array substrate relate to a display field, and can solve the technical problem that the conventional dry etching severely damages the surface flatness of other film layers below the one being etched, thereby improving the display properties of the LCD. The preparing method of the array substrate comprises patterning a non-metallic layer (4) by a dry etching. And following the step of patterning a non-metallic layer (4) by the dry etching, the method further comprises performing surface planarization on a first film layer (3) to recover the first film layer (3) with a rough surface caused by the dry etching to be planar. The first film layer (3) is located below the non-metallic layer (4).
    Type: Application
    Filed: June 5, 2013
    Publication date: March 5, 2015
    Applicants: BEIJING BOE OPOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Lei Chen, Ziqi Xia, Wukun Dai, Jiapeng Li, Xiuhong Jin, Fengguo Wang, Lei Zhang, Miao Qiu
  • Patent number: 8969213
    Abstract: A metal layer is deposited over an underlying material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation and/or nitridation. A hard mask portion is formed over the metal layer. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. The sequence of a surface pull back of the hard mask portion, trench etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a line pattern having a spacing that is not limited by lithographic minimum dimensions.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Chiahsun Tseng, David V. Horak, Chun-chen Yeh, Yunpeng Yin
  • Patent number: 8962490
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon, wherein at least one metal gate is formed in the ILD layer and at least one source/drain region is adjacent to two sides of the metal gate; forming a first dielectric layer on the ILD layer; forming a second dielectric layer on the first dielectric layer; performing a first etching process to partially remove the second dielectric layer; utilizing a first cleaning agent for performing a first wet clean process; performing a second etching process to partially remove the first dielectric layer; and utilizing a second cleaning agent for performing a second wet clean process, wherein the first cleaning agent is different from the second cleaning agent.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: February 24, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Ching-Wen Hung, Jia-Rong Wu, Chih-Sen Huang, Chieh-Te Chen
  • Patent number: 8956882
    Abstract: According to one embodiment, a method of manufacturing a magnetoresistive element, the method includes forming a first non-magnetic layer on a first magnetic layer, forming a second magnetic layer on the first non-magnetic layer, forming a second non-magnetic layer on the second magnetic layer, forming a third magnetic layer on the second non-magnetic layer, patterning the third magnetic layer by a RIE using an etching gas including a noble gas and a nitrogen gas until a surface of the second non-magnetic layer is exposed, and patterning the second non-magnetic layer and the second magnetic layer after patterning of the third magnetic layer.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: February 17, 2015
    Inventors: Kazuhiro Tomioka, Satoshi Seto, Masatoshi Yoshikawa, Satoshi Inada
  • Patent number: 8932960
    Abstract: Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: January 13, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Luan C. Tran
  • Patent number: 8921189
    Abstract: A method for fabricating a semiconductor device including a first region and a second region, wherein pattern density of etch target patterns formed in the second region is lower than that of etch target patterns formed in the first region includes providing a substrate including the first region and the second region, forming an etch target layer over the substrate, forming a hard mask layer over the etch target layer, etching the hard mask layer to form a first and a second hard mask pattern in the first and the second regions, respectively, reducing a width of the second hard mask pattern formed in the second region and etching the etch target layer using the first hard mask pattern and the second hard mask pattern having the reduced width as an etch barrier to form the etch target patterns in the first and the second regions.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: December 30, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jae-Seon Yu, Sang-Rok Oh
  • Patent number: 8907458
    Abstract: Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Shom Ponoth, David V. Horak, Takeshi Nogami, Chih-Chao Yang
  • Patent number: 8901007
    Abstract: The present disclosure is directed to a method of manufacturing a semiconductor structure in which a low-k dielectric layer is formed over a semiconductor substrate. Features can be formed proximate to the low-k dielectric layer by plasma etching with a plasma formed of a mixture of a CO2, CO, or carboxyl-containing source gas and a fluorine-containing source gas. The method allows for formation of damascene structures without encountering the problems associated with damage to a low-K dielectric layer.
    Type: Grant
    Filed: January 3, 2013
    Date of Patent: December 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Hsiung Tsai, Chung-Ju Lee, Sunil Kumar Singh, Tien-I Bao
  • Patent number: 8894870
    Abstract: A system and method for etching a material, including a compound having a formulation of XYZ, wherein X and Y are one or more metals and Z is selected from one or more Group 13-16 elements, such as carbon, nitrogen, boron, silicon, sulfur, selenium, and tellurium, are disclosed. The method includes a first etch process to form one or more first volatile compounds and a metal-depleted layer and a second etch process to remove at least a portion of the metal-depleted layer.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: November 25, 2014
    Assignee: ASM IP Holding B.V.
    Inventors: Jereld Lee Winkler, Eric James Shero, Fred Alokozai
  • Patent number: 8895431
    Abstract: A method for fabricating a semiconductor device includes: forming an interlayer insulating film on a substrate; forming a first hard mask formation film on the interlayer insulating film; altering the first hard mask formation film; after the altering of the first hard mask formation film, transferring an interconnect groove pattern to the altered first hard mask formation film to form a first hard mask made of the altered first hard mask formation film; and etching the interlayer insulating film using the first hard mask to form an interconnect groove in the interlayer insulating film. The first hard mask formation film is made of a metal film or a metallic compound film.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: November 25, 2014
    Assignee: Panasonic Corporation
    Inventors: Takeshi Harada, Toru Hinomura, Naoki Torazawa, Tatsuya Kabe
  • Patent number: 8877634
    Abstract: The inventive concept provides methods of manufacturing semiconductor devices having a fine pattern. In some embodiments, the methods comprise forming an etch-target film on a substrate, forming a first mask pattern on the etch-target film, forming a second mask pattern by performing an ion implantation process in the first mask pattern, and etching the etch-target film using the second mask pattern.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: November 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Woon Shin, Bong-Hyun Kim, Su-Min Kim, Hyo-Jung Kim, Chang-Min Park, Soo-Jin Hong
  • Publication number: 20140319693
    Abstract: A method of forming a semiconductor device is disclosed. Provided is a substrate having at least one MOS device, at least one metal interconnection and at least one MOS device formed on a first surface thereof. A first anisotropic etching process is performed to remove a portion of the substrate from a second surface of the substrate and thereby form a plurality of vias in the substrate, wherein the second surface is opposite to the first surface. A second anisotropic etching process is performed to remove another portion of the substrate from the second surface of the substrate and thereby form a cavity in the substrate, wherein the remaining vias are located below the cavity. An isotropic etching process is performed to the cavity and the remaining vias.
    Type: Application
    Filed: April 25, 2013
    Publication date: October 30, 2014
    Applicant: United Microelectronics Corp.
    Inventors: Meng-Jia Lin, Chang-Sheng Hsu, Kuo-Hsiung Huang, Wei-Hua Fang, Shou-Wei Hsieh, Te-Yuan Wu, Chia-Huei Lin
  • Patent number: 8859431
    Abstract: The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Post silicidation residues of nickel and platinum may not be removed adequately just by an aqua regia solution (comprising a mixture of nitric acid and hydrochloric acid). Therefore, embodiments of the invention provide a multi-step residue cleaning, comprising exposing the substrate to an aqua regia solution, followed by an exposure to a chlorine gas or a solution comprising dissolved chlorine gas, which may further react with remaining platinum residues, rendering it more soluble in aqueous solution and thereby dissolving it from the surface of the substrate.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: October 14, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Anh Duong, John Foster, Olov Karlsson, James Mavrinac, Usha Raghuram
  • Patent number: 8853054
    Abstract: A method is provided for preparing multilayer semiconductor structures, such as silicon-on-insulator wafers, having reduced warp and bow. Reduced warp multilayer semiconductor structures are prepared by forming a dielectric structure on the exterior surfaces of a bonded pair of a semiconductor device substrate and a semiconductor handle substrate having an intervening dielectric layer therein. Forming a dielectric layer on the exterior surfaces of the bonded pair offsets stresses that may occur within the bulk of the semiconductor handle substrate due to thermal mismatch between the semiconductor material and the intervening dielectric layer as the structure cools from process temperatures to room temperatures.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: October 7, 2014
    Assignee: SunEdison Semiconductor Limited
    Inventors: Guoqiang Zhang, Jeffrey L. Libbert
  • Patent number: 8846541
    Abstract: Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and the dual mask layer. The methods may also include forming a first spacer on a sidewall of the first structure and a second spacer on a sidewall of the second structure. The methods may further include removing the first structure while maintaining at least a portion of the second structure.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: September 30, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Ho Min, O-Ik Kwon, Bum-Soo Kim, Dong-Chan Kim, Myeong-Cheol Kim
  • Patent number: 8835210
    Abstract: The present invention reduces the time required to manufacture a solar cell. After etching main surfaces (10B1, 10B2) of a crystalline silicon substrate (10B) using one etching solution, the main surfaces (10B1, 10B2) of the crystalline silicon substrate (10B) are etched at a lower etching rate than the etching performed using the one etching solution by using another etching solution that has a higher concentration of etching components than the one etching solution. In this way, a textured structure is formed in the main surfaces (10B1, 10B2) of the crystalline silicon substrate (10B).
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: September 16, 2014
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Takuo Nakai, Naoki Yoshimura, Masaki Shima
  • Patent number: 8828815
    Abstract: First, a semiconductor substrate having a first active region and a second active region is provided. The first active region includes a first transistor and the second active region includes a second transistor. A first etching stop layer, a stress layer, and a second etching stop layer are disposed on the first transistor, the second transistor and the isolation structure. A first etching process is performed by using a patterned photoresist disposed on the first active region as a mask to remove the second etching stop layer and a portion of the stress layer from the second active region. The patterned photoresist is removed, and a second etching process is performed by using the second etching stop layer of the first active region as a mask to remove the remaining stress layer and a portion of the first etching stop layer from the second active region.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: September 9, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Pei-Yu Chou, Shih-Fang Tzou, Jiunn-Hsiung Liao
  • Patent number: 8808555
    Abstract: Provided is a method of manufacturing a substrate for a liquid discharge head including a first face, energy generating elements which generate the energy to be used to discharge a liquid to a second face opposite to the first face, and liquid supply ports for supplying the liquid to the energy generating elements. The method includes preparing a silicon substrate having, at the first face, an etching mask layer having an opening corresponding to a portion where the liquid supply ports are to be formed, and having first recesses provided within the opening, and second recesses provided in the region of the second face where the liquid supply ports are to be formed, the first recesses and the second recesses being separated from each other by a portion of the substrate; and etching the silicon substrate by crystal anisotropic etching from the opening of the first face to form the liquid supply ports.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: August 19, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Keiji Watanabe, Shuji Koyama, Hiroyuki Abo, Keiji Matsumoto
  • Patent number: 8796107
    Abstract: Provided are methods for fabricating a semiconductor device. The methods include forming a hard mask pattern on a semiconductor substrate, forming a first trench having a first width and a second trench having a second width on the semiconductor substrate using the hard mask pattern as a mask, forming an oxide film on the hard mask pattern and the first and second trenches, forming first and second isolation films on the first and second trenches by planarizing the oxide film until the hard mask pattern is exposed, and etching the first isolation film by a first thickness by performing dry cleaning on the semiconductor substrate and etching the second isolation film by a second thickness different from the first thickness.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: August 5, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kevin Ahn, Bo-Un Yoon, Jeong-Nam Han
  • Patent number: 8791026
    Abstract: A method and an apparatus for treating a silicon substrate for effectively removing a silicon oxide film formed on a surface of a silicon film and improving surface uniformity of the silicon film. The method comprises providing a substrate including a silicon film; providing a first fluid, which is capable of etching a silicon oxide film, to a surface of the substrate in a first time band; providing a second fluid containing water to the surface of the substrate in a second time band, which is different from the first time band; and providing a third fluid, which is capable of etching the silicon oxide film, has different ingredients as compared to the first fluid, and has high etching ratio with respect to the silicon oxide film, to a surface of the substrate in a third time band, which is different from the first time band and the second time band.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: July 29, 2014
    Assignee: MMTech Co., Ltd.
    Inventors: Kil Soo An, Seung Il Chang
  • Patent number: 8765587
    Abstract: A method of manufacturing non-volatile memory devices includes forming a gate insulating layer and a first conductive layer over a semiconductor substrate, etching the first conductive layer and the gate insulating layer to expose part of the semiconductor substrate, forming trenches at a target depth of the semiconductor substrate by repeatedly performing a dry etch process for etching the exposed semiconductor substrate and a cleaning process for removing residues generated in the dry etch process, forming isolation layers within the trenches, forming a dielectric layer on a surface of the entire structure in which the isolation layers are formed, and forming a second conductive layer on the dielectric layer.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: July 1, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Su Hyun Lim, Seung Cheol Lee
  • Patent number: 8759219
    Abstract: A planarization method of manufacturing a semiconductor component is provided. A dielectric layer is formed above a substrate and defines a trench therein. A barrier layer and a metal layer are formed in sequence in the trench. A first planarization process is applied to the metal layer by using a first reactant so that a portion of the metal layer is removed. An etching rate of the first reactant to the metal layer is greater than that of the first reactant to the barrier layer. A second planarization process is applied to the barrier layer and the metal layer by using a second reactant so that a portion of the barrier layer and the metal layer are removed to expose the dielectric layer. An etching rate of the second reactant to the barrier layer is greater than that of the second reactant to the metal layer.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: June 24, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Ya-Hsueh Hsieh, Teng-Chun Tsai, Wen-Chin Lin, Hsin-Kuo Hsu, Ren-Peng Huang, Chih-Hsien Chen, Chih-Chin Yang, Hung-Yuan Lu, Jen-Chieh Lin, Wei-Che Tsao
  • Patent number: 8753974
    Abstract: Structures and methods for the dissipation of charge build-up during the formation of cavities in semiconductor substrates.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: June 17, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Brian Griffin, Russ Benson
  • Patent number: 8741780
    Abstract: A structural alternative to retro doping to reduce transistor leakage is provided by providing a liner in a trench, undercutting a conduction channel region in an active semiconductor layer, etching a side, corner and/or bottom of the conduction channel where the undercut exposes semiconductor material in the active layer and replacing the removed portion of the conduction channel with insulator. This shaping of the conduction channel increases the distance to adjacent circuit elements which, if charged, could otherwise induce a voltage and cause a change in back-channel threshold in regions of the conduction channel and narrows and reduces cross-sectional area of the channel where the conduction in the channel is not well-controlled; both of which effects significantly reduce leakage of the transistor.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: June 3, 2014
    Assignee: International Business Machines Corporation
    Inventors: Joseph Ervin, Jeffrey B. Johnson, Paul C. Parries, Chengwen Pei, Geng Wang, Yanli Zhang
  • Patent number: 8741778
    Abstract: A method of etching silicon oxide from a multiple trenches is described which allows more homogeneous etch rates among trenches. The surfaces of the etched silicon oxide within the trench following the etch may also be smoother. The method includes two dry etch stages followed by a sublimation step. The first dry etch stage removes silicon oxide quickly and produces large solid residue granules. The second dry etch stage remove silicon oxide slowly and produces small solid residue granules in amongst the large solid residue granules. Both the small and large solid residue are removed in the ensuing sublimation step. There is no sublimation step between the two dry etch stages.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: June 3, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Dongqing Yang, Jing Tang, Nitin Ingle
  • Patent number: 8735295
    Abstract: A method for fabricating a dual damascene structure includes the following steps. At first, a dielectric layer, a dielectric mask layer and a metal mask layer are sequentially formed on a substrate. A plurality of trench openings is formed in the metal mask layer, and a part of the metal mask layer is exposed in the bottom of each of the trench openings. Subsequently, a plurality of via openings are formed in the dielectric mask layer, and a part of the dielectric mask layer is exposed in a bottom of each of the via openings. Furthermore, the trench openings and the via openings are transferred to the dielectric layer to form a plurality of dual damascene openings.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: May 27, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chang-Hsiao Lee, Hsin-Yu Chen, Yu-Tsung Lai, Jiunn-Hsiung Liao, Shih-Chun Tsai
  • Patent number: 8722532
    Abstract: A first wiring is disposed over a semiconductor substrate. A first via is disposed over the first wiring. Further, the bottom surface of the first via is in contact with the first wiring. A first insulation layer is disposed over the semiconductor substrate, and is in contact with at least the top surface of the first wiring and the side surface of the first via. At least a part of each side surface of the first wiring and the first via cuts off each metal crystal grain.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: May 13, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuya Usami, Hiroshi Kitajima
  • Patent number: 8716140
    Abstract: A micropattern is joined to a substrate (W1) by: a first group of covering step and micropattern forming step by etching in a transfer step; and a second group of covering step and micropattern forming step by etching in the transfer step.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: May 6, 2014
    Assignee: Toshiba Kikai Kabushiki Kaisha
    Inventors: Hiroshi Goto, Hiroshi Okuyama, Mitsunori Kokubo, Kentaro Ishibashi
  • Patent number: 8716144
    Abstract: A method for manufacturing a semiconductor device for forming a deep hole in a substrate by using a photoresist film formed on the substrate includes a positioning step of positioning a substrate inside an etching chamber, the substrate having a photoresist film including an opening part formed thereon, a first etching step of performing plasma etching on the substrate positioned inside the etching chamber by using a first mixed gas including at least SiF4 and O2 with the photoresist film as a mask, and a second etching step of forming a hole in the substrate by performing plasma etching on the substrate by using a second mixed gas including at least SF6, O2, and HBr after the first etching step.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: May 6, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Shuichiro Uda, Koji Maruyama, Yusuke Hirayama
  • Patent number: 8703617
    Abstract: The present application discloses provides a method for planarizing an interlayer dielectric layer, comprising the steps of: providing a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack, performing a first RIE on the multilayer structure, in which a reaction chamber pressure is controlled in such a manner that an etching rate of the portion of the at least one sacrificial layer at a center of a wafer is higher than that at an edge of the wafer, so as to obtain a concave etching profile; performing a second RIE on the multilayer structure to completely remove the sacrificial layer and a part of the insulating layer, so as to obtain the insulating layer having a planar surface which serves as an interlayer dielectric layer.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: April 22, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huaxiang Yin, Qiuxia Xu, Lingkuan Meng, Tao Yang, Dapeng Chen
  • Patent number: 8703604
    Abstract: Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: April 22, 2014
    Assignee: International Business Machines Corporation
    Inventors: Shom Ponoth, David V. Horak, Takeshi Nogami, Chih-Chao Yang
  • Patent number: 8703618
    Abstract: A micropattern is joined to a substrate (W1) by: a first group of covering step and micropattern forming step by etching in a transfer step; and a second group of covering step and micropattern forming step by etching in the transfer step.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: April 22, 2014
    Assignee: Toshiba Kikai Kabushiki Kaisha
    Inventors: Hiroshi Goto, Hiroshi Okuyama, Mitsunori Kokubo, Kentaro Ishibashi
  • Patent number: 8703606
    Abstract: When a wiring structure is formed by a trench-first dual damascene method, a first hard mask for forming via holes and a second hard mask for forming wiring trenches are sequentially formed on an interlayer insulating film, openings are formed at the first hard mask while using the second hard mask as a mask, and thereafter, the openings are expanded in a lateral direction by an isotropic etching to form openings, via holes are formed by etching the interlayer insulating film while using the first hard mask and the second hard mask as masks, and wiring trenches communicating with the via holes are formed by etching the interlayer insulating film while using the second hard mask as a mask.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: April 22, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Tomoyuki Kirimura
  • Patent number: 8703620
    Abstract: A method for fabricating an integrated circuit from a semiconductor substrate having formed thereon over a first portion of the semiconductor substrate a hard mask layer and having formed thereon over a second portion of the semiconductor substrate an oxide layer. The first portion and the second portion are electrically isolated by a shallow trench isolation feature. The method includes removing the oxide layer from over the second portion and recessing the surface region of the second portion by applying an ammonia-hydrogen peroxide-water (APM) solution to form a recessed surface region. The APM solution is provided in a concentration of ammonium to hydrogen peroxide ranging from about 1:1 to about 1:0.001 and in a concentration of ammonium to water ranging from about 1:1 to about 1:20. The method further includes epitaxially growing a silicon-germanium (SiGe) layer on the recessed surface region.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: April 22, 2014
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Joanna Wasyluk, Stephan Kronholz, Berthold Reimer, Sven Metzger, Gregory Nowling, John Foster, Paul Besser
  • Patent number: 8696919
    Abstract: A method for manufacturing a nozzle and an associated funnel in a single plate comprises providing the single plate, the plate being etchable; providing an etch resistant mask on the plate, the mask having a pattern, wherein the pattern comprises a first pattern part for etching the nozzle and a second pattern part for etching the funnel; covering one of the first pattern part and the second pattern part using a first cover; etching one of the nozzle and funnel corresponding to the pattern part not covered in step (c); removing the first cover; etching the other one of the nozzle and funnel; and removing the etch resistant mask.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: April 15, 2014
    Assignee: Oce-Technologies B.V.
    Inventors: René J. Van Der Meer, Hubertus M. J. M. Boesten, Maarten J. Bakker, David D. L. Wijngaards