Abstract: A method is provided for anisotropically etching semiconductor materials such as II-VI and III-V semiconductors. The method involves repeated cycles of plasma sputter etching of semiconductor material with a non-reactive gas through an etch mask, followed by passivation of the side walls by plasma polymerization using a polymer former. Using this procedure small pixels in down-converted light-emitting diode devices can be fabricated.

Abstract: A micropattern is joined to a substrate (W1) by: a first group of covering step and micropattern forming step by etching in a transfer step; and a second group of covering step and micropattern forming step by etching in the transfer step.

Abstract: The method of the preferred embodiments includes the steps of providing a base having a frame portion and a center portion; building a preliminary structure coupled to the base; removing a portion of the preliminary structure to define a series of devices and a plurality of bridges; removing the center portion of the base such that the frame portion defines an open region, wherein the plurality of bridges suspend the series of devices in the open region defined by the frame; and encapsulating the series of devices. The method is preferably designed for the manufacture of semiconductor devices, and more specifically for the manufacture of encapsulated implantable electrodes. The method, however, may be alternatively used in any suitable environment and for any suitable reason.

Abstract: Many current micromachining devices are integrated with materials such as very thick layer of polyimide (10 to 100 um) to offer essential characteristics and properties for various applications; it is inherently difficult and complicated to provide reliable metal interconnections between different levels of the circuits. The present invention is generally related to a novel micromachining process and structure to form metal interconnections in integrated circuits or micromachining devices which are incorporated with thick polyimide films. More particularly, the embodiments of the current invention relates to formation of multi-step staircase structure with tapered angle on polyimide layer, which is therefore capable of offering superb and reliable step coverage for metallization among different levels of integrated circuits, and especially for very thick polyimide layer applications.

Abstract: A method of etching silicon oxide from a multiple trenches is described which allows more homogeneous etch rates among trenches. The surfaces of the etched silicon oxide within the trench following the etch may also be smoother. The method includes two dry etch stages followed by a sublimation step. The first dry etch stage removes silicon oxide quickly and produces large solid residue granules. The second dry etch stage remove silicon oxide slowly and produces small solid residue granules in amongst the large solid residue granules. Both the small and large solid residue are removed in the ensuing sublimation step. There is no sublimation step between the two dry etch stages.

Abstract: A method for forming a plurality of variable linewidth spacers adjoining a plurality of uniformly spaced topographic features uses a conformal resist layer upon a spacer material layer located over the plurality of uniformly spaced topographic features. The conformal resist layer is differentially exposed and developed to provide a differential thickness resist layer that is used as a sacrificial mask when forming the variable linewidth spacers. A method for forming uniform linewidth spacers adjoining narrowly spaced topographic features and widely spaced topographic features over the same substrate uses a masked isotropic etching of a variable thickness spacer material layer to provide a more uniform partially etched spacer material layer, followed by an unmasked anisotropic etching of the partially etched spacer material layer. A related method for forming the uniform linewidth spacers uses a two-step anisotropic etch method that includes at least one masking process step.

Abstract: Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided.

Abstract: The invention discloses a smoothing method to decrease bowing of group III nitride semiconductor substrate. The certain face of group III nitride semiconductor substrates is etched under the appropriate etching recipe and time, the certain morphology such as rod-type and other structures are appeared at the certain face. And such structures releases the compressive stresses at these certain faces, resulting in clearly increasing the bowing radius of the group III nitride semiconductor substrates, finally decreasing the bowing phenomenon of the group III nitride semiconductor substrate.

Abstract: The invention provides a method for forming a via. A first dielectric layer is formed on a substrate. A conductive structure is formed in the first dielectric layer. A second dielectric layer is formed on the first dielectric layer and conductive structure. A first etching step is performed by using a first etching mixture to form a first via in the second dielectric layer. A second etching step is performed by using a second etching mixture to form a second via under the first via. The second via exposes at least a top surface of the conductive structure. An etching rate of the second etching step is slower than the first etching step.

Abstract: It is intended to produce a semiconductor device with a stable gate length, using an end-point detection process based on monitoring a plasma emission intensity during dry etching for setting a gate length.

Abstract: In a method of forming an asymmetric recess, an asymmetric recessed gate structure filling the asymmetric recess, a method of forming the asymmetric recessed gate structure, a semiconductor device having the asymmetric recessed gate structure and a method of manufacturing the semiconductor device, a semiconductor substrate is etched to form a first sub-recess having a first central axis. A second sub-recess is formed under the first sub-recess. The second sub-recess is in communication with the first sub-recess. The second sub-recess has a second central axis substantially parallel with the first central axis. The second central axis is spaced apart from the first central axis.

Abstract: A diaphragm is formed by etching a substrate. This substrate has a first surface provided with a depression by isotropic dry etching, and a second surface opposite the first surface. Furthermore, a through-hole is formed from the depression to the second surface by anisotropic dry etching. The depression and the through-hole are formed by using one resist mask. The depression has a hemispherical shape or a semi-elliptical spherical shape.

Abstract: The present disclosure provides a method for making a semiconductor device. The method includes forming a material layer on a substrate; forming a sacrificial layer on the material layer, where the material layer and sacrificial layer each as a thickness less than 100 angstrom; forming a patterned photoresist layer on the sacrificial layer; applying a first wet etching process to etch the sacrificial layer to form a patterned sacrificial layer using the patterned photoresist layer as a mask; applying a second wet etching process to etch the first material layer; and applying a third wet etching process to remove the patterned sacrificial layer.

Abstract: A manufacturing method of a nitride crystalline film includes following steps. First, a substrate is provided. Next, a first nitride crystalline film is formed on the substrate. A patterned mask is then formed on the first nitride crystalline film. The patterned mask covers a first part of the first nitride crystalline film and exposes a second part of the first nitride crystalline film. Afterwards, the second part is etched, and the first part is maintained. After that, the patterned mask is removed. The first part is then etched to form a plurality of nitride crystal nuclei. Next, a second nitride crystalline film is formed on the substrate, and the second nitride crystalline film is made to cover the nitride crystal nuclei. A nitride film and a substrate structure are also provided.

Abstract: A method for forming an active pillar of a vertical channel transistor includes forming a hard mask pattern on a substrate, etching vertically the substrate using the hard mask pattern as an etch barrier to form an active pillar, and etching horizontally to remove by-product remaining on the exposed substrate, the hard mask pattern and the active pillar and at the same time to reduce line width of the hard mask pattern and the active pillar, wherein a unit cycle in which the vertical etching and the horizontal etching are each performed subsequently once, respectively, is performed repeatedly at least two times or more. According to the present invention, an active pillar having vertical profiles on its sidewalls and having height and line width (or diameter) required in a highly integrated vertical channel transistor can be provided.

Abstract: The present invention improves the yield of integrated circuit manufacture by making the circuit more tolerant of varying thicknesses of the InterLayer Dielectric prior to metallization and interconnection. The sensitivity to the thickness of the ILD is reduced by first coating the devices with an etch stop layer, exposing the areas of the devices where interconnections will be made, selectively etching away the etch stop layer over the interconnection areas, adding the Interlayer Dielectric and then finally etching away the ILD to expose the contacts and continuing the processing through interconnection of the devices.

Abstract: A method and an apparatus for treating a silicon substrate for effectively removing a silicon oxide film formed on a surface of a silicon film and improving surface uniformity of the silicon film. The method comprises providing a substrate including a silicon film; providing a first fluid, which is capable of etching a silicon oxide film, to a surface of the substrate in a first time band; providing a second fluid containing water to the surface of the substrate in a second time band, which is different from the first time band; and providing a third fluid, which is capable of etching the silicon oxide film, has different ingredients as compared to the first fluid, and has high etching ratio with respect to the silicon oxide film, to a surface of the substrate in a third time band, which is different from the first time band and the second time band.

Abstract: In a plasma etching method, a substrate including an underlying film, an insulating film and a resist mask is plasma etched to thereby form a number of holes in the insulating film including a dense region and a sparse region by using a parallel plate plasma etching apparatus for applying a plasma-generating high frequency electric power to a space between an upper and a lower electrode and a biasing high frequency electric power to the lower electrode. The plasma etching method includes mounting the substrate on a mounting table; supplying a first process gas containing carbon and fluorine to form the holes in the insulating film to a depth close to the underlying film; and supplying a second process gas including an inert gas and another gas contain carbon and fluorine to have the holes reach the underlying film while applying a negative DC voltage to the upper electrode.

Abstract: Methods are provided for fabricating a semiconductor device. One embodiment includes forming an insulator layer overlying a semiconductor substrate and depositing a layer of polycrystalline silicon overlying the insulator layer. Conductivity determining impurity ions are implanted into at least an upper portion of the layer of polycrystalline silicon. At least the upper portion of the layer of polycrystalline silicon is etched using a first anisotropic etch chemistry to expose an edge portion of the upper portion. An oxide barrier is formed on the edge portion and a further portion of the layer of polycrystalline silicon is etched using the first anisotropic etch chemistry. Then a final portion of the layer of polycrystalline silicon is etched using a second anisotropic etch chemistry.

Abstract: Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.

Abstract: A method for manufacturing a capacitor electrode by removing a silicon oxide film on a surface of a substrate, including: transforming the silicon oxide film into a reaction product by supplying a gas containing a halogen element to chemically react with the silicon oxide film while controlling temperature of the substrate to a first process temperature; and removing the silicon oxide film transformed to the reaction product while controlling the temperature of the substrate to a second process temperature higher than the first process temperature. The silicon oxide film is a BPSG film.

Abstract: Provided is a semiconductor device. The device includes a substrate having a photo acid generator (PAG) layer on the substrate. The PAG layer is exposed to radiation. A photoresist layer is formed on the exposed PAG layer. The exposed PAG layer generates an acid. The acid decomposes a portion of the formed photoresist layer. In one embodiment, the PAG layer includes organic BARC. The decomposed portion of the photoresist layer may be used as a masking element.

Abstract: A substrate has at least one recess and/or protrusion formed in and/or on a surface thereof so as to scatter or diffract light generated in an active layer. The recess and/or protrusion is formed in such a shape that can reduce crystalline defects in semiconductor layers.

Abstract: A method of forming minute patterns in a semiconductor device, and more particularly, a method of forming minute patterns in a semiconductor device having an even number of insert patterns between basic patterns by double patterning including insert patterns between a first basic pattern and a second basic pattern which are transversely separated from each other on a semiconductor substrate, wherein a first insert pattern and a second insert pattern are alternately repeated to form the insert patterns, the method includes the operation of performing a partial etching toward the second insert pattern adjacent to the second basic pattern, or the operation of forming a shielding layer pattern, thereby forming the even number of insert patterns.

Abstract: Provided are a lead frame, a semiconductor package, and a method of manufacturing the lead frame and the semiconductor package. The lead frame includes: a die pad on which a semiconductor chip is installable; a plurality of lead patterns formed around a circumference of the die pad; an insulating organic material filling etching spaces interposed between the die pad and the lead patterns and structurally supporting the die pad and the lead patterns; and a pre-plating layer formed on both upper and lower surfaces of the die pad and the lead patterns.

Abstract: Methods of forming a semiconductor device can be provided by simultaneously forming a plurality of mask patterns using self-aligned reverse patterning, including respective mask pattern elements having different widths.

Abstract: A substrate processing method that forms an opening, which has a size that fills the need for downsizing a semiconductor device and is to be transferred to an amorphous carbon film, in a photoresist film of a substrate to be processed. Deposit is accumulated on a side wall surface of the opening in the photoresist film using plasma produced from a deposition gas having a gas attachment coefficient S of 0.1 to 1.0 so as to reduce the opening width of the opening.

Abstract: An interlevel dielectric layer, such as a silicon oxide layer, is selectively etched using a plasma etch chemistry including a silicon species and a halide species and also preferably a carbon species and an oxygen species. The silicon species can be generated from a silicon compound, such as SixMyHz, where “Si” is silicon, “M” is one or more halogens, “H” is hydrogen and x?1, y?0 and z?0. The carbon species can be generated from a carbon compound, such as C?M?H?, where “C” is carbon, “M” is one or more halogens, “H” is hydrogen, and ??1, ??0 and ??0. The oxygen species can be generated from an oxygen compound, such as O2, which can react with carbon to form a volatile compound.

Abstract: A method of forming an integrated deep and shallow trench isolation structure comprises depositing a hard mask on a film stack having a plurality of layers formed on a substrate such that the hard mask is deposited on a furthermost layer from the substrate, imprinting a first pattern into the hard mask to define an open end of a first trench, imprinting a second pattern into the hard mask to define an open end of a second trench, and etching into the film stack the first trench to a first depth and the second trench to a second depth such that the first trench and the second trench each define a blind aperture in the surface of the film stack.

Abstract: A method for simultaneous formation of a self-aligned contact of a core region and a local interconnect of a peripheral region of an integrated circuit includes etching a cap dielectric layer to simultaneously form a hole in the core region and a trench in the peripheral region of the cap dielectric layer, etching a dielectric layer to simultaneously form a hole in the core region and a trench in the peripheral region of the dielectric layer of the dielectric layer, etching a liner layer simultaneously on a shoulder of sidewall spacers associated with the hole and with the trench of the dielectric layer without etching the liner layer at a bottom area of the hole and the trench, performing an oxygen flushing to remove polymer residues, and etching simultaneously through the liner layer that lines the bottom area of the hole and the trench.

Abstract: A metal oxide semiconductor (MOS) device includes a substrate, a lower sacrificial membrane adjacent to the substrate, an upper thin film structure adjacent to the lower membrane, and a MOS material deposited on the upper thin film structure.

Abstract: A method of removing residues from an integrated device, in particular residues resulting from processing in HF vapor, is disclosed wherein the fabricated device is exposed to dry water vapor for a period of time sufficient to dissolve the residues in the dry water vapor.

Abstract: Methods of forming integrated circuit devices include forming an integrated circuit substrate having an electrically insulating layer thereon and forming a mask layer pattern having at least first and second openings of different size therein, on the electrically insulating layer. First and second portions of the electrically insulating layer extending opposite the first and second openings, respectively, are simultaneously etched at first and second different etch rates. This etching yields a first trench extending adjacent the first opening that is deeper than a second trench extending adjacent the second opening. Then, the bottoms of the first and second trenches are simultaneously etched to substantially the same depths using an etching process that compensates for the first and second different etch rates.

Abstract: By forming a hardmask layer in combination with one or more cap layers, undue exposure of a sensitive dielectric material to resist stripping etch ambients may be reduced and integrity of the hardmask may also be maintained so that the trench etch process may be performed with a high degree of etch selectivity during the patterning of openings in a metallization layer of a semiconductor device.

Abstract: A method for forming a semiconductor device includes forming a dielectric layer over a substrate. The method further includes forming a select gate layer over the dielectric layer. The method further includes etching the select gate layer at a first etch rate to form a first portion of a sidewall of a select gate, wherein the step of etching the select gate layer at the first etch rate includes using an oxidizing agent to oxidize at least a top portion of the substrate underlying the dielectric layer to form an oxide layer. The method further includes etching the select gate layer at a second etch rate lower than the first etch rate to form a second portion of the sidewall of the select gate, wherein the step of etching the select gate layer at the second etch rate includes removing only a top portion of the dielectric layer.

Abstract: A method of forming IC devices includes providing a substrate and forming a patterned masking layer including at least one masked region having at least one masking layer, and a feature region bounded by the masking layer. Etching forms an etched feature in the substrate, wherein undercutting during the etching forms at least one mask overhang region over a surface portion of the etched feature that is recessed relative to an outer edge of the masking layer. A pullback etch process exclusive of any additional patterning step laterally etches the masking layer. The conditions for the pullback etch retain at least a portion of the masking layer and reduce a length of the mask overhang region by at least 50%, or eliminate the mask overhang region entirely. The etched feature is then filled after the pullback etch process to form a filled etched feature.

Abstract: A conductive barrier material of a metallization system of a semiconductor device may be formed on the basis of one or more deposition/etch cycles, thereby providing a reduced material thickness in the bevel region, while enhancing overall thickness uniformity in the active region of the semiconductor substrate. In some illustrative embodiments, two or more deposition/etch cycles may be used, thereby providing the possibility to select reduced target values for the barrier thickness in the die regions, while also obtaining a significantly reduced thickness in the bevel region.

Abstract: The invention provides a method of processing a wafer using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more measurement procedures, one or more Poly-Etch (P-E) sequences, and one or more metal-gate etch sequences. The MLMIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple process steps. The multiple layers and/or the multiple process steps can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using isotropic and/or anisotropic etch processes.

Abstract: A method for forming contact holes in a semiconductor device includes forming a hard mask layer over an etch target layer, forming a first line pattern in the hard mask layer by etching a portion of the hard mask layer through a primary etch process, forming a second line pattern crossing the first line pattern by etching the hard mask layer including the first line pattern through a secondary etch process, and etching the etch target layer by using the hard mask layer including the first line pattern and the second line pattern as an etch barrier.

Abstract: A two-stage method to remove a metal layer from a substrate surface comprises using a CMP process to remove a first portion of the metal layer from the substrate surface, and using an ALV process to remove a second portion of the copper layer from the substrate surface. The ALV process comprises pulsing a co-reactant into a reactor housing the substrate, wherein the co-reactant reacts with the metal layer to form a volatile metal-containing product, and then evacuating the reactor to volatize and remove the metal-containing product.

Abstract: Exemplary embodiments provide a method for fabricating an integrated circuit (IC) device with reduced streak defects. In one embodiment, the IC device structure can be formed having a first pad oxide-based layer on a front side of a semiconductor substrate and having an oxide-nitride-based structure on a backside of the semiconductor substrate. The IC device structure can be etched to remove a nitride-related material from the backside oxide-nitride-based structure, and further to remove the first pad oxide-based layer from the front side of the semiconductor substrate. On the removed front side of the semiconductor substrate a second pad oxide-based layer can be formed, e.g., for forming an isolation structure for device component or circuitry isolation.

Abstract: A method of producing a semiconductor element includes the steps of forming a wiring portion layer on a substrate; forming an interlayer insulation layer over the substrate and the wiring portion layer, in which a third insulation film, a second insulation film, and a first insulation film are laminated in this order from the substrate; forming a mask pattern on the first insulation film; removing a contact hole forming area of the first insulation film through a wet etching process; removing a contact hole forming area of the second insulation film through an etching process; removing a contact hole forming area of the third insulation film through an etching process; and a contact hole forming step of forming a contact hole in the interlayer insulation layer so that a surface of the wiring portion layer is exposed.

Abstract: Decrease of the off-state current, increase of the on-state current, and reduction of variations of electrical characteristics. A method for manufacturing a channel-etched inversed staggered thin film transistor includes the following steps: removing, by first dry-etching, a part of a semiconductor layer including an impurity element which imparts one conductivity type, which is exposed from the source and drain electrodes, and partially a part of an amorphous semiconductor layer just below and in contact with the part of the semiconductor layer; removing, by second dry-etching, partially the part of the amorphous semiconductor layer which is exposed by the first dry-etching; and performing plasma treatment on the surface of the part of the amorphous semiconductor layer which is exposed by the second dry-etching so that an altered layer is formed.

Abstract: A method is disclosed for the cleaning of a Si surface at low temperatures. Oxide on the Si surface is brought into contact with Ge, which then sublimates off the surface. The Ge contamination remaining after the oxide removal is cleared away by an exposure to an alkali halide. The disclosed cleaning method may by used in semiconductor circuit fabrication for preparing surfaces ahead of epitaxial growth.

Abstract: A method of forming a plurality of nanotubes is disclosed. Particularly, a substrate may be provided and a plurality of recesses may be formed therein. Further, a plurality of nanotubes may be formed generally within each of the plurality of recesses and the plurality of nanotubes may be substantially surrounded with a supporting material. Additionally, at least some of the plurality of nanotubes may be selectively shortened and at least a portion of the at least some of the plurality of nanotubes may be functionalized. Methods for forming semiconductor structures intermediate structures, and semiconductor devices are disclosed. An intermediate structure, intermediate semiconductor structure, and a system including nanotube structures are also disclosed.

Abstract: An area where a lower electrode is in contact with a variable resistance material needs to be reduced to lower the power consumption of a variable resistance memory device. The present invention is to provide a method of producing a variable resistance memory element whereby the lower electrode can be formed smaller. Combining an anisotropic etching process with an isotropic etching process enables the lower electrode to be formed smaller.

Abstract: The present invention in one embodiment provides an etch method that includes providing a structure including a tungsten (W) portion and a titanium nitride (TiN) portion; applying a first etch feed gas of sulfur hexafluoride (SF6) and oxygen (O2), in which the ratio of sulfur hexafluoride (SF6) to oxygen (O2) ranges from 1:3.5 to 1:4.5; and applying a second etch feed gas of nitrogen trifluoride (NF3), helium (He) and chlorine (Cl2), in which the ratio of nitrogen trifluoride (NF3) to chlorine (Cl2) ranges from 1:5 to 2:5 and the ratio of helium (He) to nitrogen trifluoride (NF3) and chlorine (Cl2) ranges from 1:3 to 1:1.

Abstract: There is described a method for creating a thermally-isolated microstructure on a slab of mono-crystalline silicon which uses a hybrid dry-then-wet etch technique that when controlled, can produce microstructures without any silicon adhering underneath, microstructures having small masses of silicon adhering underneath, and microstructures that are still attached to the slab of mono-crystalline silicon via a waisted silicon body. When creating the microstructures with a waisted silicon body, the thermal isolation of the microstructure can be designed by controlling the depth of the etching and the size of the waist.

Abstract: A method of patterning a film stack is described. The method comprises preparing a film stack on a substrate, wherein the film stack comprises a SiCOH-containing layer formed on the substrate, a silicon oxide (SiOx) layer formed on the SiCOH-containing layer, and a mask layer formed on the silicon oxide layer. A pattern is created in the mask layer. Thereafter, the pattern in the mask layer is transferred to the silicon oxide layer using an etching process, and then the mask layer is removed. The pattern in the silicon oxide layer is transferred to the SiCOH-containing layer using a dry plasma etching process formed from a process composition comprising NF3.

Abstract: Methods and structures for interconnects in semiconductor devices are described. A method of forming a mask pattern for a metal layer in an interconnect can include searching a layout for a metal feature with a predetermined size and an interconnect layer aligned thereto, removing the metal feature from the layout to form a modified layout, and reforming the mask pattern using the modified layout. The metal interconnect may include a first pattern of metal lines, each having a minimum feature size in a layout view in no more than one dimension; a dielectric layer on or over the first pattern of metal lines, having a substantially planar horizontal upper surface; and vias or contacts in the dielectric layer, the vias or contacts contacting a top surface of the first pattern of metal lines and a top surface of silicon structures, vias, or contacts below the first pattern of metal lines.