Silicon Oxide Or Glass Patents (Class 438/743)
  • Patent number: 9040430
    Abstract: A method for stripping an organic mask above a porous low-k dielectric film is provided. A steady state flow of a stripping gas, comprising CO2 and CH4 is provided. The stripping gas is formed into a plasma, wherein the plasma strips at least half the organic mask and protects the porous low-k dielectric film, for a duration of providing the steady state flow of the stripping gas.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: May 26, 2015
    Assignee: Lam Research Corporation
    Inventors: John M. Nagarah, Gerardo Delgadino
  • Patent number: 9006106
    Abstract: Methods of removing metal hardmasks in the presence of ultra low-k dielectric films are described. In an example, a method of patterning a low-k dielectric film includes forming a pattern in a metal nitride hardmask layer formed above a low-k dielectric film formed above a substrate. The method also includes etching, using the metal nitride hardmask layer as a mask, the pattern at least partially into the low-k dielectric film, the etching involving using a plasma etch based on SiFx. The etching also involves forming an SiOx passivation layer at least on sidewalls of the low-k dielectric film formed during the etching. The method also includes removing the metal nitride hardmask layer by a dry etch process, where the SiOx passivation layer protects the low-k dielectric film during the removing.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: April 14, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Chia-Ling Kao, Kwang-soo Kim, Sean S. Kang, Srinivas D. Nemani
  • Patent number: 8921232
    Abstract: A method of taper-etching a layer to be etched that is made of a dielectric material and has a top surface. The method includes the steps of: forming an etching mask with an opening on the top surface of the layer to be etched; and taper-etching a portion of the layer to be etched, the portion being exposed from the opening, by reactive ion etching so that a groove having two wall faces intersecting at a predetermined angle is formed in the layer to be etched. The step of taper-etching employs an etching gas containing a first gas contributing to the etching of the layer to be etched and a second gas contributing to the deposition of a sidewall protective film, and changes, during the step, the ratio of the flow rate of the second gas to the flow rate of the first gas so that the ratio increases.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: December 30, 2014
    Inventors: Hironori Araki, Yoshitaka Sasaki, Hiroyuki Ito, Shigeki Tanemura
  • Patent number: 8906729
    Abstract: The invention relates to a micro-device with a cavity, the micro-device comprising a substrate, the method comprising steps of: A) providing the substrate, having a surface and comprising a sacrificial oxide region at the surface; B) covering the sacrificial oxide region with a porous layer being permeable to a vapor HF etchant, and C) selectively etching the sacrificial oxide region through the porous layer using the vapor HF etchant to obtain the cavity. This method may be used in the manufacture of various micro-devices with a cavity, i.e. MEMS devices, and in particular in the encapsulation part thereof, and semiconductor devices, and in particular the BEOL-part thereof.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: December 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Greja Johanna Adriana Maria Verheijden, Roel Daamen, Gerhard Koops
  • Patent number: 8896129
    Abstract: A semiconductor device includes a substrate including a circuit region where a circuit element is formed, a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated, and an electrode pad that is formed on the multilayer wiring layer. An interlayer insulating film is formed in a region of a first wiring layer that is a top layer of the plurality of wiring layers, in the region the electrode pad and the first circuit region overlapping each other in a planar view of the electrode pad.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: November 25, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Ryo Mori, Kazuki Fukuoka, Naozumi Morino, Yoshinori Deguchi
  • Patent number: 8895449
    Abstract: A method of selectively removing fluorocarbon layers from overlying low-k dielectric material is described. These protective plasma treatments (PPT) are delicate alternatives to traditional post-etch treatments (PET). The method includes sequential exposure to (1) a local plasma formed from a silicon-fluorine precursor followed by (2) an exposure to plasma effluents formed in a remote plasma from a fluorine-containing precursor. The remote plasma etch (2) has been found to be highly selective of the residual material following the local plasma silicon-fluorine exposure. The sequential process (1)-(2) avoids exposing the low-k dielectric material to oxygen which would undesirably increase its dielectric constant.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: November 25, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Lina Zhu, Sean S. Kang, Srinivas D. Nemani, Chia-Ling Kao
  • Patent number: 8884405
    Abstract: An integrated circuit includes a substrate and passivation layers. The passivation layers include a bottom dielectric layer formed over the substrate for passivation, a doped dielectric layer formed over the bottom dielectric layer for passivation, and a top dielectric layer formed over the doped dielectric layer for passivation.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chi Chuang, Kun-Ming Huang, Hsuan-Hui Hung, Ming-Yi Lin
  • Patent number: 8853094
    Abstract: A method for manufacturing a semiconductor structure comprising complementary bipolar transistors, wherein for manufacture of a PNP-type structure, an emitter layer having a surface oxide layer is present on top of an NPN-type structure, the emitter layer comprising lateral and vertical surfaces, and wherein for removal of the oxide layer, an ion etching step is applied, wherein for the on etching step a plasma for providing ions is generated in a vacuum chamber by RF coupling and the generated ions are accelerated by an acceleration voltage between the plasma and a wafer comprising the semiconductor structure, and wherein the plasma generation and the ion acceleration are controlled independently from each other.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: October 7, 2014
    Assignee: Texas Instruments Deutschland GmbH
    Inventors: Thomas Scharnagl, Berthold Staufer
  • Patent number: 8846542
    Abstract: The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containers over a semiconductor substrate, with such containers having upwardly-extending openings with lateral widths of less than or equal to about 4000 angstroms; and the silicon nitride can be in the form of a layer extending between the containers. The selective etching can comprise exposure of at least some of the silicon nitride and the containers to Cl2 to remove the exposed silicon nitride, while not removing at least the majority of the metal nitride from the containers. In subsequent processing, the containers can be incorporated into capacitors.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: September 30, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kevin R. Shea, Thomas M. Graettinger
  • Publication number: 20140273496
    Abstract: Methods of removing metal hardmasks in the presence of ultra low-k dielectric films are described. In an example, a method of patterning a low-k dielectric film includes forming a pattern in a metal nitride hardmask layer formed above a low-k dielectric film formed above a substrate. The method also includes etching, using the metal nitride hardmask layer as a mask, the pattern at least partially into the low-k dielectric film, the etching involving using a plasma etch based on SiFx. The etching also involves forming an SiOx passivation layer at least on sidewalls of the low-k dielectric film formed during the etching. The method also includes removing the metal nitride hardmask layer by a dry etch process, where the SiOx passivation layer protects the low-k dielectric film during the removing.
    Type: Application
    Filed: May 8, 2013
    Publication date: September 18, 2014
    Inventors: Chia-Ling Kao, Kwang-soo Kim, Sean S. Kang, Srinivas D. Nemani
  • Patent number: 8808564
    Abstract: Embodiments described herein generally relate to methods for manufacturing flash memory devices. In one embodiment, a method for removing native oxides from a substrate is provided. The method includes transferring a substrate having an oxide layer disposed thereon into a first processing chamber, exposing the substrate to a plasma generated from a cleaning gas mixture, wherein the cleaning gas mixture comprises a hydrogen-containing gas and a fluorine-containing gas, heating the substrate to a temperature sufficient to remove the oxide layer from the substrate, transferring the substrate from the first processing chamber to a second processing chamber without breaking vacuum, and flowing a plasma containing substantially nitrogen-containing radicals into the second processing chamber to expose the substrate to nitrogen containing radicals.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: August 19, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Matthew S. Rogers, Christopher S. Olsen
  • Patent number: 8748322
    Abstract: A method of etching silicon oxide from a trench is described which allows more homogeneous etch rates across a varying pattern on a patterned substrate. The method also provides a more rectilinear profile following the etch process. Methods include a sequential exposure of gapfill silicon oxide. The gapfill silicon oxide is exposed to a local plasma treatment prior to a remote-plasma dry etch which may produce salt by-product on the surface. The local plasma treatment has been found to condition the gapfill silicon oxide such that the etch process proceeds at a more even rate within each trench and across multiple trenches. The salt by-product may be removed by raising the temperature in a subsequent sublimation step.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: June 10, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Nancy Fung, David T. Or, Qingjun Zhou, Lina Zhu, Jeremiah T. Pender, Srinivas D. Nemani, Sean S. Kang, Sergey G. Belostotskiy, Chinh Dinh
  • Patent number: 8747684
    Abstract: A method and apparatus for plasma etching a workpiece, such as a semiconductor wafer, including a thin film stack having a top film disposed over a bottom film with an intervening middle film there between. Etch selectivity between the top and bottom films may be as low as between 1:1 and 2:1 and a first carbon-lean gas chemistry is used to etch through the top film, a second carbon-lean gas chemistry is used to etch through the middle film, and the bottom film is etched through by alternating between depositing a polymer passivation on the top film using a carbon-rich gas chemistry and an etching of the bottom film with a third carbon-lean gas chemistry, which may be the same as the first carbon-lean gas chemistry.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: June 10, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Sunil Srinivasan, Jinhan Choi, Anisul H. Khan
  • Patent number: 8734660
    Abstract: An imaging structure such as a mask or reticle may be fabricated using a patterning layer on an imaging layer. The patterning layer may have substantially different etch properties than the imaging layer. A first etch process may be selective of the patterning layer with respect to a resist layer. A second etch process may be selective of the imaging layer with respect to the patterning layer.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: May 27, 2014
    Assignee: Intel Corporation
    Inventors: Jian Ma, Phil Freiberger, Karmen Yung, Frederick Chen, Chaoyang Li, Steve Mak
  • Patent number: 8728945
    Abstract: A method of uniformly shrinking hole and space geometries by forming sidewalls of an ALD film deposited at low temperature on a photolithographic pattern.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: May 20, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Steven Alan Lytle
  • Patent number: 8691704
    Abstract: The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containers over a semiconductor substrate, with such containers having upwardly-extending openings with lateral widths of less than or equal to about 4000 angstroms; and the silicon nitride can be in the form of a layer extending between the containers. The selective etching can comprise exposure of at least some of the silicon nitride and the containers to Cl2 to remove the exposed silicon nitride, while not removing at least the majority of the metal nitride from the containers. In subsequent processing, the containers can be incorporated into capacitors.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: April 8, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kevin R. Shea, Thomas M. Graettinger
  • Patent number: 8642479
    Abstract: A method for forming an opening in a semiconductor device is provided, including: providing a semiconductor substrate with a silicon oxide layer, a polysilicon layer and a silicon nitride layer sequentially formed thereover; patterning the silicon nitride layer, forming a first opening in the silicon nitride layer, wherein the first opening exposes a top surface of the polysilicon layer; performing a first etching process, using gasous etchants including hydrogen bromide (HBr), oxygen (O2), and fluorocarbons (CxFy), forming a second opening in the polysilicon layer, wherein a sidewall of the polysilicon layer adjacent to the second opening is substantially perpendicular to a top surface of the silicon oxide layer, wherein x is between 1-5 and y is between 2-8; removing the silicon nitride layer; and performing a second etching process, forming a third opening in the silicon oxide layer exposed by the second opening.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: February 4, 2014
    Assignee: Nanya Technology Corporation
    Inventors: Chih-Ching Lin, Yi-Nan Chen, Hsien-Wen Liu
  • Patent number: 8642476
    Abstract: There is provided a method for manufacturing a SiC semiconductor device achieving improved performance. The method for manufacturing the SiC semiconductor device includes the following steps. That is, a SiC semiconductor is prepared which has a first surface having at least a portion into which impurities are implanted. By cleaning the first surface of the SiC semiconductor, a second surface is formed. On the second surface, a Si-containing film is formed. By oxidizing the Si-containing film, an oxide film constituting the SiC semiconductor device is formed.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: February 4, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Satomi Itoh, Hiromu Shiomi, Yasuo Namikawa, Keiji Wada, Mitsuru Shimazu, Toru Hiyoshi
  • Patent number: 8592322
    Abstract: A method of fabricating openings is disclosed. First, a semiconductor substrate having a salicide region thereon is provided. An etch stop layer and at least a dielectric layer are disposed on the semiconductor substrate from bottom to top. Second, the dielectric layer and the etching stop layer are patterned to form a plurality of openings in the dielectric layer and in the etching stop layer so that the openings expose the salicide region. Then, a dielectric thin film covering the dielectric layer, sidewalls of the openings and the salicide region is formed. Later, the dielectric thin film disposed on the dielectric layer and on the salicide region is removed.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: November 26, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Feng-Yi Chang, Pei-Yu Chou, Jiunn-Hsiung Liao, Chih-Wen Feng, Ying-Chih Lin, Po-Chao Tsao
  • Patent number: 8580694
    Abstract: A method of patterning a hard mask layer for defining a deep trench is described. A substrate formed with an isolation structure therein is provided. A hard mask layer is formed over the substrate provided. A patterned photoresist layer is formed over the hard mask layer, having therein a deep-trench opening pattern over the isolation structure. An etching gas not containing hydrogen is used to etch the hard mask layer with the patterned photoresist layer as a mask and thereby transfer the deep-trench opening pattern to the hard mask layer.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: November 12, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Sheng-Jie Hsu, Shin-He Siao
  • Patent number: 8535551
    Abstract: A plasma etching method includes plasma-etching a silicon oxide layer through a mask using a process gas, the process gas containing oxygen gas and a fluorohydrocarbon shown by the formula (1), CxHyFz, wherein x is an integer from 4 to 6, y is an integer from 1 to 4, and z is a positive integer, provided that (y+z) is 2x or less. A contact hole having a very small diameter and a high aspect ratio can be formed in a substantially vertical shape without necking by plasma-etching the silicon oxide layer using a single process gas.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: September 17, 2013
    Assignee: Zeon Corporation
    Inventors: Takefumi Suzuki, Tatsuya Sugimoto, Masahiro Nakamura
  • Patent number: 8501629
    Abstract: A method of etching silicon-containing material is described and includes a SiConi™ etch having a greater or lesser flow ratio of hydrogen compared to fluorine than that found in the prior art. Modifying the flow rate ratios in this way has been found to reduce roughness of the post-etch surface and to reduce the difference in etch-rate between densely and sparsely patterned areas. Alternative means of reducing post-etch surface roughness include pulsing the flows of the precursors and/or the plasma power, maintaining a relatively high substrate temperature and performing the SiConi™ in multiple steps. Each of these approaches, either alone or in combination, serve to reduce the roughness of the etched surface by limiting solid residue grain size.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: August 6, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Jing Tang, Nitin Ingle, Dongqing Yang
  • Patent number: 8497211
    Abstract: A method of depositing a phosphosilicate glass (PSG) film on a substrate disposed in a substrate processing chamber includes depositing a first portion of the PSG film over the substrate using a high-density plasma process. Thereafter, a portion of the first portion of the PSG film may be etched back. The etch back process may include flowing a halogen precursor to the substrate processing chamber, forming a high-density plasma from the halogen precursor, and terminating flowing the halogen precursor after the etch back. The method also includes flowing a halogen scavenger to the substrate processing chamber to react with residual halogen in the substrate processing chamber, and exposing the first portion of the PSG film to a phosphorus-containing gas to provide a substantially uniform phosphorus concentration throughout the first portion of the PSG film.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: July 30, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Young S. Lee, Anchuan Wang, Lan Chia Chan, Shankar Venkataraman
  • Patent number: 8440568
    Abstract: The etching method includes etching the silicon oxide film by supplying a halogen-containing gas and a basic gas to the substrate so that the silicon oxide film is chemically reacted with the halogen-containing gas and the basic gas to generate a condensation layer; etching silicon by supplying a silicon etching gas, which includes at least one selected from the group consisting of an F2 gas, an XeF2 gas, and a ClF3 gas, to the substrate; and after the etching of the silicon oxide film and the etching of the silicon, heating and removing the condensation layer from the substrate.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: May 14, 2013
    Assignee: Tokyo Electron Limited
    Inventor: Hajime Ugajin
  • Patent number: 8420547
    Abstract: A plasma processing method performed in a plasma processing apparatus including a processing chamber accommodating a substrate in which a plasma is generated; a mounting table mounting the substrate, which is provided in the processing chamber and to which a plasma attraction high frequency voltage is applied; and a facing electrode provided to face the mounting table in the processing chamber, to which a negative DC voltage is applied, the method including: applying a plasma attraction high frequency voltage to the mounting table for a predetermined period of time; and stopping the application of the plasma attraction high frequency voltage to the mounting table. In the plasma processing method, the application of the plasma attraction high frequency voltage and stopping thereof are alternately repeated.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: April 16, 2013
    Assignee: Tokyo Electron Limited
    Inventor: Yoshinobu Ooya
  • Patent number: 8318605
    Abstract: Formation of BPSG surface defects upon exposure to atmosphere is prevented by a plasma treatment method for converting boron and/or phosphorus materials separated from silicon near the surface of the doped glass layer to gas phase compounds. The treatment plasma is generated from a treatment process gas containing one of (a) a fluorine compound or (b) a hydrogen compound.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: November 27, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Chien-Teh Kao, Haichun Yang, Xinliang Lu, Mei Chang
  • Patent number: 8314033
    Abstract: A significantly improved low-k dielectric patterning method is described herein using plasma comprising an oxygen radical source and a silicon source to remove the photo-resist layer.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: November 20, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Yifeng Zhou, Srinivas D. Nemani, Khoi Doan, Jeremiah T. P. Pender
  • Patent number: 8299564
    Abstract: Formation of transistors, such as, e.g., PMOS transistors, with diffusion regions having different depths for equalization of performance among transistors of an integrated circuit is described. Shallow-trench isolation structures are formed in a substrate formed at least in part of silicon for providing the transistors with at least substantially equivalent channel widths and lengths. A series of masks and etches is performed to form first recesses and second recesses defined in the silicon having different depths and respectively associated with first and second transistors. The second recesses are deeper than the first recesses. A silicon germanium film is formed in the first recesses and the second recesses. The silicon germanium film in the second recesses is thicker than the silicon germanium film in the first recesses, in order to increase performance of the second transistor so it is closer to the performance of the first transistor.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: October 30, 2012
    Assignee: Xilinx, Inc.
    Inventors: Yun Wu, Bei Zhu, Zhiyuan Wu, Michael J. Hart
  • Patent number: 8282845
    Abstract: The present invention relates to a method for etching a feature in an etch layer that has a thickness of more than 2 micrometers from an initial contact face for the etchant to an opposite bottom face of the etch layer, at a lateral feature position in the etch layer and with a critical lateral extension at the bottom face. The method includes fabricating, at the lateral feature position on the substrate layer, a mask feature from a mask-layer material, the mask feature having the critical lateral extension. The etch layer is deposited to a thickness of more than 2 micrometers, on the mask feature and on the substrate layer, from an etch-layer material, which is selectively etchable relative to the mask-layer material. Then, the feature is etched in the etch layer at the first lateral position with a lateral extension larger than the critical lateral extension, using an etchant that selectively removes the etch layer-material relative to the mask-layer material.
    Type: Grant
    Filed: July 2, 2009
    Date of Patent: October 9, 2012
    Assignee: EPCOS AG
    Inventors: Dirk Marteen Knotter, Arnoldus Den Dekker, Ronald Koster, Robertus T. F. Van Schaijk
  • Patent number: 8236702
    Abstract: A semiconductor substrate having an etch stop layer and at least a dielectric layer disposed from bottom to top is provided. The dielectric layer and the etching stop layer is then patterned to form a plurality of openings exposing the semiconductor substrate. A dielectric thin film is subsequently formed to cover the dielectric layer, the sidewalls of the openings, and the semiconductor substrate. The dielectric thin film disposed on the dielectric layer and the semiconductor substrate is then removed while the dielectric thin film disposed on the sidewalls remains.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: August 7, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Feng-Yi Chang, Pei-Yu Chou, Jiunn-Hsiung Liao, Chih-Wen Feng, Ying-Chih Lin, Po-Chao Tsao
  • Publication number: 20120178263
    Abstract: [Problem] To provide a substrate processing apparatus capable of preventing adherence of hydrogen fluoride to an inner surface the like of a chamber. [Means for Solving] An apparatus housing and processing a substrate W in a chamber includes a hydrogen fluoride gas supply path 61 for supplying a hydrogen fluoride gas into a chamber 40, wherein a part or whole of an inner surface of the chamber 40 is formed of Al or Al alloy which has not been subjected to surface oxidation treatment. The chamber 40 includes a lid 52 closing an upper opening of a chamber main body 51, and at least an inner surface of the lid 52 is formed of the Al or Al alloy which has not been subjected to alumite treatment.
    Type: Application
    Filed: March 19, 2012
    Publication date: July 12, 2012
    Applicant: Tokyo Electron Limited
    Inventors: Shigeki TOZAWA, Yusuke Muraki, Tadashi Ilno, Daisuke Hayashi
  • Patent number: 8177990
    Abstract: Disclosed is a method of etching a substrate having a layered structure in which a photoresist mask with a pattern, a coating film made of silicon oxide, and an organic film are laminated in that order from the top. Before etching the coating film of silicon oxide, a deposit is deposited on the photoresist mask by using plasma generated from a hydrocarbon gas such as CH4 gas so as to narrow the size of openings in the pattern of the photoresist mask. The pattern of the photoresist mask is well transferred to the organic film through the coating film, and a pattern with openings having a high aspect ratio can be formed in the organic film and toppling of the pattern in the organic film can be prevented. The organic film with the transferred pattern is used as an etch mask for etching the underlying layer.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: May 15, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Ryou Mochizuki, Jun Yashiro
  • Patent number: 8153019
    Abstract: Methods for preventing isotropic removal of materials at corners formed by seams, keyholes, and other anomalies in films or other structures include use of etch blockers to cover or coat such corners. This covering or coating prevents exposure of the corners to isotropic etch solutions and cleaning solutions and, thus, prevents higher material removal rates at the corners than at smoother areas of the structure or film from which material is removed. Solutions, including wet etchants and cleaning solutions, that include at least one type of etch blocker are also disclosed, as are systems for preventing higher rates of material removal at corners formed by seams, crevices, or recesses in a film or other structure. Semiconductor device structures in which etch blockers are located so as to prevent isotropic etchants from removing material from corners of seams, crevices, or recesses in a surface of a film or other structure at undesirably high rates are also disclosed.
    Type: Grant
    Filed: August 6, 2007
    Date of Patent: April 10, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Nishant Sinha, J. Neil Greeley
  • Patent number: 8129242
    Abstract: A method of manufacturing a flash memory device having an enhanced gate coupling ratio includes steps of forming a first semiconductor layer on a substrate and forming a semiconductor spacer layer on top of the first semiconductor layer. The semiconductor spacer layer includes a plurality of recesses. The method provides a semiconductor spacer structure which functions to increase the contact area between a floating gate and a control gate of the flash memory device.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: March 6, 2012
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Tian-Shuan Luo, Chun-Pei Wu
  • Patent number: 8114781
    Abstract: A substrate processing method capable of selectively removing a nitride film. Oxygen plasma containing plasmarized oxygen gas is made to be in contact with a silicon nitride film, which is made of SiN, of a wafer to thereby cause the silicon nitride film to be changed to a silicon monoxide film. The silicon monoxide film is selectively etched by hydrofluoric acid generated from HF gas supplied toward the silicon monoxide film.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: February 14, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Eiichi Nishimura, Koichi Yatsuda
  • Patent number: 8076248
    Abstract: The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containers over a semiconductor substrate, with such containers having upwardly-extending openings with lateral widths of less than or equal to about 4000 angstroms; and the silicon nitride can be in the form of a layer extending between the containers. The selective etching can comprise exposure of at least some of the silicon nitride and the containers to Cl2 to remove the exposed silicon nitride, while not removing at least the majority of the metal nitride from the containers. In subsequent processing, the containers can be incorporated into capacitors.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: December 13, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Kevin R. Shea, Thomas M. Graettinger
  • Patent number: 8062982
    Abstract: A high yield plasma etch process for an interlayer dielectric layer of a semiconductor device is provided, according to an embodiment of which a dielectric layer is etched with a nitrogen-containing plasma. In this way, the formation of polymers on a backside bevel of a substrate is avoided or substantially reduced. Remaining polymer at the backside bevel can be removed in situ by post-etch treatment. Further, a plasma etching device is provided comprising a chamber, a substrate receiving space for receiving a substrate, a plasma generator for generating a plasma in the chamber and a temperature conditioner for conditioning a temperature at an outer circumferential region of the substrate receiving space and thereby minimizing temperature gradients at a bevel of the wafer.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: November 22, 2011
    Assignee: Advanced Micro Devices, Inc
    Inventors: Daniel Fischer, Matthias Schaller, Matthias Lehr, Kornelia Dittmar
  • Patent number: 8048689
    Abstract: Various semiconductor devices and methods of testing such devices are disclosed. In one aspect, a method of manufacturing is provided that includes forming a bore from a backside of a semiconductor chip through a buried insulating layer and to a semiconductor device layer of the semiconductor chip. A conductor structure is formed in the bore to establish an electrically conductive pathway between the semiconductor device layer and the conductor structure. The conductor structure may provide a diagnostic pathway.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: November 1, 2011
    Assignee: Globalfoundries Inc.
    Inventors: Liang Wang, Michael R. Bruce
  • Patent number: 8012877
    Abstract: Exemplary embodiments provide a method for fabricating an integrated circuit (IC) device with reduced streak defects. In one embodiment, the IC device structure can be formed having a first pad oxide-based layer on a front side of a semiconductor substrate and having an oxide-nitride-based structure on a backside of the semiconductor substrate. The IC device structure can be etched to remove a nitride-related material from the backside oxide-nitride-based structure, and further to remove the first pad oxide-based layer from the front side of the semiconductor substrate. On the removed front side of the semiconductor substrate a second pad oxide-based layer can be formed, e.g., for forming an isolation structure for device component or circuitry isolation.
    Type: Grant
    Filed: November 19, 2008
    Date of Patent: September 6, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Scott Cuong Nguyen
  • Patent number: 8008209
    Abstract: A technique is described whereby temperature gradients are created within a semiconductor wafer. Temperature sensitive etching and/or deposition processes are then employed. These temperature sensitive processes proceed at different rates in regions with different temperatures. To reduce pinch off in etching processes, a temperature sensitive etch process is selected and a temperature gradient is created between the surface and subsurface of a wafer such that the etching process proceeds more slowly at the surface than deeper in the wafer. This reduces “crusting” of solid reaction products at trench openings, thereby eliminating pinch off in many cases. Similar temperature-sensitive deposition processes can be employed to produce void-free high aspect ratio conductors and trench fills.
    Type: Grant
    Filed: October 24, 2007
    Date of Patent: August 30, 2011
    Assignee: International Business Machines Corporation
    Inventors: Michael R. Sievers, Kaushik A. Kumar, Andres F. Munoz, Richard Wise
  • Patent number: 7988873
    Abstract: A method of forming a mask pattern for fabricating a semiconductor device. A first region and a second region, having an intersecting third region, are defined in the semiconductor substrate. An inorganic mask layer is etched in the first region to a predetermined thickness, and etched in the second region to another predetermined thickness. While the inorganic mask layer is etched in the first and second region, an organic mask layer is exposed in the third region. The organic mask layer exposed in the third region is removed to form a mask pattern. Consequently, double exposure is performed using the organic mask layer and the inorganic mask layer, so that a fine feature size that closely follows a desired layout can be formed, damage to the organic mask layer by ashing is prevented, and adhesiveness between the organic mask layer and the inorganic mask layer can be improved.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: August 2, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyong-Soo Kim, Sang-Hyeop Lee
  • Patent number: 7977246
    Abstract: A thermal anneal process for preventing formation of certain BPSG surface defects following an etch or silicon clean step using a fluorine and hydrogen chemistry. The thermal anneal process is carried out while protecting the wafer from moisture, by heating the wafer to a sufficiently high temperature for a sufficient duration of time to thermally diffuse boron and/or phosphorus materials separated from silicon near the surface of the doped glass layer into the bulk of the layer. The thermal anneal process is completed by cooling the wafer to a sufficiently low temperature to fix the distribution of the boron and/or phosphorus materials in bulk of the doped glass layer.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: July 12, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Haichun Yang, Chien-Teh Kao, Xinliang Lu, Mei Chang
  • Patent number: 7972967
    Abstract: A method of forming patterns of a semiconductor device comprising forming an auxiliary layer over an underlying layer comprising a cell region and a select transistor region, forming a first passivation layer over the auxiliary layer, wherein the first passivation layer blocks the auxiliary layer of the select transistor region and opens the auxiliary layer of the cell region, and forming a first photoresist pattern having a narrower width than the first passivation layer over (a) the first passivation layer and (b) second photoresist patterns, each having a narrower width than the first photoresist pattern, over an opening region of the auxiliary layer, wherein a gap between the first and second photoresist patterns is identical in width with a gap defined between the second photoresist patterns.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: July 5, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Chan Sun Hyun
  • Patent number: 7943524
    Abstract: Silicon oxide film having, as a sublayer, a silicon nitride film layer serving as a protective film layer for 5 gate formed on silicon substrate is etched by introducing a processing gas including a gaseous mixture containing at least C4F6, Ar, O2 and N2 into an airtight processing chamber and carrying out a plasma treatment in a self-alignment contact process, thereby forming contact hole. For the 10 processing gas, e.g., the ratio of N2 gas flow rate to C4F6 gas flow rate ranges from 25/8 to 85/8, the ratio of O2 and N2 gas flow rate to C4F6 gas flow rate ranges from 15/4 to 45/4 and the ratio of N2 gas flow rate to O2 gas flow rate ranges from 5 to 17. Accordingly, stable contact holes of 15 high aspect ratio exhibiting desirable control characteristics is formed while minimizing etching the silicon nitride film, a protective film layer for gate.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: May 17, 2011
    Assignee: Tokyo Electrons Limited
    Inventors: Noriyuki Kobayashi, Kenji Adachi
  • Patent number: 7911034
    Abstract: A method for patterning CNTs on a wafer wherein a CNT layer is provided on a substrate, a hard mask film is deposited on the CNT layer, a BARC layer (optional) is coated on the hard mask film, and a resist is patterned on the BARC layer (or directly on the hard mask film if the BARC layer is not included). Then, the resist pattern is effectively transferred to the hard mask film by etching the BARC layer (if provided) and etching partly into, but not entirely through, the hard mask film (i.e., etching is stopped before reaching the CNT layer). Then, the resist and the BARC layer (if provided) is stripped, and the hard mask pattern is effectively transferred to the CNTs by etching away (preferably by using C1, F plasma) the portions of the hard mask which have been already partially etched away.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: March 22, 2011
    Assignee: Nantero, Inc.
    Inventors: Shiqun Gu, Peter G. McGrath, James Elmer, Richard J. Carter, Thomas Rueckes
  • Patent number: 7902080
    Abstract: Methods of filling a gap on a substrate with silicon oxide are described. The methods may include the steps of introducing an organo-silicon precursor and an oxygen precursor to a deposition chamber, reacting the precursors to form a first silicon oxide layer in the gap on the substrate, and etching the first silicon oxide layer to reduce the carbon content in the layer. The methods may also include forming a second silicon oxide layer on the first layer, and etching the second layer to reduce the carbon content in the second layer. The silicon oxide layers are annealed after the gap is filled.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: March 8, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Xiaolin Chen, Srinivas D. Nemani, Shankar Venkataraman
  • Patent number: 7846843
    Abstract: A process for manufacturing a semiconductor device using a spacer as an etch mask for forming a fine pattern is described. The process includes forming a hard mask layer over a target layer that is desired to be etched. A sacrificial layer pattern is subsequently formed over the hard mask layer. Spacers are formed on the sidewalls of the sacrificial layer pattern. The protective layer is formed on the hard mask layer portions between the sacrificial patterns formed with the spacer. The sacrificial layer pattern and the protective layer are then later removed, respectively. The hard mask layer is etched using the spacer as an etching mask. After etching, the spacer is removed. Finally, the target layer is etched using the etched hard mask as an etching mask.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: December 7, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Chai O Chung, Jong Min Lee, Chan Bae Kim, Hyeon Ju An, Hyo Seok Lee, Sung Kyu Min
  • Patent number: 7838431
    Abstract: Methods and apparatus for processing a substrate are provided herein. In some embodiments, a method of processing a substrate may include providing a substrate having at least one of a defect or a contaminant disposed on or near a surface of the substrate; and selectively annealing a portion of the substrate with a laser beam in the presence of a process gas comprising hydrogen. The laser beam may be moved over the substrate or continuously, or in a stepwise fashion. The laser beam may be applied in a continuous wave or pulsed mode. The process gas may further comprise an inert gas, such as, at least one of helium, argon, or nitrogen. A layer of material may be subsequently deposited atop the annealed substrate.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: November 23, 2010
    Assignee: Applied Materials, Inc.
    Inventor: Errol Sanchez
  • Patent number: 7825034
    Abstract: A substrate having an etch stop layer and at least a dielectric layer disposed from bottom to top is provided. The dielectric layer is then patterned to form a plurality of openings exposing the etch stop layer. A dielectric thin film is subsequently formed to cover the dielectric layer, the sidewalls of the openings, and the etch stop layer. The dielectric thin film disposed on the dielectric layer and the etch stop layer is then removed.
    Type: Grant
    Filed: October 6, 2005
    Date of Patent: November 2, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Po-Chao Tsao, Chang-Chi Huang, Ming-Tsung Chen
  • Patent number: 7803673
    Abstract: A method of manufacturing a thin film transistor (“TFT”) substrate includes forming a gate insulating film and an active layer on a substrate, forming a data metal layer including a first, second, and third metal layers on the active layer, forming a first photoresist pattern on the data metal layer, dry-etching the third metal layer by using the first photoresist pattern, simultaneously dry-etching the second and first metal layers by using the first photoresist pattern, dry-etching the active layer by using the first photoresist pattern, etching the first photoresist pattern to form a second photoresist pattern by which the channel region is removed and forming a source electrode and a drain electrode by dry-etching the channel region of the data metal layer by using the second photoresist pattern.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: September 28, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Duck-Jung Lee, Dae-Ho Song, Kyung-Seop Kim, Yong-Eui Lee