Projection Of Etchant Against A Moving Substrate Or Controlling The Angle Or Pattern Of Projected Etchant Patents (Class 438/748)
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Patent number: 8007594Abstract: A method for manufacturing a semiconductor device includes the step of conducting a cleaning process for a wafer formed with copper wiring lines to remove contaminations produced on a back surface of the wafer. The cleaning process is conducted by injecting onto the back surface of the wafer an etchant for removing contaminations and simultaneously injecting onto a front surface of the wafer a reductant containing hydrogen.Type: GrantFiled: July 12, 2010Date of Patent: August 30, 2011Assignee: Hynix Semiconductor Inc.Inventors: Young Bang Lee, Kwang Kee Chae, Ok Min Moon
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Patent number: 7998876Abstract: A method of producing a semiconductor element includes the steps of forming a wiring portion layer on a substrate; forming an interlayer insulation layer over the substrate and the wiring portion layer, in which a third insulation film, a second insulation film, and a first insulation film are laminated in this order from the substrate; forming a mask pattern on the first insulation film; removing a contact hole forming area of the first insulation film through a wet etching process; removing a contact hole forming area of the second insulation film through an etching process; removing a contact hole forming area of the third insulation film through an etching process; and a contact hole forming step of forming a contact hole in the interlayer insulation layer so that a surface of the wiring portion layer is exposed.Type: GrantFiled: March 11, 2010Date of Patent: August 16, 2011Assignee: Oki Semiconductor Co., Ltd.Inventor: Toshiyuki Orita
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Patent number: 7972969Abstract: A method is provided for controlling substrate thickness. At least one etchant is dispensed from at least one dispenser to a plurality of different locations on a surface of a spinning substrate to perform etching. A thickness of the spinning substrate is monitored at the plurality of locations, so that the thickness of the substrate is monitored at each individual location while dispensing the etchant at that location. A respective amount of etching performed at each individual location is controlled, based on the respective monitored thickness at that location.Type: GrantFiled: March 6, 2008Date of Patent: July 5, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ku-Feng Yang, Wen-Chih Chiou, Weng-Jin Wu, Kewei Zuo
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Publication number: 20110151675Abstract: A spin chuck in an apparatus for single wafer wet processing has structures at its periphery that, in combination with a supported wafer, form a series of annular nozzles that direct flowing gas from a chuck-facing surface of the wafer, around the edge of the wafer, and exhaust the gas away from the non-chuck-facing surface of the wafer, thereby preventing treatment fluid applied to the non-chuck-facing surface from contacting the edge region of the wafer. Retaining pins with enlarged heads engage the wafer edge and prevent it from being displaced upwardly when a high flow rate of gas is utilized.Type: ApplicationFiled: December 18, 2009Publication date: June 23, 2011Applicant: LAM RESEARCH AGInventors: Dieter FRANK, Michael PUGGL
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Patent number: 7887636Abstract: A substrate dryer includes, among other things, means for generating isopropyl alcohol bubbles, and a vibrator to atomize stored isopropyl alcohol. A heater may be provided to heat pumped isopropyl alcohol, as wells as a spray nozzle to spray the heated IPA to the vibrator. It is possible to increase the concentration of the isopropyl alcohol supplied for the purpose of drying the substrate. Improved substrate drying is achieved.Type: GrantFiled: January 11, 2006Date of Patent: February 15, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Hyeon Nam, Seung-Kun Lee
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Patent number: 7884028Abstract: A method of removing material layer is disclosed. First, a semiconductor substrate is fixed on a rotating platform, where a remnant material layer is included on the surface of the semiconductor substrate. Afterward, an etching process is carried out. In the etching process, the rotating platform is rotated, and an etching solution is sprayed from a center region and a side region of the rotating platform toward the semiconductor substrate until the material layer is removed. Since the semiconductor substrate is etched by the etching solution sprayed from both the center region and the side region of the rotating platform, the etching uniformity of the semiconductor substrate is improved.Type: GrantFiled: April 10, 2007Date of Patent: February 8, 2011Assignee: United Microelectronics Corp.Inventors: Yi-Wei Chen, Chun-Chieh Chang, Tzung-Yu Hung, Yu-Lan Chang, Chao-Ching Hsieh
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Patent number: 7833912Abstract: According to an aspect of the present invention, there is provided a semiconductor device including a semiconductor substrate which includes a number of chip areas, a processed film which is formed on the semiconductor substrate, and a ring-shaped pattern which is formed on the processed film and along a peripheral portion of the semiconductor substrate.Type: GrantFiled: April 27, 2007Date of Patent: November 16, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Takayo Kobayashi, Tomohiro Oki
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Patent number: 7776709Abstract: A method (and apparatus) of replicating a pattern on a structure, includes using imprint lithography to replicate a pattern formed on a first structure onto a portion of a second structure.Type: GrantFiled: October 26, 2007Date of Patent: August 17, 2010Assignee: International Business Machines CorporationInventors: Matthew E. Colburn, Yves C. Martin, Theodore G. van Kessel, Hematha K. Wickramasinghe
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Patent number: 7759252Abstract: The present invention is related to a method of two-step backside-etching. First, a substrate with a plurality of hard masks is provided. Next, the back and the edge of the substrate are backside-etched to remove parts of the hard masks on the back and the edge of the substrate. Then, the hard masks and the substrate are patterned in sequence to form a plurality of trenches in the substrate. Finally, before performing a wet bath step, the edge of the substrate is backside-etched to remove needle structures on the edge of the substrate.Type: GrantFiled: July 10, 2007Date of Patent: July 20, 2010Assignee: Promos Technologies Inc.Inventor: Yeng-Peng Wang
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Patent number: 7745237Abstract: Method of forming a pattern by a nanoimprint technique starts with preparing a mold with nanostructures on its surface. The mold is pressed against a substrate or plate coated with a resin film. The positions of alignment marks formed on the rear surface of the plate coated with the resin film are detected. Thus, a relative alignment between the mold and the plate coated with the resin film is performed.Type: GrantFiled: January 24, 2007Date of Patent: June 29, 2010Assignee: Hitachi, Ltd.Inventors: Souichi Katagiri, Yasunari Sohda, Masahiko Ogino
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Publication number: 20100151597Abstract: Disclosed is a method for smoothing the surface of at least one side of a wafer which is obtained by slicing a semiconductor ingot. In this method, a fluid is applied according to projections of the wafer surface, thereby reducing the projections. Alternatively, a fluid is applied over the wafer surface, thereby smoothing the entire surface of the wafer while reducing the projections in the wafer surface.Type: ApplicationFiled: January 17, 2007Publication date: June 17, 2010Applicant: SUMCO CORPORATIONInventors: Takeo Katoh, Tomohiro Hashii, Katsuhiko Murayama, Sakae Koyata, Kazushige Takaishi
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Publication number: 20100130021Abstract: A method is disclosed for processing the cleaved surface of a silicon-on-insulator structure. The silicon-on-insulator structures comprises a handle wafer, a silicon layer, and a dielectric layer between the handle wafer and the silicon layer. The silicon layer has a cleaved surface defining an outer surface of the structure. The methods disclosed include an etching process to reduce the time and cost required to process the silicon-on-insulator structure to remove the surface damage and defects formed when a portion of the donor wafer is separated along a cleave plane from the silicon-on-insulator structure. The method includes, annealing the structure, etching the cleaved surface, and performing a non-contact smoothing process on the cleaved surface.Type: ApplicationFiled: November 23, 2009Publication date: May 27, 2010Applicant: MEMC ELECTRONIC MATERIALS, INC.Inventors: Michael J. Ries, Robert W. Standley, Jeffrey L. Libbert, Andrew M. Jones, Gregory M. Wilson
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Publication number: 20100055924Abstract: Chemical etching methods and associated modules for performing the removal of metal from the edge bevel region of a semiconductor wafer are described. The methods and systems provide the thin layer of pre-rinsing liquid before applying etchant at the edge bevel region of the wafer. The etchant is less diluted and diffuses faster through a thinned layer of rinsing liquid. An edge bevel removal embodiment involving that is particularly effective at reducing process time, narrowing the metal taper and allowing for subsequent chemical mechanical polishing, is disclosed.Type: ApplicationFiled: August 27, 2008Publication date: March 4, 2010Inventors: Kousik Ganesan, Shanthinath Ghongadi, Tariq Majid, Aaron Labrie, Steven T. Mayer
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Publication number: 20100029088Abstract: An apparatus for wet etching metal from a semiconductor wafer comprises a wafer holder for rotating a wafer and a plurality of nozzles for applying separate flow patterns of etching liquid to the surface of the wafer. The flow patterns impact the wafer in distinct band-like impact zones. The flow pattern of etching liquid from at least one nozzle is modulated during a total etching time control the cumulative etching rate in one local etch region relative to the cumulative etching rate in one or more other local etch regions. Some embodiments include a lower etch chamber and an upper rinse chamber separated by a horizontal splash shield. Some embodiments include a retractable vertical splash shield used to prevent splashing of etching liquid onto the inside walls of a treatment container. An etch-liquid delivery system includes a plurality of nozzle flow paths having corresponding nozzle flow resistances, and a plurality of drain flow paths having corresponding drain flow resistances.Type: ApplicationFiled: August 4, 2009Publication date: February 4, 2010Applicant: Novellus Systems, Inc.Inventors: Steven T. Mayer, David W. Porter
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Patent number: 7655496Abstract: A method of fabricating a semiconductor device includes patterning a layer of photoresist onto a surface of a wafer to define metal feature areas and residual metal areas. A layer of metal is deposited over the patterned layer of photoresist, the metal layer includes metal feature portions in the metal feature areas, residual metal areas in the residual metal areas, and residual metal flaps at the edges of the metal feature portions. The wafer is sprayed with high-pressure solvent at a pressure to dissolve the layer of photoresist and to physically remove the residual metal portions from the residual metal areas, leaving only at least a portion of the residual metal flaps. The wafer is sprayed with a stream of frozen gas particles to remove the residual metal flaps.Type: GrantFiled: July 31, 2007Date of Patent: February 2, 2010Assignee: FLIR Systems, Inc.Inventors: Patrick Franklin, John J. Naughton
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Publication number: 20090317981Abstract: Provided is a substrate treating method for selectively etching a surface of a substrate. In the substrate treating method, an etchant is supplied to a center portion of a rotating substrate through a first nozzle, and an etch prevention fluid is supplied through a second nozzle disposed at a predetermined position apart from the center portion of the substrate so as to dilute the etchant.Type: ApplicationFiled: June 24, 2009Publication date: December 24, 2009Inventors: Bok Kyu Lee, Jong Su Choi, Jun Kee Kang
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Publication number: 20090209110Abstract: A spin etching method for etching a back-side surface of a semiconductor wafer provided with a plurality of devices on the face side and subjected to back grinding, wherein the semiconductor wafer is held with its back-side surface down, and the back-side surface of the semiconductor wafer is supplied with an etching liquid from an etching liquid supply nozzle disposed on the lower side of the semiconductor wafer while the semiconductor wafer being rotated.Type: ApplicationFiled: January 30, 2009Publication date: August 20, 2009Applicant: DISCO CORPORATIONInventors: Ayumu Okano, Osamu Nagai
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Patent number: 7566652Abstract: A semiconductor device 300 includes a metal line 304 formed in a first dielectric layer 302. A capping layer 306 is formed the metal line 304. A second dielectric layer 308 is formed over the first dielectric layer 302 and the metal line 304. A first via 310 is formed in the second dielectric layer 308 and in contact with the metal line 304. A second via 312 is formed in the second dielectric layer 308 and in contact with the metal line 304, and is positioned a distance away from the first via 310. An electrically isolated via 326 is formed in the second dielectric layer 308 and in contact with the metal line 304 and in between the first via 310 and the second via 312. A third dielectric layer 314 is formed over the second dielectric layer 308. First and second trenches 316, 318 are formed in the third dielectric layer 314 and in contact with the first via 310 and the second via 312, respectively. An isolated trench 328 is formed in the third dielectric layer and in contact with the isolated via 326.Type: GrantFiled: July 24, 2006Date of Patent: July 28, 2009Assignee: Texas Instruments IncorporatedInventors: Ki-Don Lee, Young-Joon Park, Ennis Takashi Ogawa
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Publication number: 20090186488Abstract: A single wafer etching apparatus is an apparatus that supplies etching liquid to an upper face of a thin discoid wafer obtained by slicing a semiconductor ingot while rotating the wafer to etch the upper face and an edge face of the wafer. The apparatus includes: a first nozzle for supplying etching liquid to the upper face of the wafer; and a second nozzle for supplying etching liquid to the edge face of the wafer that is opposed to the edge face of the wafer. The second nozzle is fixed at a predetermined position in a range of ?10 mm to 20 mm from an end of an outer periphery of the wafer toward an inner side of the wafer in the radial direction. The apparatus includes a lower face blowing mechanism by which etching liquid flowing along the edge face of the wafer is blown off by gas jet toward an outer side in the radial direction of the wafer.Type: ApplicationFiled: February 29, 2008Publication date: July 23, 2009Inventors: KATOH Takeo, Hashii Tomohiro, Murayama Katsuhiko, Koyata Sakae, Takaishi Kazushige
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Publication number: 20090163026Abstract: A method of performing a single step/single solvent edge bead removal (EBR) process on a photolithography layer stack including a photoresist layer and a top coat layer using propylene glycol monomethyl ether acetate (PGMEA) or a mixture of PGMEA and gamma-butyrolactone (GBL) is disclosed. The single step/single solvent EBR process is compatible with organic and inorganic BARC layers.Type: ApplicationFiled: December 19, 2008Publication date: June 25, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Benjamen Michael Rathsack, Mark Howell Somervell
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Patent number: 7541293Abstract: According to the present invention, a process for changing the form of a processed film is performed to planarize it before the processed film which is formed on a wafer is processed in a manufacturing process of a semiconductor device. As the process for changing the form of the processed film, there may be exemplified a single wafer type wet etching process. The compatibility of the processed film with processing means is taken into consideration and, for instance, the wet etching process is applied to the processed film so as to eliminate parts incompatible with the processing means, so that a distribution in-plane of the processed film is previously improved.Type: GrantFiled: October 25, 2001Date of Patent: June 2, 2009Assignees: Sony Corporation, SEZ Japan, Inc.Inventors: Hayato Iwamoto, Kei Kinoshita
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Publication number: 20090075484Abstract: In a spin unit for rotating a substrate and a method of processing the substrate, the substrate is secured on a support and is rotated on the support. Processing materials including drying gases, etching solutions and cleaning solutions are selectively supplied onto a bottom surface of the rotating substrate. The same processing materials are also selectively supplied onto a top surface of the substrate. The top and bottom surfaces of the substrate are simultaneously processed by simultaneous supply of the processing materials through the first and second sub-injectors.Type: ApplicationFiled: September 16, 2008Publication date: March 19, 2009Inventors: Gil-Hun Song, Pyeng-Jae Park
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Patent number: 7476554Abstract: A substrate processing method of the present invention includes the steps of placing a substrate inside a vacuum container containing particles and processing the substrate inside the container while moving the substrate at a predetermined relative velocity of the substrate to the container. In this case, an allowable upper limit of the number or density of defects produced at the substrate due to the particles in the process for the substrate is determined, and the predetermined relative velocity is set at a value equal to or smaller than the relative velocity obtained when the number or density of defects reaches the upper limit.Type: GrantFiled: March 27, 2006Date of Patent: January 13, 2009Assignee: Panasonic CorporationInventors: Toshio Kaneko, Toru Nishiwaki
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Patent number: 7470622Abstract: A method of fabricating silicon micro-mirrors includes etching from opposite sides of a silicon wafer with a polished surface on at least one of the opposite sides, to form silicon bars each having a parallelogram-shaped cross-section and including a portion of the polished surface. At least one of the silicon bars is mounted on a mounting surface. The polished surface of the silicon bar may be used to reflect optical signals.Type: GrantFiled: June 17, 2005Date of Patent: December 30, 2008Assignee: Hymite A/SInventor: Lior Shiv
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Patent number: 7446051Abstract: Silicon (12) is etched through a mask (11) comprising a layer of organic resin material (such as novolac) through which openings (32) are formed in the areas to be etched. The layer of organic resin is first deposited over a free surface of the device to be etched. The openings (32) are then formed by depositing droplets of a caustic etchant such as sodium hydroxide (NaOH) or potassium hydroxide (KOH) with an inkjet printer. The etchant reacts with the resin to expose the silicon surface in areas to be etched. The etching of the silicon surface is performed by applying a dilute solution of hydrofluoric acid (HF) and potassium permanganate (KMnO4) to the exposed surface through the openings in the mask to etch the silicon to a desired depth (83).Type: GrantFiled: September 9, 2004Date of Patent: November 4, 2008Assignee: CSG Solar AGInventor: Trevor Lindsay Young
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Publication number: 20080254640Abstract: A method of removing material layer is disclosed. First, a semiconductor substrate is fixed on a rotating platform, where a remnant material layer is included on the surface of the semiconductor substrate. Afterward, an etching process is carried out. In the etching process, the rotating platform is rotated, and an etching solution is sprayed from a center region and a side region of the rotating platform toward the semiconductor substrate until the material layer is removed. Since the semiconductor substrate is etched by the etching solution sprayed from both the center region and the side region of the rotating platform, the etching uniformity of the semiconductor substrate is improved.Type: ApplicationFiled: April 10, 2007Publication date: October 16, 2008Inventors: Yi-Wei Chen, Chun-Chieh Chang, Tzung-Yu Hung, Yu-Lan Chang, Chao-Ching Hsieh
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Patent number: 7431861Abstract: An etchant for copper and copper alloys, includes an aqueous solution containing: 14 to 155 g/liter of cupric ion source in terms of a concentration of copper ions; 7 to 180 g/liter of hydrochloric acid; and 0.1 to 50 g/liter of azole, the azole including nitrogen atoms only as heteroatoms residing in a ring. A method for producing a wiring by etching of copper or copper alloys, includes the step of: etching a portion of a copper layer on an electrical insulative member that is not covered with an etching resist using the above-described etchant so as to form the wiring. Thereby, a fine and dense wiring pattern with reduced undercut can be formed.Type: GrantFiled: July 22, 2004Date of Patent: October 7, 2008Assignee: Mec Company Ltd.Inventors: Kenji Toda, Yukari Morinaga, Takahiro Teshima, Ai Kuroda
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Patent number: 7405139Abstract: A method of preventing the formation of cracks on the backside of a silicon (Si) semiconductor chip or wafer during the processing thereof. Also provided is a method for inhibiting the propagation of cracks, which have already formed in the backside of a silicon chip during the processing thereof and prior to the joining thereto of a substrate during the fabrication of an electronic package. The methods entail either treating the backside with a wet etch, or alternatively, applying a protective film layer thereon prior to forming an electronic package incorporating the chip or wafer.Type: GrantFiled: August 3, 2006Date of Patent: July 29, 2008Assignee: International Business Machines CorporationInventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Jerome B. Lasky, Christopher D. Muzzy, Wolfgang Sauter
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Patent number: 7396483Abstract: The invention concerns a method of wet chemical etching of a wafer comprising at least one surface layer of silicon-germanium (SiGe) for etching by dispensing an etching solution deposited on a rotating wafer, the method being characterized in that it comprises a first etching step in which said etching solution is dispensed from a fixed position located at a predetermined distance from the center of the wafer, and a second etching step in which the etching solution is dispensed radially from the center of the wafer and over a maximum distance which is less than the radius of said wafer.Type: GrantFiled: August 29, 2005Date of Patent: July 8, 2008Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventor: Cêcile Delattre
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Patent number: 7387455Abstract: Rinsing nozzles 310a to 310e are moved on a wafer W while they are discharging rinsing solution 326. At that point, discharging openings 317a to 317e are contacted to developing solution 350 coated on the wafer W or rinsing solution 326 on the wafer W. Thus, the impact against the wafer W can be suppressed. As a result, pattern collapse can be prevented. In addition, a front portion of the developing solution 350 can push away the developing solution 350.Type: GrantFiled: May 16, 2003Date of Patent: June 17, 2008Assignee: Tokyo Electron LimitedInventors: Tetsutoshi Awamura, Yukio Kiba, Keiichi Tanaka, Takahiro Okubo, Shuuichi Nishikido
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Patent number: 7354869Abstract: A method for a substrate processing apparatus having a substrate holding mechanism and a chemical solution dispensing/sucking mechanism including a chemical solution dispensing port for supplying a first chemical solution and a chemical solution suction port, includes placing the target substrate on the substrate holding mechanism, laying out an auxiliary plate at a periphery of the substrate such that the two main faces are substantially flush with each other, supplying a second chemical solution onto the main faces, dispensing the first solution from the dispensing port and sucking the first and second solutions through the suction port, with the dispensing and suction ports brought into contact with the second solution, and while dispensing the first solution from the dispensing port and sucking the first solution through the suction port, scanning the dispensing/sucking mechanism such that the dispensing and suction ports are opposed to the main face of the substrate.Type: GrantFiled: April 12, 2005Date of Patent: April 8, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Hideaki Sakurai, Masamitsu Itoh
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Patent number: 7351642Abstract: A process and method for compensating for a radial non-uniformity on a wafer that includes the steps of: centering a rotational thickness non-uniformity of a film on the wafer about the axis of the spin susceptor following a CMP process; positioning a nozzle in the spin processing unit to direct the etching solution along a radius of the wafer; adjusting the flow of the etching solution from the nozzle; adjusting the rotational speed of the spin susceptor to control the residence time of the etching solution; and coordinating the rotational speed of the spin susceptor, flow of etching solution and positioning of the nozzle to maximize the removal of material. The process may be utilized to compensate for the bowl-shaped non-uniformities of an STI oxide. These non-uniformities are compensated for and addressed after a CMP process.Type: GrantFiled: January 14, 2005Date of Patent: April 1, 2008Assignee: Infineon Technologies Richmond, LPInventors: Walter Hartner, Joseph Page, Jonathan Davis
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Patent number: 7344955Abstract: A method (and apparatus) of replicating a pattern on a structure, includes using imprint lithography to replicate a pattern formed on a first structure onto a portion of a second structure.Type: GrantFiled: November 19, 2004Date of Patent: March 18, 2008Assignee: International Business Machines CorporationInventors: Matthew E. Colburn, Yves C. Martin, Theodore G. van Kessel, Hematha K. Wickramasinghe
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Publication number: 20080057730Abstract: The present invention provides a method for manufacturing an integrated circuit. In one embodiment, the method includes etching one or more openings within a substrate using an etch tool, and subjecting the one or more openings to a post-etch clean, wherein a delay time exists between removing the substrate from the etch tool and the subjecting the one or more opening to the post-etch clean. This method may further include exposing the substrate having been subjected to the post-etch clean to a rinsing agent, wherein a resistivity of the rinsing agent is selected based upon the delay time.Type: ApplicationFiled: August 31, 2006Publication date: March 6, 2008Applicant: Texas Instruments IncorporatedInventors: Phillip Daniel Matz, Trace Hurd
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Patent number: 7338909Abstract: A method and apparatus for locally etching a substrate area the method including providing a substrate comprising a process surface; depositing a material layer over the process surface; and, applying a wet etchant to cover a targeted etching portion of the process surface while excluding an adjacent surrounding area to selectively etch the material layer overlying the targeted etching portion.Type: GrantFiled: June 18, 2004Date of Patent: March 4, 2008Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.Inventors: Yu-Liang Lin, Henry Lo, Chung-Long Chang, Gorge Huang, Tony Lu, Gnesh Yeh, Candy Liang, Chun-Hsien Lin, Mei Sheng Zhou, Sunny Su, Ai-Sen Liu, Cheng-Lin Huang, Li-Jui Chen, Shih Che Wang
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Patent number: 7312160Abstract: The removing solution containing a cerium (IV) nitrate salt, periodic acid or a hypochlorite can be applied to metals containing copper, silver or palladium and also to metals containing other metals having a relatively large oxidation-reduction potential.Type: GrantFiled: January 24, 2003Date of Patent: December 25, 2007Assignee: NEC Electronics CorporationInventors: Hidemitsu Aoki, Hiroaki Tomimori
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Patent number: 7276449Abstract: A method for moving resist stripper across the surface of a semiconductor substrate includes applying a wet chemical resist stripper, such as an organic or oxidizing wet chemical resist stripper, to at least a portion of a photomask positioned over the semiconductor substrate. A carrier fluid, such as a gas, is then directed toward the semiconductor substrate so as to move the resist stripper across the substrate. The carrier fluid may be directed toward the substrate as the resist stripper is being applied thereto or following application of the resist stripper. A system for effecting the method is also disclosed.Type: GrantFiled: January 13, 2005Date of Patent: October 2, 2007Assignee: Micron Technology, Inc.Inventor: Terry L. Gilton
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Patent number: 7186577Abstract: A method of monitoring a density profile of impurities, the method including presetting a monitoring position of a thin layer coated on a substrate, the density profile of impurities being monitored from the monitoring position in a direction of thickness of the thin layer, moving an exposer for exposing a local area of the thin layer to the monitoring position, exposing the local area of the thin layer along the direction of thickness of the thin layer, forming a shape profile of the exposed local area of the thin layer, and monitoring the density profile of impurities by determining a density of impurities in accordance with the shape profile, and an apparatus therefor. The impurity density profile may be monitored without destroying a substrate on which a thin layer is coated, and an amount of impurities used for forming the thin layer may be monitored and controlled in real-time.Type: GrantFiled: February 27, 2004Date of Patent: March 6, 2007Assignee: Samsung Electronics Co. Ltd.Inventors: Yun-Jung Jee, Sun-Yong Choi, Chung-Sam Jun, Kwan-Woo Ryu
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Patent number: 7179753Abstract: In a process for planarization of semiconductor substrates in which a layer which has been applied to a semiconductor substrate which has a trench and/or contact holes is removed such that the layer remains solely in the area of the trenches or contact holes, instead of as in the prior art the etching medium being applied in drops, the etching medium is applied in a continuous flow with a flow rate of at least 0.4 l/min so that the etching medium covers the entire surface of the semiconductor substrate to be planarized. This technique yields a differentiated etching rate, the etching speed in the area of the fields between the trenches or contact holes being greater than in the area of the trenches themselves, so that as a result the coating applied to the semiconductor substrate is etched away more quickly than in the area of the trenches and finally material remains only in the area of the trenches or contact holes.Type: GrantFiled: May 14, 2002Date of Patent: February 20, 2007Assignee: Sez AGInventors: Hans-Jurgen Kruwinus, Reinhard Sellmer
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Patent number: 7160808Abstract: A method of relieving surface stress on a thin wafer by removing a small portion of the wafer substrate, the substrate being removed by applying a warm solution of KOH to the backside of the wafer while the wafer spins. The wafer may be supported on a rotatable platform adapted to direct the flow of chilled, deionized water underneath the device side of the wafer. The chilled water supports the wafer and protects the devices built-up on the wafer from the corrosive effects of KOH and from thermal damage.Type: GrantFiled: June 1, 2004Date of Patent: January 9, 2007Assignee: StrasbaughInventor: Salman M. Kassir
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Patent number: 7151058Abstract: In a method for removing a nitride layer of a semiconductor device, an etchant including about 15 to about 40 percent by volume of hydrofluoric acid, about 15 to about 60 percent by volume of phosphorous acid, and about 25 to about 45 percent by volume of deionized water is prepared. The etchant is provided onto a nitride layer that is formed on a bevel, a front side or a backside of a substrate to remove the nitride layer. The substrate is rinsed using deionized water, and then the substrate is dried. The etchant rapidly removes the nitride layer at a relatively low temperature to avoid damage to the substrate.Type: GrantFiled: June 30, 2004Date of Patent: December 19, 2006Assignee: Samsung Electronics Co., Ltd.Inventor: Sang-Mi Lee
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Patent number: 7129174Abstract: Methods of fabricating a semiconductor device can include forming at least one layer on a first and a second side of a semiconductor substrate. Portions of the at least one layer may be removed on the first side of the semiconductor substrate to form a pattern of the at least one layer on the first side of the substrate while the at least one layer is maintained on the second side of the substrate. A capping layer can be formed on the pattern of the at least one layer on the first side of the substrate and on the at least one layer on the second side of the semiconductor substrate. The capping layer can be removed on the second side of the semiconductor substrate, thereby exposing the at least one layer on the second side of the substrate while maintaining the capping layer on the first side of the substrate.Type: GrantFiled: March 23, 2004Date of Patent: October 31, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Jin Kim, Young-Wook Park, Jeong-Do Ryu
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Patent number: 7119027Abstract: Where a thin film formed on a glass substrate is etched with a solution containing a fluoride, insoluble residues formed by the reaction of the solution with glass substrate components adhere to the back of the substrate to cause etching non-uniformity called roller marks. So, a solution is supplied directly to supporting members for supporting the glass substrate, or concentratedly to a region where the substrate and the supporting members come into contact and from a position opposite to the transporting direction of the substrate, or to both the supporting members and regions where the substrate and the supporting members come into contact. This enables the roller marks to be kept from forming, consequently making it possible to improve display quality of display devices.Type: GrantFiled: January 8, 2004Date of Patent: October 10, 2006Assignee: Hitachi Displays Ltd.Inventors: Toshiyuki Ohsawa, Yoichi Takahara, Toshiki Kaneko, Daisuke Sonoda
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Patent number: 7119026Abstract: A pattern forming method of the present invention includes the steps of forming, on a substrate before droplets are ejected onto the substrate, a water repelling area, in which a contact angle between the droplet and the target surface is a first contact angle, and a water attracting line, which is adjacent to the water repelling area and in which a second contact angle is smaller than the first contact angle and which is to be the pattern to be formed; and landing droplets onto the target surface such that part of the droplet landed is in a water repelling area and part of the droplet landed is in a water attracting line, the equation (1) is satisfied, D?L×{1+2(cos ?2?cos ?1)}??(1) where D is a droplet diameter, L is a pattern width, ?1 is a first contact angle, and ?2 is a second contact angle. By decreasing the number of discharged droplets, it is possible to prevent increase of a tact time and decrease of an inkjet operating life.Type: GrantFiled: June 5, 2003Date of Patent: October 10, 2006Assignee: Sharp Kabushiki KaishaInventors: Mitsuru Honda, Takaya Nakabayashi, Akiyoshi Fujii
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Patent number: 7022610Abstract: A method for cleaning semiconductor substrates includes a DI water clean operation that uses a spin speed no greater than 350 rpm. The cleaning method may include additional cleaning operations such as an organic clean, an aqueous chemical clean or a DI water/ozone clean. The cleaning method may be used to clean substrates after the conclusion of an etching procedure which exposes a single film between a Cu-containing conductive material and the environment. The spin speed of the DI water clean operation prevents copper corrosion due to breakdown of the film that separates the Cu-containing conductive material from the environment.Type: GrantFiled: December 22, 2003Date of Patent: April 4, 2006Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chun-Li Chou, Yih-Ann Lin, Yi-Chen Huang, Chao-Cheng Chen, Hun-Jan Tao
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Patent number: 7008877Abstract: The present invention provides a method and an apparatus for etching a photolithographic substrate. The photolithographic substrate is placed on a support member in a vacuum chamber. A processing gas for etching a material from the photolithographic substrate is introduced into the vacuum chamber, and a plasma is generated. An RF bias is supplied to the support member in the vacuum chamber through an RF bias frequency generator at or below the ion transit frequency. Exposed material is etched from the photolithographic substrate with improved CD Etch Linearity and CD Etch Bias since the low frequency bias allows the developed charge on the photolithographic substrate, generated by the plasma, to dissipate.Type: GrantFiled: May 3, 2004Date of Patent: March 7, 2006Assignee: Unaxis USA Inc.Inventors: Christopher Constantine, Jason Plumhoff, Russell Westerman, David J. Johnson
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Patent number: 7001086Abstract: A developing method comprises determining in advance the relation of resist dissolution concentration in a developing solution and resist dissolution speed by the developing solution, estimating in advance the resist dissolution concentration where the resist dissolution speed is a desired speed or more from the relation, and developing in a state in which the resist dissolution concentration in the developing solution is the estimated dissolution concentration or less.Type: GrantFiled: October 21, 2004Date of Patent: February 21, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Masamitsu Itoh, Ikuo Yoneda, Hideaki Sakurai
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Patent number: 6992014Abstract: A method for controlling a process on a substrate. The method comprising: providing the substrate, the substrate having an upper surface, an opposite lower surface and an edge between the upper and lower surfaces; processing the upper surface of the substrate with a first fluid; directing a second fluid against a portion of the lower surface proximate to the edge of the substrate, wherein the second fluid flows adjacent to the edge of the substrate; and controlling the temperature of the second fluid in order to affect a processing of an edge region of the upper side of the substrate.Type: GrantFiled: November 13, 2002Date of Patent: January 31, 2006Assignee: International Business Machines CorporationInventors: Casey J. Grant, Joel M. Sharrow, John J. Snyder
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Patent number: 6969688Abstract: A wet etchant solution composition and method for etching oxides of hafnium and zirconium including at least one solvent present at greater than about 50 weight percent with respect to an arbitrary volume of the wet etchant solution; at least one chelating agent present at about 0.1 weight percent to about 10 weight percent with respect to an arbitrary volume of the wet etchant solution; and, at least one halogen containing acid present from about 0.0001 weight percent to about 10 weight percent with respect to an arbitrary volume of the wet etchant solution.Type: GrantFiled: October 8, 2002Date of Patent: November 29, 2005Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Baw-Ching Perng, Fang-Cheng Chen, Hun-Jan Tao, Peng-Fu Hsu, Yue-Ho Hsieh, Chih-Cheng Wang, Shih-Yi Hsiao
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Patent number: 6967174Abstract: A wafer chuck includes alignment members that allows a semiconductor wafer to be properly aligned on the chuck without using a separate alignment stage. The alignment members may be cams, for example, attached to arms of the wafer chuck. These members may assume an alignment position when a robot arm places the wafer on the chuck. In this position, they guide the wafer into a proper alignment position with respect to the chuck. During rotation at a particular rotational speed, the alignment members move away from the wafer to allow liquid etchant to flow over the entire edge region of the wafer. At still higher rotational speeds, the wafer is clamped into position to prevent it from flying off the chuck. A clamping cam or other device (such as the alignment member itself) may provide the clamping.Type: GrantFiled: February 3, 2003Date of Patent: November 22, 2005Assignee: Novellus Systems, Inc.Inventors: Steven T. Mayer, Steve Taatjes, Andy McCutcheon, Jim Schall, Jingbin Feng