Abstract: A new polysilicon-buffered field isolation process provides reduced stress during field oxidation and reduced bird's beak. Prior to forming the LOCOS masking stack conventionally used for field isolation, a polysilicon buffer layer is first formed on the semiconductor wafer. The polysilicon buffer layer relieves stress between the masking stack and semiconductor wafer similar to conventional Poly-buffered LOCOS processes, but additionally provides sacrificial silicon into which the bird's beak region extends. Subsequent deprocessing of mask and buffer layers removes a significant portion of the bird's beak region, thereby providing active areas having improved physical and electrical characteristics.

Abstract: This invention is a process for manufacturing a random access memory array. Each memory cell within the array which results from the process incorporates a stacked capacitor, a silicon nitride coated access transistor gate electrode, and a self-aligned high-aspect-ratio digit line contact having a tungsten plug which extends from the substrate to a metal interconnect structure located at a level above the stacked capacitor. The contact opening is lined with titanium metal which is in contact with the substrate, and with titanium nitride that is in contact with the plug. Both the titanium metal and the titanium nitride are deposited via chemical vapor deposition reactions.

Abstract: A cleaning method and a cleaning device which require an extremely short time for processing and also insure and extremely high cleaning effect. Foreign materials deposited on a substrate are removed with a cleaning liquid prepared by mixing a basic and water-soluble fluoride and an oxidizing agent in pure water.

Abstract: First and second semiconductor substrate samples formed with a first oxide layer with holes and a third semiconductor substrate sample formed with a second oxide layer having no hole are prepared. The first and the third samples are subject to the same contaminating process for contaminating the surface of the first oxide layer of the first sample and the surface within the hole, and the surface of the second oxide layer of the third sample. All of the first and second layers of the first to third samples are dissolved by the HF vapor. The dissolved solutions are collected and analyzed the amount of contaminating material contained in respective solutions. The contamination amount in the hole is derived from the first, second and third contamination amount from an equation:contamination amount in the hole =first contamination amount-second contamination amount-(surface exposing ratio.times.

Abstract: A method of fabricating shallow trench isolation with multi-step HDP process for avoiding kinks is described. This method is to form two insulator layers with different etching rates, the etching rate of outer insulator layer being slower than that of inner insulator layer. Additionally, use of a multi-step HDP process produces better gapfilling and avoid clipping phenomenon in shallow trench isolations. This method comprises the following steps. A substrate having a mask layer thereabove is provided. A pattern is defined on the mask layer to form a trench. Then, a first insulator layer, which covers the inner wall of the trench and the top surface of the mask layer, is formed. Next, a second insulator layer is formed in the trench and over the first insulator layer, the etching rate of the first insulator layer being slower than that of the second insulator layer. The first and the second insulator layer are removed, using said mask layer as a etching stop layer.

Abstract: The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of etching inorganic antireflective layers without etching excessive amounts of an underlying oxide. According to one aspect of the present invention, the antireflective layer is selectively etched using an etchant which comprises about 35-40 wt. % NH.sub.4 F and about 0.9-5.0 wt. % H.sub.3 PO.sub.4 in an aqueous solution.

Abstract: An alumina film, a silicon oxide film, and a silicon nitride film formed on a substrate containing a large amount of alumina are etched by using an etching material in which the concentration of ammonium fluoride, which is a component of BHF, is set low. Etching is performed by using an etching material that is an aqueous solution produced by mixing hydrofluoric acid, ammonium fluoride and water at a weight ratio of x:y:(100-x-y) where x and y satisfy a relationship y<-2x+10 (0<x.ltoreq.5, 0<y.ltoreq.10). 50% hydrofluoric acid on the market and 40% aqueous solution of ammonium fluoride are used.

Abstract: The present invention relates to a method of manufacturing an opening through a dielectric layer. The method comprises treating a polished dielectric layer with a wet etch selectively enchancing composition, such as buffered HF, prior to the formation of a patterned photoresist to improve the lateral-to-vertical wet etch ratio.

Abstract: The present invention provides systems, methods and apparatus for high temperature (at least about 500-800.degree. C.) processing of semiconductor wafers. The systems, methods and apparatus of the present invention allow multiple process steps to be performed in situ in the same chamber to reduce total processing time and to ensure high quality processing for high aspect ratio devices. Performing multiple process steps in the same chamber also increases the control of the process parameters and reduces device damage. In particular, the present invention can provide high temperature deposition, heating and efficient cleaning for forming dielectric films having thickness uniformity, good gap fill capability, high density, low moisture, and other desired characteristics.

Abstract: There is provided a method of fabricating a semiconductor device, including the steps of (a) forming impurity-diffused layers at a surface of a silicon semiconductor substrate in selected regions, (b) forming a refractory metal film over the impurity-diffused layers, (c) carrying out first thermal annealing in nitrogen atmosphere to convert the refractory metal film into a refractory metal silicide layer, (d) causing damage to a denaturated layer having been formed over the refractory metal film due to the first thermal annealing, (e) etching both the denaturated layer and non-reacted portions of the refractory metal film with a solution containing ammonia and hydrogen peroxide therein, and (f) carrying out second thermal annealing in nitrogen atmosphere to reduce resistance of the refractory metal silicide layer. For instance, the damage is caused to the denaturated layer by arsenic (As) ion implantation. The damage may be caused to the denaturated layer by exposing to oxygen plasma.

Abstract: A surface having an exposed silicon/silica interface is cleaned by ah HF dip, followed immediately by a rinse in citric acid, followed by a rinse in deionized water. Low pH of the citric acid significantly prevents the formation of a charge differential between the silica and silicon portions of the surface, which charge differential would otherwise cause any silica particles present to remain on the silicon portion of the surface. Surfactant properties of the citric acid help remove any silica particles from the surface. The deionized water rinse then removes the citric acid from the surfaces, leaving a very clean, low particulate surface on both the silica and silicon portions thereof, with little or no etching of the silicon portion.

Abstract: A method of fabricating a semiconductor device includes the steps of sequentially forming a gate oxide layer, a gate material layer and a cap insulating layer on a semiconductor substrate, selectively etching them to form a gate, sequentially forming a plurality of material layers on the overall surface of the semiconductor substrate including the gate, etching them back to form a gate sidewall spacer out of the plurality of material layers, and selectively removing the plurality of material layers forming the gate sidewall spacer to form gate sidewall spacers having lengths different from each other, the lengths depending on a particular region of the substrate.

Abstract: The invention relates to integrated circuits and to methods of forming self-aligned silicidation structures. In an exemplary embodiment, a first insulating layer is formed on the surface of a semiconductor substrate which includes an electrode. A second insulating layer is formed over the first insulating layer and a photoresist pattern is formed over a silicide exclusion area. Exposed portions of the first and second insulating layers are removed by one or more etching steps, wherein an etchant used to remove the exposed portions of the second insulating layer has a higher selectivity for the second insulating layer than for the first insulating layer. A silicide layer can then be formed over the surface of the semiconductor substrate except for silicide exclusion areas. Modification of the profiles of features underlying the first insulating layer, such as sidewall spacer and field oxides can thereby be prevented.

Abstract: A semiconductor processing method of forming a capacitor includes, a) providing a mass of electrically insulative oxide of a first density; b) densifying the oxide mass to a higher second density, the densified oxide mass being characterized by a wet etch rate of less than or equal to about 75 Angstroms/minute in a 100:1 by volume H.sub.

Abstract: Pre heat-treatment processing of a silicon wafer to grow a hydrophilic oxide layer includes an initial step of contacting the wafer with a pre-clean SC-1 bath, thereby producing a silicon wafer surface that is highly particle free. After a deionized water rinse, the wafer is scoured with an aqueous solution containing hydrofluoric acid and hydrochloric acid to remove metallic-containing oxide from the wafer surface. In order to grow a hydrophilic oxide layer, an SC-2 bath (containing hydrogen peroxide and a dilute concentration of metal-scouring HCl) is used. The resulting hydrophilic silicon oxide layer grown on the surface of the silicon wafer using the combined SC-1.fwdarw.HF/HCL.fwdarw.SC-2 wafer cleaning process has a metal concentration no greater than 1.times.10.sup.9. The diffusion length of minority carriers is increased from a range on the order of 500-600 microns to a range on the order of 800-900 microns.

Abstract: A semiconductor device is fabricated by the step of forming a gate insulation film of a GaS film on a compound semiconductor layer; the step of forming an inter-layer insulation film on the gate insulation film; the step of etching the inter-layer insulation film selectively with respect to the gate insulation film by the use of an etchant containing hydrogen fluoride and ammonium fluoride, the step of exposing a prescribed region of the gate insulation film; and the step of forming a gate electrode on the exposed gate insulation film.

Abstract: A new method for planarization of shallow trench isolation is disclosed by using wet selective etching. The formation of the shallow trench isolation described herein includes a pad layer, a silicon nitride layer formed on a semiconductor substrate. A PE-TEOS oxide layer is subsequently formed on the silicon nitride layer. Then a shallow trench is created by photolithography and dry etching processes to etch the PE-TEOS oxide layer, the silicon nitride layer and the pad layer. Then, the photoresist is removed, an ozone-TEOS layer is form in the shallow trench and on the PE-TEOS oxide layer for the purpose of isolation. A wet selective etching is used to etch the ozone-TEOS layer. A CMP is performed to make the surface of the substrate with a planar surface. Then, a thermal annealing is used for densification of the ozone-TEOS layer and for forming a lining oxide to improve the isolation of the shallow trench isolation.

Abstract: Fluorine bearing spacers on the sidewalls of gate electrodes of a semiconductor device are provided to suppress hot carrier injection in the semiconductor device. In accordance with one embodiment of the invention, a semiconductor device is formed by forming at least one gate electrode on a surface of a substrate and forming fluorine bearing spacers on the sidewalls of the gate electrode. The fluorine bearing spacers may, for example, be formed of an NF.sub.3 -doped glass material.

Abstract: A method of fabricating a transistor. A dielectric layer is formed on an upper surface of a semiconductor substrate. A photoresist layer is then deposited on a dielectric layer and patterned with a photolithography exposure device to expose a region of the dielectric layer having a lateral dimension approximately equal to the minimum feature size resolvable by the photolithography exposure device. The exposed region of the dielectric layer is then removed to form a trench in the dielectric layer having opposed dielectric sidewalls and to expose a channel region of the semiconductor substrate having a lateral dimension approximately equal to the minimum feature size. First and second spacer structures are then formed on the respective dielectric sidewalls. The spacer structures shadow peripheral portions of the exposed channel region. A channel dielectric is then formed between the first and second spacer structures.

Abstract: According to the invention, a plurality of wafers are disposed in a steady-state rotating flow of a mixed acid in a main chemical processing zone in an etching trough, the rotating flow being formed to be substantially concentric circle with the wafers, thus permitting uniform dispersion of air bubbles for bubbling in the mixed acid and stable flow thereof to obtain reliable reproduction of satisfactory flatness and luster. A flow of mixed acid in the etching trough is formed as a superficial horizontal laminar flow in the neighborhood of the liquid level and a rotating flow induced in the neighborhood of the semiconductor wafer. Mixed acid in the etching trough is caused to overflow from the mixed acid supply side to the opposite side and is thus discharged.

Abstract: A method for treating thin silicon web crystals used to produce solar cells in order to remove complex SiOx contaminants from the web after growth. A dendritic silicon web with {111} surface orientation is immersed in a caustic solution of KOH or NaOH at a temperature at a range from about 80 to about 85.degree. C. for a period of about five to about ten minutes. The caustic solution quickly removes the SiOx contaminants, while leaving relatively unaffected the silicon crystal in the surface. After the caustic solution treatment, the web is rinsed in deionized water and optionally subjected to an acid cleaning with HCL or HF in order to remove any residual contaminants on the web surface.

Abstract: To planarize an insulating film formed on a semiconductor substrate, a polishing slurry containing cerium oxide is used to polish the surface of the insulating film. Using the cerium oxide included slurry as a polishing agent, the insulating film is not contaminated by alkali metals during the polishing process. Furthermore, the insulating film is polished at an enhanced polishing rate.

Abstract: A method for forming a contact hole in a phosphosilicate glass layer includes the steps of forming a phosphosilicate glass layer, reflowing the phosphosilicate glass layer, removing a surface portion of the phosphosilicate glass layer, and forming the contact hole in the phosphosilicate glass layer. In particular, the surface portion of the phosphosilicate glass layer can be on the order of about 1000 .ANG. thick, and the step of removing the surface portion can include etching the surface portion. Furthermore, the step of forming the contact hole can include the step of selectively wet etching the phosphosilicate glass layer followed by the step of selectively dry etching the phosphosilicate glass layer.

Abstract: A method of ion implanting a substrate is disclosed, which includes providing a substrate having a surface. A sacrificial layer of semiconductor material is formed on the surface and resistlessly patterning to define masked and unmasked portions. The unmasked portions are etched away to form an implantation mask on the substrate. Ions are implanted in the substrate underlying the etched away unmasked portions and the sacrificial layer is removed.

Abstract: A method for forming an electrode for an integrated circuit device includes the steps of forming a first insulating layer on a semiconductor substrate and forming a conductive mesa on the first insulating layer. The insulating layer has a contact hole therein exposing a portion of the substrate, and the conductive mesa covers and extends into the contact hole so that the conductive mesa is electrically connected to the substrate. A second insulating layer is formed on the first insulating layer wherein the second insulating layer surrounds the conductive mesa and wherein the second insulating layer has a second thickness greater than the first thickness. Accordingly, sidewalls of the second insulating layer are exposed adjacent the conductive mesa. Spacers are formed on the conductive mesa along the sidewalls of the second insulating layer, and the conductive mesa is etched using the second insulating layer and the spacers as an etching mask.

Abstract: Methods of wet etching through a silicon substrate using composite etch-stop layers are disclosed. In one embodiment, the composite etch stop comprises a layer of silicon dioxide and a layer of polyimide.

Abstract: An improved wet etchant process is provided which has greater selectivity than existing hot phosphoric acid etching processes and which maintains a high etch rate in use. The etchant composition includes a second acid having a boiling point higher than that of the phosphoric acid.

Abstract: Trench structures (12,32,35,46) are formed in single crystal silicon substrates (10,30) that have either a (110) or (112) orientation. A selective wet etch solution is used that removes only the exposed portions of the single crystal silicon substrates (10,30) that are in the (110) or (112) crystal planes. The trench structures (12,32,35,46) are defined by the {111} crystal planes in the single crystal silicon substrate (10,30) that are exposed during the selective wet etch process. Trench structures (32,35) can be formed on both sides of a single crystal silicon substrate (30) to form an opening (34). Opening (34) can be used as an alignment mark to align front side processing to backside and vice versa. Trench structures can also be use to form a microstructure (41,61) for a sensor (40,60).

Abstract: A method of removing an inorganic antireflective coating from a semiconductor substrate and a method of forming an integrated circuit (IC) are provided. In the former method, a sacrificial layer is formed over a semiconductor substrate, the layer being selectively removable from the substrate and compatible with photolithography. An inorganic antireflective coating such as SiON is then formed over the sacrificial layer. Thereafter, the sacrificial layer is removed from the substrate to lift the coating off the substrate. Preferred materials for the sacrificial layer include TiN, tetraethyl orthosilicate-based silicon oxide, spin-on-glass (SOG) such as hydrogen silsesquioxane and methyl silsesquioxane, and porous polymeric materials. In the latter method, a patterned layer of photoresist material is formed over the anitreflective coating.

Abstract: The chemoresistive gas sensor comprises a heating element integrated in a dedicated SOI substrate having an air gap in the intermediate oxide layer between two wafers of monocrystalline silicon. A sensitive element of tin oxide is formed over the heating element and separated from it by a dielectric insulating and protective layer. A trench formed at the end of the fabrication of the device, extends from the surface of the wafer in which the heating element is integrated, up to the air gap to mechanically separate and insulate the sensitive element from the rest of the chip, thereby improving the mechanical characteristics sensitivity and response of the sensor.

Abstract: After a resist mask is selectivity formed on an upper portion of a gate electrode containing mainly aluminum. At this state an anodization process is performed using an electrolytic solution, to form an anodic oxide film in a region other than a region of the upper portion on which the resist mask is formed. A silicon oxide film is formed to cover the gate electrode or the like Since an anodic oxide film is not formed on the region of the upper portion, contact holes for a wiring or an electrode made of aluminum are formed by etching the silicon oxide film using a hydrofluoric acid system etchant.

Abstract: A method is described which uses the differential etch behaviour of two different kinds of sequentially deposited silicon oxide layers in conjunction with controlled thicknesses and etching conditions to allow the etching of features such as via contact holes, oxide sidewalls, and crossover insulation edges to produce non-abrupt step height profiles for better edge coverage while still maintaining close adherence to minimum spacing design ground rules between adjacent features.

Abstract: A semiconductor processing method of forming a contact opening to a substrate includes forming at least one conductive line over the substrate adjacent a substrate contact area to which electrical connection is to be made. A first oxide layer is formed over the substrate to cover at least part of the contact area. A second oxide layer is formed over the first oxide layer and is formed from a different oxide than the first oxide layer. A first etch is conducted over the contact area and through the second oxide layer to a degree sufficient to leave at least a portion of the first oxide layer over the contact area. A second etch is conducted to a degree sufficient to remove substantially all of the first oxide layer left behind and to remove a desired amount of the second oxide layer laterally outwardly of the contact area.

Abstract: A method of removing inorganic contamination (contamination 104 of FIGS. 2a-2b) from a layer (layer 102) overlying a substrate (substrate 100), the method comprising the steps of: removing the layer overlying the substrate with at least one removal agent; reacting the inorganic contamination with at least one conversion agent, thereby converting the inorganic contamination; removing the converted inorganic contamination by subjecting it to at least one solvent agent, the solvent agent included in a first supercritical fluid; and wherein the converted inorganic contamination is more highly soluble in the solvent agent than the inorganic contamination.

Abstract: This invention relates to a method for protecting regions of a spin-on-glass(SOG) layer, which covers usable semiconductor dice, from dissolution damage during an etch step which removes SOG along the wafer edge. The endangered dice have portions which lie in the area affected by the edge rinse. Instead of performing the edge etching step immediately after the deposition of the SOG, the endangered dice are first selectively partially cured by exposure to ultraviolet radiation. This makes the SOG over these dice resistant to the SOG solvent used for the edge rinse. Up to ten percent of the total usable dice on the wafer can be salvaged by the method of this invention.

Abstract: Cleaning solutions for semiconductor devices comprise tetramethyl ammonium hydroxide, acetic acid, and water. Methods of removing contaminants from semiconductor devices comprise contacting the semiconductor devices with cleaning solutions to remove the contaminants from the semiconductor devices.

Abstract: A process is described for forming a heavily doped buried element below an active device region of a silicon wafer without the use of costly epitaxial layers and without incurring ion implantation damage within active device regions. The method is particularly applicable to active device regions which have small lateral dimensions. Thus, the technological trend towards shrinking devices favors the incorporation of the process of the invention. The process utilizes a silicon nitride hardmask to define a narrow band around the perimeter of the device active area. A deep implant is performed through this mask, placing a ring of dopant below and outside the active area. The silicon nitride hardmask is then patterned a second time to define the conventional field oxide isolation regions. The LOCOS field oxidation is then performed whereby the implanted dopant diffuses vertically, engaging the field oxide around the perimeter of the device region and laterally filling in the region under the device active area.

Abstract: According to the present invention, to flatten the surface of a silicon substrate by polishing an element isolating buried insulation film by chemical mechanical polishing, a polysilicon film is formed on the top surface of a projection of a silicon substrate. After that, a buried insulation film is formed all over the silicon substrate along the irregularities thereof. A carbon film is formed on the surface of a recess of the buried insulation film. Using the carbon film as a stopper, the buried insulation film is polished by the chemical mechanical polishing to ease the irregularities of the surface of the polished insulation film. Then the carbon film is removed and, using the polysilicon film as a stopper, the buried insulation film is polished by the chemical mechanical polishing to flatten the surface of the polished insulation film. Thus, the flatness of the buried insulation film can easily be controlled, and the surface of the silicon substrate can always be flattened satisfactorily.

Abstract: A semiconductor processing method of forming a contact opening includes providing a substrate having a node location to which electrical connection is to be made. A layer comprising doped silicon dioxide is formed over the node location. Thereafter, both O.sub.2 and O.sub.3 are flowed simultaneously to the substrate along with tetraethylorthosilicate to the substrate to form a continuous layer comprising undoped silicon dioxide on the layer comprising doped silicon dioxide. During the flowing, a ratio of O.sub.3 to O.sub.2 flows is increased to form an outer portion of the continuous layer comprising undoped silicon dioxide to have a higher etch rate for a selected wet etch chemistry than an inner portion of said continuous layer. A common contact opening is anisotropically dry etched into the layer comprising undoped silicon dioxide and into the layer comprising doped silicon dioxide over the node location to outwardly expose the node location.

Abstract: A method for etching aluminum containing layers. A layer (13) of aluminum nitride is formed on a semiconductor substrate (11). The layer (13) of aluminum nitride is etched using a dilute ammonium hydroxide solution that is diluted with water such that the ammonium hydroxide solution has one part of ammonium hydroxide to at least fifteen parts of water. The dilute ammonium hydroxide solution is showered onto the semiconductor substrate and forms an aluminum hydroxide layer. The aluminum hydroxide layer is dissolved by excess water in the dilute aluminum hydroxide solution and rinsed from the semiconductor substrate (11).

Abstract: One embodiment of the instant invention is a method of abruptly terminating etching of a dielectric layer on a semiconductor wafer, the method comprising the steps of: removing the semiconductor wafer from the etchant, the etchant is held a first temperature; and rinsing the semiconductor wafer in a rinse solution that is at a second temperature, the second temperature is at least 5.degree. C. colder than the first temperature. Preferably, the dielectric layer is comprised of: TEOS, BPSG, PSG, thermally grown oxide, and any combination thereof. Preferably, first temperature is approximately 25.degree. C. and the second temperature is approximately 0.degree. to 5.degree. C.; or the first temperature is approximately 70.degree. to 90.degree. C. and the second temperature is approximately 10.degree. to 30.degree. C. Preferably, the etchant is comprised of a buffered or unbuffered HF acid, and the rinse solution is comprised of deionized water. The second temperature is, preferably, at least 15.degree. C.

Abstract: A layer of silicon dioxide is formed conformably over a substrate having a surface with non-planar topography. The layer of silicon dioxide is then implanted with a species that affects the etch rate of the silicon dioxide when etched in an HF based etchant. The implant energy, dose, and direction are chosen such that only a selected portion of the layer of silicon dioxide is implanted with the implant species. The layer of silicon dioxide is then etched in an HF based etchant. The HF etchant etches both doped and undoped silicon dioxide, but the implanted silicon dioxide is removed at a faster rate or slower rate, depending on the implant species, than the unimplanted silicon dioxide. This allows the formation of specialized silicon dioxide structures due to the selectivity of the etch as between the implanted and unimplanted portions of the layer of silicon dioxide, without any damage to silicon.

Abstract: A tungsten layer swells out from a contact hole into a tungsten layer on an inter-level insulating layer, and the tungsten layer is chemically mechanically polished so as to create s smooth top surface of the tungsten plug substantially coplanar with the upper surface of the inter-level insulating layer; the chemical mechanical polishing is changed from mild conditions to severe conditions at an intermediate point so that a shallow recess and scratches are not produced in the top surface of the inter-level insulating layer; the polishing speed, the particle size of powder in polishing slurry, the hydrogen ion concentration of the polishing slurry and additives are examples of the polishing condition to be controlled.

Abstract: A simple, non critical, low cost process step is added to the manufacture of integrated circuit wafers to remove a ridge of dielectric material remaining at the flat edge of the wafer after an edge rinse has removed the ridge of dielectric from the circular edges of the wafer. A layer of dielectric, such as Spin-On-Glass or the like, is formed on the wafer. An edge rinse is then used to remove the ridge of dielectric formed at the wafer edge, however the edge rinse does not remove the ridge of dielectric at the flat edge of the wafer. A layer of photoresist is formed on the wafer, selectively exposed, and developed to form a photoresist mask. The flat edge of the wafer is then dipped in buffered oxide etch to remove the dielectric material at the flat edge of the wafer. The photoresist mask is then stripped and processing of the wafer is continued.

Abstract: A method of cleaning wafer surfaces includes providing a wafer surface and cleaning the wafer surface using at least hydrofluoric acid (HF) and an etch reducing component. The etch reducing component is from the group of (R).sub.4 NOH wherein R=(C.sub.1 -C.sub.20)alkyls, either straight or branch chained, and further wherein each R is independently a (C.sub.1 -C.sub.20)alkyl, preferably a (C.sub.1 -C.sub.4)alkyl, and more preferably one of tetra ethyl ammonium hydroxide (TEAH) and tetra methyl ammonium hydroxide (TMAH). A cleaning solution for use in cleaning a wafer surface includes an H.sub.2 O diluted HF solution and an etch reducing component from the group above, preferably, TMAH. A system for performing an HF vapor cleaning process includes a vapor chamber for positioning a wafer having a wafer surface and means for providing an HF vapor to the vapor chamber. The HF vapor includes an inert carrier gas, an HF component, one of a water vapor or an alcohol vapor, and an etch reducing component.

Abstract: There is provided a method for manufacturing a capacitor in a semiconductor device including the steps of forming first and second insulating layers with a first contact hole through to a semiconductor substrate, patterning a first conductive layer to form a pedestal portion of a lower electrode, using a patterned third insulating layer selectively forming an upper portion of the lower electrode from a tungsten nitride thin film, and forming an undercut beneath the pedestal portion by wet-etching the second insulating layer.

Abstract: A surface having exposed doped silicon dioxide such as BPSG is cleaned with a solution that etches thermal oxide at least one-third as fast as it etches the exposed doped silicon dioxide, resulting in more thorough cleaning with less removal of the exposed doped silicon dioxide. Specific applications to formation of container capacitors are disclosed. Preferred cleaning solutions include about 46 parts ammonium fluoride, about 9.5 parts hydrogen fluoride, and about 8.5 parts ammonium hydroxide in about 100 parts water by weight; and about 670 parts ammonium fluoride and about 3 parts hydrogen fluoride in about 1000 parts water by weight. The latter solution is also useful in cleaning methods in which a refractory metal silicide is exposed to the cleaning solution such as in cleaning prior to spacer formation or prior to a gate stack contact fill, in which case about 670 parts ammonium fluoride and about 1.6 parts hydrogen fluoride in about 1000 parts water is most preferred.