Abstract: The present invention provides a MOS semiconductor device which enables gate leakage current reduction with a thinner gate dielectric film for higher speed, and a production method thereof. According to the present invention, a gate dielectric film 6 is made as follows: after forming a silicon nitride film 3 with a specified thickness, it is annealed in an oxidizing atmosphere to form silicon oxide 4 on the silicon nitride film 3, then this silicon oxide 4 is completely removed by exposure to a dissolving liquid. As a result, at depths between 0.12 nm and 0.5 nm from the top surface of the silicon nitride film 3 in the gate dielectric film 6 whose main constituent elements are silicon, nitrogen and oxygen, the nitrogen concentration is higher than the oxygen concentration. This enables the use of a thinner gate dielectric film with silicon, nitrogen and oxygen as main constituent elements while at the same time realizing reduction in leakage currents.

Abstract: The invention encompasses a semiconductor processing method of cleaning a surface of a copper-containing material by exposing the surface to an acidic mixture comprising Cl+, NO3+ and F+. The invention also includes a semiconductor processing method of forming an opening to a copper-containing substrate. Initially, a mass is formed over the copper-containing substrate. The mass comprises at least one of a silicon nitride and a silicon oxide. An opening is etched through the mass and to the copper-containing substrate. A surface of the copper-containing substrate defines a base of the opening, and is referred to as a base surface. The base surface of the copper-containing substrate is at least partially covered by at least one of a copper oxide, a silicon oxide or a copper fluoride.

Abstract: A method for forming thoroughly deposited shallow trench isolation. A first oxide layer is formed conformally over the surface of a semiconductor substrate and on a trench thereon with an aspect ratio greater than 3. A liquid etching shield is filled in the trench by spin-spraying to cover the oxide layer in the trench. An etchant is then sprayed over the surface of the semiconductor substrate to remove the uncovered oxide layer and expose the surface of the semiconductor substrate. The density of the etchant is less than that of the liquid etching shield. A second oxide layer is deposited in the trench to form isolation without voids or seams.

Abstract: A method and an apparatus for forming an under bump metallurgy layer over a contact pad area on an interconnect formed over a semiconductor substrate are provided which eliminate a pretreatment process for removing native oxide on the contact pad area prior to the deposition of the under bump metallurgy layer. In one embodiment, the removal of a cap layer which insulates the contact pad area and the deposition of the under bump metallurgy layer are carried out without leaving a vacuum environment.

Abstract: A metrology method and system of structures on a wafer includes obtaining a projection image of at least a first portion of the structures on the wafer using a first metrology apparatus. A profile of at least a second portion of the structure on the wafer is obtained using a second metrology apparatus. The information from the profile obtained using the second metrology apparatus and the information from the projection image obtained using the first metrology apparatus are combined using a processor.

Abstract: A method of controlling the quantity and uniformity of distribution of bonded oxygen atoms at the interface between the polysilicon and the monocrystalline silicon includes carrying out, after having loaded the wafer inside the heated chamber of the reactor and evacuated the chamber of the LPCVD reactor under nitrogen atmosphere, a treatment of the wafer with hydrogen at a temperature generally between 500 and 1200° C. and at a vacuum generally between 0.1 Pa and 60000 Pa. The treatment is performed at a time generally between 0.1 and 120 minutes, to remove any and all the oxygen that may have combined with the silicon on the surface of the monocrystalline silicon during the loading inside the heated chamber of the reactor even if it is done under a nitrogen flux. After such a hydrogen treatment, another treatment is carried out substantially under the same vacuum conditions and at a temperature generally between 700 and 1000° C. with nitrogen protoxide (N2O) for a time generally between 0.

Abstract: A method for fabricating STI for semiconductor device. The method includes the following steps. A trench is formed on the semiconductor substrate, a liner oxide is formed on the bottom and sidewall of the trench, and then a liner nitride is formed on the liner oxide. The first oxide layer is deposited in the trench by high density plasma chemical vapor deposition. The first oxide layer is spray-etched to a predetermined depth, wherein the recipe of the spray etching solution is HF/H2SO4=0.3˜0.4. A second oxide layer is deposited to fill the trench by high density plasma chemical vapor deposition to form a shallow trench isolation structure.

Abstract: An integrated circuit die coupled to a package substrate and having circuitry in a circuit side opposite a back side is etched in a manner that inhibits the erosion of underfill material that is used around the periphery of the die and between the die and the package substrate. According to an example embodiment of the present invention, a protective coating adapted to resist etch chemicals is formed over the underfill material. The die is then etched using an etch chemistry that, absent the protective coating, would erode the underfill material. In this manner, etch chemistries that would harm the die, or even be unusable can be used to etch the die. In addition, problems associated with the underfill being eroded, such as die chipping, can be avoided.

Abstract: A composition for removing side wall which includes an aqueous solution containing both nitric acid and at least one of carboxylic acids selected from the group consisting of polycarboxylic acid, aminocarboxylic acid, and salts thereof; a method of removing side wall; and a process for producing a semiconductor device. Use of the composition is effective in removing side wall at a low temperature in a short time in semiconductor device production without corroding the wiring material, e.g., an aluminium alloy. Thus, a semiconductor device having an aluminium alloy wiring which has undergone substantially no corrosion can be efficiently produced.

Abstract: A method of measuring resistance in a deep trench. A first substrate having a first trench with a first depth is provided. A first collar insulating layer is formed on the sidewall of the first trench. A first polysilicon layer is formed in the first trench and on the first substrate to obtain a first polysilicon plug in the first trench. The first polysilicon layer and the first substrate are doped with impurity ions, and a first N well is formed in the first substrate. The above procedures are repeated to obtain a second substrate having a second trench with a second depth not equal to the first depth. A voltage is applied to the first and second substrates respectively to obtain a first total resistance of the first substrate and a second total resistance of the second substrate. Finally, the first total resistance and second total resistance are converted by calculation to obtain a resistance of the first polysilicon plug and a resistance of the second polysilicon plug.

Abstract: A method of depositing a silicon oxynitride spacer film on a gate stack in a semiconductor device involves contacting the gate stack with bistertiarybutylaminosilane (BTBAS), at least one nitrogen containing compound and oxygen (O2). The deposition is controlled to provide a wet etch rate for the deposited spacer film that is within the range of about 25 Angstroms per minute to less than or equal to about 1 Angstrom.

Abstract: A method (M) of determining the effectiveness of a deposited thin conformal barrier layer (30) by forming a test specimen and measuring the copper (Cu) penetration from a metallization layer (40) through the barrier layer (30) (e.g., refractory metals, their nitrides, their carbides, or their other compounds), through a thin insulating dielectric layer (20) (e.g., SiO2), and into a semiconductor (10) substrate (e.g., Si), wherein the interaction between the migrating metal ions and the semiconductor ions are detected/monitored, and wherein the detection/monitoring comprises (1) stripping at least a portion of the insulating dielectric layer (20) and the barrier layer (30) and (2) examining the semiconductor substrate (10) surface of the test specimen, thereby improving interconnect reliability, enhancing electromigration resistance, improving corrosion resistance, reducing copper diffusion, and a test specimen device thereby formed.

Abstract: A stacked gate insulating film comprises a silicon oxide film and a tantalum oxide film which is stacked on the silicon oxide film and whose dielectric constant is higher than a dielectric constant of the silicon oxide film. The stacked gate insulating film is formed in accordance with the following steps. A semiconductor wafer is heated up, and the surface thereof is heat-oxidized. The silicon oxide film is formed on the semiconductor wafer (heat oxidation process). The silicon oxide film is etched back so as to be made thin (etch back process). The tantalum oxide film is stacked on the thin silicon oxide film (dielectric film formation process), thereby to form the stacked gate insulating film.

Abstract: A method of forming narrow gates comprising the following steps. A substrate is provided having an overlying Si3N4 or an SiO2/Si3N4 stack gate dielectric layer. A gate material layer is formed over the gate dielectric layer. A hard mask layer is formed over the gate material layer. The hard mask layer and the gate material layer are patterned to form a hard mask/gate material layer stack. A planarized dielectric layer is formed surrounding the hard mask/gate material layer stack. The patterned hard mask layer is removed from over the patterned gate material layer to form a cavity having exposed dielectric layer side walls. Masking spacers are formed on the exposed dielectric layer side walls over a portion of the patterned gate material layer. The patterned gate material layer is etched using the masking spacers as masks to expose a portion of the gate dielectric layer. The planarized dielectric layer is removed. The masking spacers are removed to form narrow gates comprising gate material.

Abstract: A method and a solution for preparing SEM samples comprising low-K dielectric materials. The process begins by providing a SEM sample comprising low-K dielectric material and silicon oxide material. A solution is formed for preparing (staining and etching) the SEM sample by adding NH4F (s) to a solution comprising CH3COOH having a concentration of about 98% at a ratio of about 1 g NH4F (s):20 ml CH3COOH, then stirring until the NH4F (s) is thoroughly dissolved. Alternatively, the NH4F (s) can be added to a solution comprising HNO3 having a concentration of about 70% and CH3COOH having a concentration of about 98%, with a volume ratio of about 15 ml HNO3:20 ml CH3COOH. The NH4F (s) is added at a ratio of about 1 g NH4F (s):35 ml CH3COOH and HNO3, and stirred until the NH4F (s) is thoroughly dissolved. The SEM sample is then etched in this solution for about 3 seconds, whereby the low-K dielectric material and silicon oxide material have similar etch rates with good selectivity to metals.

Abstract: A method and apparatus for analyzing a semiconductor surface obtains a sample from a localized section of a wafer. The sample is obtained by isolating a section of a wafer with a sampling apparatus, dispensing liquid onto the isolated section of the wafer, dissolving compounds of interest in the liquid, removing a portion of the liquid, and analyzing the liquid and dissolved compounds of interest. The liquid can be an etching solution, an organic solvent, or other suitable solvent. Samples and analyses can, thus, be obtained as a function of position on the wafer. Analyses as a function of depth can also be determined by sampling and analyzing an isolated portion of the wafer as a function of time.

Abstract: In a method of fabricating a microstructure for microfluidics applications, a first layer of etchable material is formed on a suitable substrate. A mechanically stable support layer is formed over the etchable material. A mask is applied over the support to expose at least one opening in the mask. An anistropic etch is then performed through the opening to create a bore extending through the support layer to said layer of etchable material. After performing an isotropic etch through the bore to form a microchannel in the etchable material extending under the support layer, a further layer is deposited over the support layer until overhanging portions meet and thereby close the microchannel formed under the opening.

Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

Abstract: A method of forming a trench type isolation layer is provide, wherein the method comprises: forming a trench by etching after forming a trench etching pattern on a substrate; forming a silicon nitride liner on an inner wall of the trench; filling the trench with a first buried oxide layer; exposing an upper part of the liner of the trench by recessing the first buried oxide layer using a wet process; removing the upper part of the silicon nitride liner using isotropic etching; and filling the recessed space of the trench with a second buried oxide layer. The method may further comprise: forming the trench etching pattern by depositing and patterning a silicon nitride layer, and forming a thermal oxide layer, preferably through annealing, for healing etching defects on an inner wall of the trench, between forming the trench and forming the liner.

Abstract: A chemical mechanical polishing slurry comprising a film forming agent, an oxidizer, a complexing agent and an abrasive, and a method for using the chemical mechanical polishing slurry to remove copper alloy, titanium, and titanium nitride containing layers from a substrate.

Abstract: An isolation oxide film is formed on a silicon substrate, and a pad oxide film is formed in an active region. A lower electrode of a capacitor is formed on the isolation oxide film, and a multilayered film (ON film) comprising a silicon oxide film and a silicon nitride film is formed on the lower electrode. A mask oxide film is formed on the ON film so as to cover only the area in the vicinity of the lower electrode. The ON film is patterned by means of wet etching capable of selectively removing the silicon nitride film. The pad oxide film and the mask oxide film are removed before forming a gate oxide film. Fabrication of a capacitor and a transistor is completed by formation of gate electrodes and an upper electrode.

Abstract: The invention includes a method of cleaning a surface of a copper-containing material by exposing the surface to an acidic mixture comprising NO3−, F− and one or more organic acid anions having carboxylate groups. The invention also includes a semiconductor processing method of forming an opening to a copper-containing material. A mass is formed over a copper-containing material within an opening in a substrate. The mass contains at least one of an oxide barrier material and a dielectric material. A second opening is etched through the mass into the copper-containing material to form a base surface of the copper-containing material that is at least partially covered by particles comprising at least one of a copper oxide, a silicon oxide or a copper fluoride. The base surface is cleaned with a solution comprising nitric acid, hydrofluoric acid and one or more organic acids to remove at least some of the particles.

Abstract: To prevent a thick gate oxide film from being damaged by a cleaning and hydrofluoric-acid treatment preprocess performed prior to formation of a thin gate oxide film. A thick first gate oxide film is formed, and an insulating film, having etching resistance against the cleaning and hydrofluoric-acid treatment process for formation of thin second gate oxide film, is formed in an upper region of the first gate oxide film. A resist is then formed in a region where a thick gate insulating film is to be formed, and etching is performed on the first gate oxide film with the resist as a mask. The resist is stripped, then cleaning and hydrofluoric-acid treatment are performed on the silicon surface in a region where a thin gate insulating film is to be formed, and the thin second gate oxide film is formed.

Abstract: Methods for forming elements having a predetermined shape and for assembling the elements. In one example of a method, each of the elements includes a functional component which is disposed on a first face of a first substrate. A layer representing a first portion of the first substrate at a second face of the first substrate is removed, leaving a second portion of the first substrate on the first substrate. The second portion is etched through a first patterned mask on a surface of the second portion. The plurality of elements is then released from the first substrate. The plurality of elements may then be combined with a fluid to form a slurry. In another example of a method, the first face is etched vertically in regions adjacent to the edges of the plurality of elements, and regions below the first face are etched laterally, and then the plurality of elements are released from the substrate.

Abstract: A substrate with a metal oxide film deposited thereon is annealed, and then the surface of the metal oxide film is exposed to a plasma, after which the metal oxide film is removed by wet-etching.

Abstract: The present invention provides a method for improving the quality of thin oxides formed upon a semiconductor body. The etch and pre-clean processes are performed in situ, taking place in a single apparatus. This reduces the amount of handling of the wafers, their exposure to clean room air, and time delays between clean and oxidation. This results in both a higher yield and greater reliability. In addition, it reduces equipment requirements. The etch, employing a buffered oxide etchant, resist strip, and pre-clean, all occur in a single apparatus without transfer, yielding better results, despite the inherently dirty nature of the resist strip, than the traditional technique of transferring to a new apparatus for each of these steps. The improvements are particularly important for thin oxides such as the tunnel oxides of EEPROMs.

Abstract: Shallow trench isolation techniques are disclosed in which a nitride layer is formed on a semiconductor substrate, and a trench is formed through the nitride layer and into the semiconductor substrate. The nitride layer is removed prior to filling the isolation trench, and the fill material is planarized using a fixed-abrasive CMP process to mitigate or avoid step height in the shallow trench isolation process.

Abstract: A method to simplify the polycide gate structure fabrication processes by using a hardmask 240 to define a pattern of siliciding 260 a silicon layer 230, and then using the silicide 260 to mask removal of the unreacted silicon 220 and 230 in locations where the hardmask 240 had been present. The metal silicide 260 formed in the exposed silicon regions 220 and 230 functions as a self-aligned mask against the silicon 220 and 230 etching. By using a selective etching process between the silicon 220 and 230 and the silicide 260, the silicon 220 and 230 can be etched down to the gate oxide 210 to form the polycide (silicide/polysilicon) gate. The polycide gate formed by this method is particularly advantageous in DRAM applications, but can also be used as a MOS gate in a transistor.

Abstract: The present invention provides a method of manufacturing a MOS transistor of an embedded memory. The method of the present invention involves first defining a memory array area and a periphery circuit region on the surface of the semiconductor wafer and to deposit a gate oxide layer, an undoped polysilicon layer and a dielectric layer, respectively. Next, the undoped polysilicon layer in the memory array area is implanted to form a doped polysilicon layer followed by the removal of the dielectric layer in the memory array area. Thereafter, a metallic silicide layer and a passivation layer are formed, respectively, on the surface of the semiconductor wafer. The passivation layer, the metallic silicide layer and the doped polysilicon layer are then etched to form a plurality of gates in the memory array area. Next, the passivation layer, the metallic silicide layer and the dielectric layer in the periphery circuit region are removed.

Abstract: An electromechanical device includes a first frame having a first aperture therein, a second frame suspended in the first frame wherein the second frame has a second aperture therein, and a plate suspended in the second aperture. A first pair of beams support the second frame along a first axis relative to the first frame so that the second frame rotates about the first axis. A second pair of beams supports the plate along a second axis relative to the second frame so that the plate rotates about the second axis relative to the frame. The first and second axes preferably intersect at a 90° angle. A first actuator provides mechanical force for rotating the second frame relative to the first frame about the first axis. A second actuator provides mechanical force for rotating the plate relative to the second frame about the second axis. Accordingly, the plate can be independently rotated relative to the first axis and the second axis. Related methods are also disclosed.

Abstract: A method for forming a silicide of a metal with high-melting-point in a semiconductor device includes the step of removing a higher-density impurity area which acts for prevention of refractory-metal-silicification of diffused regions between the steps of implanting impurities to form an impurity-implanted region and annealing for refractory-metal-silicification of the diffused layer. The refractory-metal-silicification of the diffused regions proceeds smoothly to thereby prevent degradation of the initial gate withstand voltage and a higher sheet resistance.

Abstract: A microelectromechanical (MEMS) device and a method of fabricating a MEMS device are provided. The method of fabricating the MEMS device includes the steps of: etching a die release trench in a primary handle layer of a wafer having the handle layer, an etch-stop layer disposed on the primary handle layer, and a device layer disposed on the etch-stop layer; patterning a release trench in the device layer that is aligned with the release trench in the primary handle layer; temporarily attaching an additional handle layer to the primary handle layer; etching the device layer to define a structure in the device layer; removing the etch-stop layer; and removing the additional handle layer to release the die.

Abstract: A method for completely removing dielectric layers formed selectively upon a substrate employed within a microelectronics fabrication from regions wherein closely spaced structures such as self-aligned metal silicide (or salicide) electrical contacts may be fabricated, with improved properties and with attenuated degradation. There is first provided a substrate with employed within a microelectronics fabrication having formed thereon patterned microelectronics layers with closely spaced features. There is then formed a salicide block layer employing silicon oxide dielectric material which may be selectively doped. There is then formed over the substrate a patterned photoresist etch mask layer. There is then etched the pattern of the patterned photoresist etch mask layer employing dry plasma reactive ion etching. An anhydrous etching environment is then employed to completely remove the silicon oxide dielectric salicide block layer with attenuated degradation of the microelectronics fabrication.

Abstract: Disclosed is a method for forming contact by using the ArF lithography technology using a low-k dielectric sacrifice layer. The method comprises forming a layer to be etched on the semiconductor substrate, successively forming a low-k dielectric sacrifice layer and a hard mask on the etched layer, forming an anti-reflective layer and a photoresist pattern on the hard mask by using ArF lithography technology, selectively etching the anti-reflective layer and the hard mask and simultaneously removing the photoresist pattern when etching the hard mask, forming a contact hole exposing a surface of the semiconductor substrate by etching the low-k dielectric sacrifice layer and the layer by using the hard mask as a mask and removing the hard mask and the low-k dielectric sacrifice layer.

Abstract: A technique for fabricating a solar cell includes an n+ emitter region first being formed on a front surface of the cell, and then front and rear insulating layers being formed on both sides of the cell. P (Phosphorus)-source and B (Boron)-source are printed on the front and rear insulating layers, respectively, and then both dopants are diffused into the cell at high temperature. Therefore, n++ region in the front side of the cell and BSF (back surface field) region in the rear side of the cell is formed. Front and rear contact patterns are formed on the front and rear insulating layers, respectively. The n++ region and BSF region are exposed after front and rear contacts are formed on the front and rear insulating layers, respectively. The front and rear contacts contact the n++ region and BSF region, respectively.

Abstract: A monolithic inkjet printhead formed using integrated circuit techniques is described. A silicon substrate has formed on its top surface a thin polysilicon layer in the area in which a trench is to be later formed in the substrate. The edges of the polysilicon layer align with the intended placement of ink feed holes leading into ink ejection chambers. Thin film layers, including a resistive layer, are formed on the top surface of the silicon substrate and over the polysilicon layer. An orifice layer is formed on the top surface of the thin film layers to define the nozzles and ink ejection chambers. A trench mask is formed on the bottom surface of the substrate. A trench is etched (using, for example, TMAH) through the exposed bottom surface of the substrate and to the polysilicon layer. The etching of the polysilicon layer exposes fast etch planes of the silicon. The TMAH then rapidly etches the silicon substrate along the etch planes, thus aligning the edges of the trench with the polysilicon.

Abstract: When fabricating an MIM capacitive circuit in which a lower electrode and an upper electrode confront each other through a capacitive film, the lower electrode composed of titanium nitride (TiN), which is a metal that is resistant to oxidation by sulfuric acid, is formed on a substrate, following which the surface of this lower electrode is cleaned with a solution containing sulfuric acid, preferably, dilute sulfuric acid. A capacitive film composed of the dielectric material tantalum oxide (Ta2Q5) is then formed on the surface of the cleaned lower electrode, following which an upper electrode composed of the metal titanium nitride (TiN) is formed on the surface of the capacitive film. Cleaning with dilute sulfuric acid eliminates the presence of organic material or oxide material on the surface of the lower electrode, thereby preventing leakage current that is caused by these materials.

Abstract: A novel method of Cu seed layer deposition for ULSI metalization is disclosed. The method of Cu seed layer deposition for ULSI metalization comprises forming a diffusion barrier on a substrate, forming a poly silicon layer, amorphous silicon layer or TaSix layer on said diffusion barrier, replacing said poly silicon layer with copper to form a copper seed layer, and electroplating a thick copper film on said copper seed layer. In this invention, a chemical replacing solution comprising a replacing reactant and at least one etchant is used to replace the poly silicon layer with copper and to reduce the quantity of byproducts of the reaction.

Abstract: The invention includes a method of etching silicon dioxide, comprising doping a layer of silicon dioxide to form a layer of doped silicon dioxide and etching the doped silicon dioxide layer with phosphoric acid.

Abstract: Deep profile and highly doped impurity regions can be formed by diffusing from a solid source or doped silicon glass and using a patterned nitride layer. An oxide etch stop and polysilicon sacrificial layer are left in place in the patterned regions and the dopant is diffused through those layers. The polysilicon provides sacrificial silicon that serves to prevent the formation of boron silicon nitride on the substrate surface and also protects the oxide layer during etching of the silicon glass layer. The oxide layer then acts as an etch stop during removal of the polysilicon layer. In this way, no damage done to the substrate surface during the diffusion or subsequent etch steps and the need for expensive ion implanter steps is avoided.

Abstract: A method for removing a plurality of dielectric films from a supporting substrate by providing a substrate with a second dielectric layer overlying a first dielectric layer, contacting the substrate at a first temperature with a first acid solution exhibiting a positive etch selectivity at the first temperature, and then contacting the substrate at a second temperature with a second acid solution exhibiting a positive etch selectivity at the second temperature. The first and second dielectric layers exhibit different etch rates in the first and second acid solutions. The first and second acid solutions may contain phosphoric acid. The first dielectric layer may be silicon nitride and the second dielectric layer may be silicon oxide. Under these conditions, the first temperature may be about 175° C. and the second temperature may be about 155° C.

Abstract: On the sides of a gate electrode, layered-film sidewalls are formed which includes a first oxide film such as an NSG film or a TEOS film and a second oxide film such as a BPSG film or a PSG film. After the layered-film sidewalls are used as a mask for forming source and drain regions of a MIS transistor, the second oxide film of the sidewalls is selectively removed. At the removal, wet etching is performed with an aqueous solution containing hydrofluoric acid, and acetic acid or isopropyl alcohol. This makes etching selectivity between oxide films higher and removes only the upper second oxide film. As a result, in the formation of two types of oxide films which differ in their etching properties, the etching selectivity can be prevented from deteriorating.

Abstract: A method for avoiding erosion of a conductor structure during a procedure of removing etching residues is provided. The method provides a semiconductor structure and the conductor structure formed therein. A cap layer is formed on the conductor structure and the semiconductor and a dielectric layer formed thereon. The dielectric layer and the cap layer are then etched to partially expose the conductor structure. The etching residues are removed with an amine-containing solution and the amine-containing solution is removed with an intermediate solvent to avoid erosion of the exposed conductor structure. As a key step of the present invention, the intermediate solvent comprises N-methylpyrrolidone or isopropyl alcohol and can protect the conductor structure from erosion.

Abstract: The present invention is directed toward building a microelectronic device in which a semiconductor substrate has thereon an etch buffer layer used in a processing method in which the buffer layer will act as an etch uniformity aid. In a method of making the microelectronic device, a semiconductor substrate is covered with an etch buffer layer and with an insulative layer. A first etch is performed by patterning and etching through a mask. The first etch penetrates the insulative layer, forms a cavity therein, and is selective to the buffer layer so as to expose the buffer layer. A second etch is performed that is selective to the insulative layer and the semiconductor substrate, and is not selective to the buffer layer. The buffer layer can be an insulative material of a type other than the material of the insulative layer or the buffer layer can also be of a conductive material.

Abstract: Methods and devices for mechanical and/or chemical-mechanical planarization of semiconductor wafers, field emission displays and other microelectronic substrate assemblies. One method of planarizing a microelectronic substrate assembly in accordance with the invention includes pressing a substrate assembly against a planarizing surface of a polishing pad at a pad/substrate interface defined by a surface area of the substrate assembly contacting the planarizing surface. The method continues by moving the substrate assembly and/or the polishing pad with respect to the other to rub at least one of the substrate assembly and the planarizing surface against the other at a relative velocity. As the substrate assembly and polishing pad rub against each other, a parameter indicative of drag force between the substrate assembly and the polishing pad is measured or sensed at periodic intervals.

Abstract: A method is disclosed for forming an ultrathin oxide layer of uniform thickness. The method is particularly advantageous for producing uniformly thin interfacial oxides beneath materials of high dielectric permittivity, or uniformly thin passivation oxides. Hydrofluoric (HF) etching of a silicon surface, for example, is followed by termination of the silicon surface with ligands larger than H or F, particularly hydroxyl, alkoxy or carboxylic tails. The substrate is oxidized with the surface termination in place. The surface termination and relatively low temperatures moderate the rate of oxidation, such that a controllable thickness of oxide is formed. In some embodiments, the ligand termination is replaced with OH prior to further deposition. The deposition preferably includes alternating, self-limiting chemistries in an atomic layer deposition process, though any other suitable deposition process can be used.

Abstract: The present invention discloses a method of forming a slope lateral structure. In this invention, the silicon nitride and the silicon hydroxide with different etching rates are used. Thus, when the silicon nitride is etching, the top and laterals portion of the silicon hydroxide is suffering the slight etching. So that, when the silicon nitride is etched completely, a slope lateral silicon hydroxide is formed, because of the different etching time on the top and the bottom portion of the silicon hydroxide. Using the present invention, the conventional NROM process problem, which the wordlines are connected by the residue on the laterals of the protective layer after etching process can be solved.

Abstract: The present applicant has discovered that the application of an etch-rate reducing liquid that selectively wets the mask can permit anisotropic wet etching. In a preferred embodiment, the application of a hydrocarbon liquid film to a masked silica surface permits wet etching of straight silica walls without undercutting the mask. It is believed that the oil selectively wets the polymer mask, but not the silica surface. The oil will thus be selectively present at the point where the mask meets the silica. Since the HF etchant does not dissolve the oil, the etching produces straight walls instead of undercutting the mask.

Abstract: Under the first embodiment of the invention, back-end etching is applied to the specimen that needs to be inspected. Its surface is cleaned and mounted on a glass surface with the surface of the poly gate silicide that needs to be inspected being in contact with the surface of the glass. The exposed surface of the sample that is to be examined contains silicon, this silicon is removed. The gate oxide is then removed followed by the removal of the remaining poly of the gate structure. The second embodiment of the invention addresses poly gate inspection by enhanced (top surface of the gate electrode) gas etching of the gate electrode to remove gate oxide and silicon remains from the environment of the silicide. The specimen is etched back to the contact layer using a conventional Chemical Mechanical Polishing (CMP) process. The polished surface of the specimen is next exposed to XeF2, which selectively removes the oxide while the silicide remains in place.

Abstract: Methods for forming openings having predetermined shapes in a substrate and apparatuses with these openings. The methods may be used to form assemblies which include the substrate with its openings and elements which are disposed in the openings. In one example of a method, each of the elements include an electrical component and are assembled into one of the openings by a fluidic self assembly process. In an particular example of a method to create such an opening, the substrate is etched through a first patterned mask and is later etched through a second patterned mask. Typically, the second patterned mask is aligned relative to the opening created by etching through the first patterned mask and has an area of exposure which is smaller than an area of exposure through the first patterned mask.