Abstract: A method for fabricating funnel-shaped vias in semiconductor devices with an improved profile amelioration of the sharp angles at the onset of the via and at the intersection between the wet etch section (i.e., the bowl-shaped section) and the dry etch section (i.e., the straight section).

Abstract: A trench (110) for isolation is formed in a substrate (102) through an opening in a nitride masking layer (106). After the trench is formed, the opening in the nitride masking layer is widened uniformly by an isotropic etch (FIG. 8). This leaves the nitride masking layer uniformly recessed from the edge of the trench. The trench is then filled with oxide and, with CMP, is etched back so that there is a nearly planar surface with oxide (114b) extending outside the trench wall along the surface and abutting the recessed nitride masking layer (106). The nitride masking layer is then removed so that there is left an oxide overlap portion (114b) which extends outside the trench wall. Subsequent oxide etches which are required for formation of transistors etch the oxide overlap portion instead of etching down into the oxide along the sidewall of the trench whereby an improved device is formed.

Abstract: A method of manufacturing a semiconductor device comprises the steps of forming a first film over a semicondutor substrate, introducing a reaction gas including a dilution gas into a reaction atmosphere and then growing a antireflection film made of silicon nitride or silicon nitride oxide on the first film by a plasma chemical vapor deposition method in the reaction atmosphere, coating resist on the antireflection film directly or via a second film and then patterning the resist via exposure and development, patterning the first film located in an area not covered with the resist by etching, and removing the antireflection film by use of hydrofluoric acid after patterning of the first film, whereby expansion of impurity diffusion can be prevented and also retreat of sidewalls can be suppressed.

Abstract: The present invention is directed to a method of forming conductive interconnections in an integrated circuit device. In one embodiment, the method comprises forming a dielectric stack comprised of multiple layers, and determining a thickness ratio of the layers of the stack. The method further comprises determining an etching process to be performed on the dielectric stack to define an opening for a conductive interconnection based upon the determined thickness ration, and performing the determined etch process on the dielectric stack.

Abstract: A method for fabricating and patterning semiconductor devices with a resolution down to 0.12 &mgr;m on a substrate structure. The method begins by providing a substrate structure comprising various layers of oxide and/or nitride formed over either monocrystalline silicon or polycrystalline silicon. A silicon oxynitride layer is formed on the substrate structure. Key characteristics of the oxynitride layer include: a refractive index of between about 1.85 and 2.35 at a wavelength of 248 nm, an extinction coefficient of between 0.45 and 0.75 at a wavelength of 248 nm, and a thickness of between about 130 Angstroms and 850 Angstroms. A photoresist layer is formed over the silicon oxynitride layer and exposed at a wavelength of between about 245 nm and 250 nm; whereby during exposure at a wavelength of between 245 nm 250 nm, the silicon oxynitride layer provides a phase-cancel effect.

Abstract: A process for forming a SAC opening, in a composite insulator layer, to expose an active device region in a semiconductor substrate, has been developed. The process features a RIE procedure, used to selectively define a first portion of the SAC opening, in a thick silicon oxide layer, with the RIE procedure terminating at the appearance of a polymer material, formed on the surface of an underlying, thin silicon nitride stop layer, at the conclusion of thick silicon oxide, dry etching procedure. A critical wet etch procedure, performed in a dilute hydrofluoric acid solution, is then employed to remove the polymer material, allowing selective removal of the thin silicon nitride stop layer to be accomplished, resulting in the desired SAC opening.

Abstract: In one aspect, the invention encompasses a semiconductor processing method. A layer of material is provided over a substrate and reacted in a solution to remove at least some of the material. The reacting comprises a reaction chemistry that alters a concentration of a species in the solution. An absorbance of the solution is monitored for at least one wavelength of light that the species absorbs, and a concentration of the species in the solution is monitored by the monitoring of the absorbance. The concentration of the species in the solution is adjusted utilizing information obtained from the absorbance monitoring. In another aspect, the invention encompasses a semiconductor processing method wherein a layer of material is provided over a substrate and reacted with a solution to remove at least some of the material. The reaction consumes a component of the solution, and an absorbance of the solution is monitored for at least one wavelength of light that the consumed component absorbs.

Abstract: A semiconductor device includes a F-doped interlayer insulation film and a high-refractive index insulation film having a refractive index higher than a refractive index of the F-doped interlayer insulation film, such that the high-refractive index insulation film is disposed at least one of a top side and a bottom side of the F-doped interlayer insulation film.

Abstract: A method of polishing selected ceramics and metals is provided wherein the selected ceramic or metal material is rubbed against a solid surface in the presence of a nonabrasive liquid medium which only attacks the selected ceramic or metal material under friction. Examples of materials for the tribochemical polishing process includes ceramics such as silicon, silicon nitride, silicon carbide, silicon oxide, titanium carbide and aluminum nitride and metals such as tungsten. Both ceramic and metal surfaces can be polished, as in a damascene structure of an integrated circuit.

Abstract: A new method of forming metal interconnects with air gaps between adjacent interconnects in the manufacture of an integrated circuit device is achieved. A semiconductor substrate is provided. The metal interconnects are formed overlying the semiconductor substrate. A silicon nitride liner layer is deposited. A gap filling oxide layer is deposited to fill gaps between adjacent metal interconnects. The gap filling oxide layer is polished down to the silicon nitride liner layer. A silicon nitride thin layer is deposited. The silicon nitride thin layer is patterned using an oversized, reverse mask of the metal interconnects. The patterning of the silicon nitride thin layer creates openings to thereby expose a portion of the gap filling oxide. The gap filling oxide layer is etched away. A self-sealing oxide layer is deposited overlying the silicon nitride thin layer and the silicon nitride liner layer.

Abstract: A method for forming shallow trench isolations includes the steps of defining a wafer substrate, forming a silicon dioxide insulating layer on the substrate, depositing a silicon nitride layer on the silicon dioxide insulating layer, and forming at least one trench in the substrate through the silicon dioxide and silicon nitride layers. The method also includes the steps of depositing a silicon dioxide layer over the silicon nitride layer and in the trench, removing the silicon dioxide layer deposited over the silicon nitride layer, anisotropically etching the silicon dioxide layer to produce silicon dioxide sidewalls in the trench contiguous with the silicon nitride layer, isotropically etching to remove the sidewalls and removing the silicon nitride layer.

Abstract: A method is provided for polishing a composite comprised of silica and silicon nitride wherein a polishing composition is used comprising: an aqueous medium, abrasive particles, a surfactant, an organic polymer viscosity modifier which increases the viscosity of the composition, and a compound which complexes with the silica and silicon nitride wherein the complexing agent has two or more functional groups each having a dissociable proton, the functional groups being the same or different.

Abstract: A method for forming the gate electrode in an integrated circuit, in which a cap silicon nitride layer is deposited in a two step process to improve the condition of silicon nitride residue remaining on the surface of tungsten silicide. First, a layer of polysilicon and a layer of tungsten silicide are sequentially formed on the semiconductor substrate, subsequently, a thin film of silicon nitride is formed at a first temperature and a second silicon nitride is formed at a second temperature, then the pattern of the contact window of gate is defined and the first etching is performed to remove the second and the second silicon nitride, finally, the second etching is performed to remove the layers of polysilicon and tungsten silicide to form a gate electrode.

Abstract: In accordance with the objectives of the invention a new method of forming air gaps between adjacent conducting lines of a semiconductor circuit is achieved. A pattern of metal lines is deposited over an insulating layer. A layer of oxynitride (SiON) is deposited over the pattern of metal lines and the exposed surface of the insulating layer. PECVD oxide is deposited over the layer of oxynitride; the PECVD oxide is removed down to the top surface of the layer of oxynitride overlying the metal pattern. A layer of SOON is deposited over the surface of the polished oxynitride and the polished PECVD oxide. A trench is etched between the conducting line pattern through the layer of SOON and into the PECVD oxide. The profile of this trench is aggressively expanded converting the trench profile from a rectangular profile into an arch-shaped profile. The top region of the arch-shaped profile is closed off by depositing a layer of dielectric over the surface of the layer of SOON.

Abstract: The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of etching inorganic antireflective layers without etching excessive amounts of an underlying oxide.

Abstract: In a method for preparing a semiconductor device wherein a first silicon oxide film, a second silicon oxide film and a silicon nitride film are sequentially deposited on a silicon substrate, and both silicon oxide films and the silicon nitride film are patterned, a patterned resist 45 is formed on the silicon nitride film, the silicon nitride film is etched with phosphoric acid the resist serving as a mask, and both silicon oxide films are etched with hydrofluoric acid the resist serving as a mask.

Abstract: Methods, apparatuses and substrate assembly structures for mechanical and chemical-mechanical planarizing processes used in the manufacturing microelectronic-device substrate assemblies. One aspect of the invention is directed toward a method for planarizing a microelectronic-device substrate assembly by removing material from a surface of the substrate assembly, detecting a first change in drag force between the substrate assembly and a polishing pad indicating that the substrate surface is planar, and identifying a second change in drag force between the substrate assembly and the polishing pad indicating that the planar substrate surface is at the endpoint elevation. After the second change in drag force is identified, the planarization process is stopped.

Abstract: A method of pad etch which removes an anti-reflective coating over a conductor in an integrated circuit is disclosed herein. The method includes providing a mask layer, stabilizing the mask layer, and providing a high temperature etch to remove the anti-reflective coating.

Abstract: The use of silicon oxynitride (SiOxNy) as a sacrificial material for forming a microelectromechanical (MEM) device is disclosed. Whereas conventional sacrificial materials such as silicon dioxide and silicate glasses are compressively strained, the composition of silicon oxynitride can be selected to be either tensile-strained or substantially-stress-free. Thus, silicon oxynitride can be used in combination with conventional sacrificial materials to limit an accumulation of compressive stress in a MEM device; or alternately the MEM device can be formed entirely with silicon oxynitride.

Abstract: A process for etching a gate conductor material in the fabrication of MOS transistors is presented. A hard mask layer composed of silicon oxynitride is formed upon a gate conductor layer. The hard mask layer is preferably patterned using a resin layer. The patterned hard mask layer is preferably used to form a patterned gate conductor. The gate conductor is preferably composed of polycrystalline silicon or a silicon-germanium alloy.

Abstract: The invention relates to an aqueous phosphoric acid etch bath composition with a readily soluble silicon containing composition. The baths are used in the etching step of composite semiconductor device manufacturing.

Abstract: Disclosed is a method for fabricating reliable interconnect structures on a semiconductor substrate that has at least a first dielectric layer, a first patterned metallization layer, a second dielectric layer over the first patterned metallization layer, and a plurality of tungsten plugs formed in the second dielectric layer. The method includes patterning a second metallization layer that overlies the second dielectric layer and the plurality of tungsten plugs, such that the patterning leaves at least one of the plurality of tungsten plugs not completely covered by the second metallization layer. Submersing the semiconductor substrate into a dilute nitric acid solution until a passivating tungsten oxide is formed over a portion of the at least one of the plurality of tungsten plugs that is not completely covered by the second metallization layer.

Abstract: A method for removing a plurality of dielectric films from a supporting substrate by providing a substrate with a second dielectric layer overlying a first dielectric layer, contacting the substrate at a first temperature with a first acid solution exhibiting a positive etch selectivity at the first temperature, and then contacting the substrate at a second temperature with a second acid solution exhibiting a positive etch selectivity at the second temperature. The first and second dielectric layers exhibit different etch rates in the first and second acid solutions. The first and second acid solutions may contain phosphoric acid. The first dielectric layer may be silicon nitride and the second dielectric layer may be silicon oxide. Under these conditions, the first temperature may be about 175.degree. C. and the second temperature may be about 155.degree. C.

Abstract: The present invention provides a wet etching method applied to a thin, including the steps of (a) setting in advance an etching rate of said thin film in view of a kind of the thin film to be etched, components of said etchant solution, and temperature, (b) loading the substrate on a spin chuck such that the surface having the thin film formed thereon faces upward and, (c) detecting a thickness of the thin film in at least a peripheral portion and a central portion of the substrate.

Abstract: A masking process for forming first and second ion-doped regions on a substrate of a semiconductor device. An oxide layer and a first nitride layer are formed on the substrate in order. The first nitride layer is etched using a photolithography process to form a first predetermined pattern which exposes portions of the oxide layer. The exposed portions of the oxide layer are then etched using the first predetermined pattern as an etching mask, until portions of the substrate corresponding to the first ion-doped regions are exposed. Next, first ions are doped into the exposed portions of the substrate using the first predetermined pattern as a doping mask. The first predetermined pattern is removed. A second nitride layer is then formed over the substrate and the patterned oxide layer. Portions of the second nitride layer are removed to reveal the top of the patterned oxide layer, forming a second predetermined pattern on the substrate.

Abstract: An improved wet etchant process is provided which has greater selectivity than existing hot phosphoric acid etching processes and which maintains a high etch rate in use. The etchant composition includes a second acid having a boiling point higher than that of the phosphoric acid.

Abstract: The formation and/or growth of dendrites emanating from Cu or Cu alloy lines into a bordering open dielectric field are prevented or substantially reduced by chemically removing a portion of the surface from the dielectric field and from between the lines after CMP. Embodiments include removing up to 20 .ANG. of silicon oxide by buffing with a solution containing ammonium fluoride, diammonium hydrogen citrate, triammonium citrate, a surfactant and de-ionized water.

Abstract: A method of fabrication of a metal lines without dishing using damascene and chemical-mechanical polish processes. A Key feature is the hard cap layer that is only formed over the trench opening. The hard cap layer prevents dishing of the metal line and also allows faster CMP than blanket polish stop layers. The method includes forming a first dielectric layer having a first trench opening over a semiconductor structure. A metal layer is deposited in the first trench opening. The metal layer has a dimple. The metal layer is preferably composed of Al or Cu. A hard mask is formed having a first opening over the first trench opening. The first opening is at least partially over first trench opening. A hard cap layer (e.g., W or WSi.sub.x) is selectively deposited on the metal layer exposed in the first opening. The hard cap layer, the hard mask, and the metal layer are chemical-mechanical polished to completely remove the hard mask resulting in a metal line having a "dishing free" flat top surface.

Abstract: A method of forming an isolation region of a semiconductor device, includes the steps of forming a first insulating film on a substrate; defining a plurality of isolation regions on the first insulating film; removing portions of the first insulating film in the isolation regions to expose portions of the substrate; selectively removing the exposed portions of the substrate to form at least one trench; forming a second insulating film in the at least one trench and on portions of the first insulating film; and removing the first insulating film so as to remove the second insulating film formed thereon.

Abstract: Silicon nitride is etched employing a composition containing a fluoride containing compound, certain organic solvents, and water.

Abstract: The invention encompasses methods of forming capacitors, methods of forming silicon nitride layers on silicon-comprising substrates, methods for densifying silicon nitride layers, methods for forming capacitors, and capacitors. In one aspect, the invention includes a method of densifying a silicon nitride layer comprising subjecting a silicon nitride layer to a nitrogen-comprising ambient atmosphere having at least about two atmospheres of pressure. In another aspect, the invention includes a method of forming a capacitor comprising: a) forming a first capacitor plate, the first capacitor plate comprising silicon and having a surface; b) forming a dielectric layer proximate the first capacitor plate, the dielectric layer comprising a silicon nitride layer and being formed by exposing the first capacitor plate surface to a nitrogen-comprising ambient atmosphere having at least about two atmospheres of pressure; and c) forming a second capacitor plate proximate the dielectric layer.

Abstract: A method for forming an isolating layer in a semiconductor device including the steps of sequentially forming a buffer oxide layer, a CVD oxide layer and a first nitride layer on a semiconductor substrate, selectively removing the first nitride layer, selectively exposing a surface of the semiconductor substrate using the first nitride layer as a mask, forming and planarizing a second nitride layer on the selectively exposed surface of the semiconductor substrate, removing the CVD oxide layer and buffer oxide layer using the second nitride layer as a mask, while leaving a nitride pattern layer which becomes wider in an upward direction, forming oxide sidewalls at sides of the nitride pattern layer, forming a trench having a slope by selectively etching the semiconductor substrate using the oxide sidewalls as a mask, depositing a filling insulating material layer on the nitride pattern layer, the oxide sidewalls and in the trench, planarizing the filling insulating material layer until a surface of the nitride

Abstract: A fabricating method for a dynamic random access memory capacitor includes the following steps. A cap layer and a spacer are formed on the gate to protect the gate from being etched. A self-aligned contact hole is formed and then the self-aligned contact hole is etched again to form a contact node opening. In this way, the difficulty of forming the contact node opening can be reduced. The method of forming the storage electrode includes forming and patterning a stacked layer, which is formed by several conductive layers and isolation layers interlaced with each other, to form the self-aligned contact hole. A conductive spacer is formed on the sidewall of the stacked layer. The conductive spacer is used as a mask to etch the dielectric layer below the bit line so as to form a contact node opening. The contact opening exposes a source/drain region. A conductive layer is formed to fill the contact node opening. The conductive layer and the staked layer are patterned.

Abstract: The present invention intends to form multilayer interconnects without deteriorating the advantage of an organosiloxane film (an interlayer dielectric), i.e., the low dielectric constant. According to the present invention, an organosiloxane film, a silicon nitride film, an inorganic SOG film, and a photoresist pattern are formed on a first metal layer, in series. The inorganic SOG film is then etched with use of the photoresist pattern as a mask to transfer the photoresist pattern to the inorganic SOG film. The photoresist pattern is then removed by oxygen plasma treatment with use of the silicon nitride film as a protection mask for protecting the organosiloxane film. Subsequently thereto, the silicon nitride film and the organosiloxane film are etched with use of the inorganic SOG film to form a contact hole reaching the first metal layer. After removing the inorganic SOG film, a second metal layer is formed to contact with the first metal layer through the contact hole.

Abstract: Aqueous compositions for etching silicon nitride films present on wafers used in microelectronic devices comprise hydrogen fluoride and phosphate. Methods for etching silicon nitride films present in wafers to be used in microelectronic devices comprise exposing the wafers to the aqueous compositions.

Abstract: Etching residue, etching mask and silicon nitride and/or silicon dioxide are etched or removed employing a composition containing a fluoride containing compound, water and certain organic solvents.

Abstract: A process for producing an electronic device having a silicon nitride film on a substrate is provided which comprises steps of forming a silicon nitride film and a silicon oxide film on a first face and a second face reverse to the first face of the substrate respectively, removing the silicon oxide film on the first face by wet etching, removing the silicon nitride film on the first face by wet etching, and removing the silicon oxide film on the second face by wet etching.

Abstract: This invention is a process for manufacturing a random access memory array. Each memory cell within the array which results from the process incorporates a stacked capacitor, a silicon nitride coated access transistor gate electrode, and a self-aligned high-aspect-ratio digit line contact having a tungsten plug which extends from the substrate to a metal interconnect structure located at a level above the stacked capacitor. The contact opening is lined with titanium metal which is in contact with the substrate, and with titanium nitride that is in contact with the plug. Both the titanium metal and the titanium nitride are deposited via chemical vapor deposition reactions.

Abstract: The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of etching inorganic antireflective layers without etching excessive amounts of an underlying oxide. According to one aspect of the present invention, the antireflective layer is selectively etched using an etchant which comprises about 35-40 wt. % NH.sub.4 F and about 0.9-5.0 wt. % H.sub.3 PO.sub.4 in an aqueous solution.

Abstract: Silicon nitride is etched employing a composition containing a fluoride containing compound, certain organic solvents, and water.

Abstract: A method of fabricating a semiconductor device includes the steps of sequentially forming a gate oxide layer, a gate material layer and a cap insulating layer on a semiconductor substrate, selectively etching them to form a gate, sequentially forming a plurality of material layers on the overall surface of the semiconductor substrate including the gate, etching them back to form a gate sidewall spacer out of the plurality of material layers, and selectively removing the plurality of material layers forming the gate sidewall spacer to form gate sidewall spacers having lengths different from each other, the lengths depending on a particular region of the substrate.

Abstract: The invention relates to integrated circuits and to methods of forming self-aligned silicidation structures. In an exemplary embodiment, a first insulating layer is formed on the surface of a semiconductor substrate which includes an electrode. A second insulating layer is formed over the first insulating layer and a photoresist pattern is formed over a silicide exclusion area. Exposed portions of the first and second insulating layers are removed by one or more etching steps, wherein an etchant used to remove the exposed portions of the second insulating layer has a higher selectivity for the second insulating layer than for the first insulating layer. A silicide layer can then be formed over the surface of the semiconductor substrate except for silicide exclusion areas. Modification of the profiles of features underlying the first insulating layer, such as sidewall spacer and field oxides can thereby be prevented.

Abstract: A semiconductor device is fabricated by the step of forming a gate insulation film of a GaS film on a compound semiconductor layer; the step of forming an inter-layer insulation film on the gate insulation film; the step of etching the inter-layer insulation film selectively with respect to the gate insulation film by the use of an etchant containing hydrogen fluoride and ammonium fluoride, the step of exposing a prescribed region of the gate insulation film; and the step of forming a gate electrode on the exposed gate insulation film.

Abstract: A method of fabricating a transistor. A dielectric layer is formed on an upper surface of a semiconductor substrate. A photoresist layer is then deposited on a dielectric layer and patterned with a photolithography exposure device to expose a region of the dielectric layer having a lateral dimension approximately equal to the minimum feature size resolvable by the photolithography exposure device. The exposed region of the dielectric layer is then removed to form a trench in the dielectric layer having opposed dielectric sidewalls and to expose a channel region of the semiconductor substrate having a lateral dimension approximately equal to the minimum feature size. First and second spacer structures are then formed on the respective dielectric sidewalls. The spacer structures shadow peripheral portions of the exposed channel region. A channel dielectric is then formed between the first and second spacer structures.

Abstract: Methods of wet etching through a silicon substrate using composite etch-stop layers are disclosed. In one embodiment, the composite etch stop comprises a layer of silicon dioxide and a layer of polyimide.

Abstract: An improved wet etchant process is provided which has greater selectivity than existing hot phosphoric acid etching processes and which maintains a high etch rate in use. The etchant composition includes a second acid having a boiling point higher than that of the phosphoric acid.

Abstract: Trench structures (12,32,35,46) are formed in single crystal silicon substrates (10,30) that have either a (110) or (112) orientation. A selective wet etch solution is used that removes only the exposed portions of the single crystal silicon substrates (10,30) that are in the (110) or (112) crystal planes. The trench structures (12,32,35,46) are defined by the {111} crystal planes in the single crystal silicon substrate (10,30) that are exposed during the selective wet etch process. Trench structures (32,35) can be formed on both sides of a single crystal silicon substrate (30) to form an opening (34). Opening (34) can be used as an alignment mark to align front side processing to backside and vice versa. Trench structures can also be use to form a microstructure (41,61) for a sensor (40,60).

Abstract: A method of forming silicon nitride includes, a) forming a first layer comprising silicon nitride over a substrate; b) forming a second layer comprising silicon on the first layer; and c) nitridizing silicon of the second layer into silicon nitride to form a silicon nitride comprising layer, said silicon nitride comprising layer comprising silicon nitride of the first and second layers. Further, a method of forming a capacitor dielectric layer of silicon nitride includes, a) forming a first capacitor plate layer; b) forming a first silicon nitride layer over the first capacitor plate layer; c) forming a silicon layer on the silicon nitride layer; d) nitridizing the silicon layer into a second silicon nitride layer; and e) forming a second capacitor plate layer over the second silicon nitride layer.

Abstract: A manufacturing method of fabricating a polysilicon conductive wire suitable for an integrated circuit and which can avoid pattern transfer errors caused by reflection of ultraviolet light during photolithographic processing and that results in constriction in width or the bottlenecking effect in part of the conductive wore. A polysilicon layer is formed above a semiconductor substrate having a preformed device. A cap insulting layer is formed above the polysilicon layer. A micro-roughness structure is formed on the surface of the cap insulating layer. A photoresist layer is coated over the micro-roughened surface of the cap insulating layer. A pattern is transferred onto the photoresist layer by selective light exposure followed by the removal of unexposed photoresist. Then the cap insulating layer and the polysilicon layer are etched in sequence in regions not covered by photoresist. The residual photoresist is then removed to leave behind a polysilicon conductive wire.

Abstract: A process is described for forming a heavily doped buried element below an active device region of a silicon wafer without the use of costly epitaxial layers and without incurring ion implantation damage within active device regions. The method is particularly applicable to active device regions which have small lateral dimensions. Thus, the technological trend towards shrinking devices favors the incorporation of the process of the invention. The process utilizes a silicon nitride hardmask to define a narrow band around the perimeter of the device active area. A deep implant is performed through this mask, placing a ring of dopant below and outside the active area. The silicon nitride hardmask is then patterned a second time to define the conventional field oxide isolation regions. The LOCOS field oxidation is then performed whereby the implanted dopant diffuses vertically, engaging the field oxide around the perimeter of the device region and laterally filling in the region under the device active area.