Silicon Nitride Patents (Class 438/757)
  • Patent number: 5843850
    Abstract: A method of stripping a nitride layer from a wafer includes the steps of putting the wafer into a process bath containing a stripping solution, passing the stripping solution from the process bath through a filter to remove the nitride particles contained therein, heating the filtered stripping solution through an in-line electrical heater with two heating parts connected in parallel to allow the stripping solution to quickly return to the proper etching temperature, and returning the temperature recovered stripping solution to the process bath. The filtered stripping solution is branched through the parallel heating parts to enable it to be quickly heated. The stripping solution may be a phosphoric acid solution, whose proper etching temperature is about 163.degree. C. The in-line heater consists of at least two heating parts connected in parallel, each with an electrical capacity of 6 KW.
    Type: Grant
    Filed: October 23, 1996
    Date of Patent: December 1, 1998
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Min Shin, Seung-Ho Jun, Se-Jong Ko, Tae-Juon Kim
  • Patent number: 5821170
    Abstract: A method for etching aluminum containing layers. A layer (13) of aluminum nitride is formed on a semiconductor substrate (11). The layer (13) of aluminum nitride is etched using a dilute ammonium hydroxide solution that is diluted with water such that the ammonium hydroxide solution has one part of ammonium hydroxide to at least fifteen parts of water. The dilute ammonium hydroxide solution is showered onto the semiconductor substrate and forms an aluminum hydroxide layer. The aluminum hydroxide layer is dissolved by excess water in the dilute aluminum hydroxide solution and rinsed from the semiconductor substrate (11).
    Type: Grant
    Filed: September 30, 1996
    Date of Patent: October 13, 1998
    Assignee: Motorola, Inc.
    Inventors: Lawrence S. Klingbeil, Jr., Terry K. Daly
  • Patent number: 5795830
    Abstract: A method of forming sub-lithographic elements and spaces therebetween where the pitch may be reduced with continuously adjustable line and space dimensions, and a structure resulting from the method, are disclosed. A plurality of spaced convertible members are formed on a substrate. A portion of each member is then converted, thereby reducing the dimensions of the unconverted portion of the member while increasing the width of the member plus its converted layer. A conformal layer of material is then deposited over the converted members, followed by directional etching of the conformal layer. The unconverted portion of the member is then removed. The line and space dimensions can be continuously adjusted by altering either or both of the member's converted layer and conformal layer.
    Type: Grant
    Filed: July 26, 1996
    Date of Patent: August 18, 1998
    Assignee: International Business Machines Corporation
    Inventors: John E. Cronin, Carter W. Kaanta
  • Patent number: 5731235
    Abstract: A method of forming silicon nitride includes, a) forming a first layer comprising silicon nitride over a substrate; b) forming a second layer comprising silicon on the first layer; and c) nitridizing silicon of the second layer into silicon nitride to form a silicon nitride comprising layer, the silicon nitride comprising layer comprising silicon nitride of the first and second layers. Further, a method of forming a capacitor dielectric layer of silicon nitride includes, a) forming a first capacitor plate layer; b) forming a first silicon nitride layer over the first capacitor plate layer; c) forming a silicon layer on the silicon nitride layer; d) nitridizing the silicon layer into a second silicon nitride layer; and e) forming a second capacitor plate layer over the second silicon nitride layer.
    Type: Grant
    Filed: October 30, 1996
    Date of Patent: March 24, 1998
    Assignee: Micron Technology, Inc.
    Inventors: Anand Srinivasan, Sujit Sharan, Gurtej S. Sandhu
  • Patent number: 5723384
    Abstract: There is provided a method for manufacturing a capacitor in a semiconductor device including the steps of forming first and second insulating layers with a first contact hole through to a semiconductor substrate, patterning a first conductive layer to form a pedestal portion of a lower electrode, using a patterned third insulating layer selectively forming an upper portion of the lower electrode from a tungsten nitride thin film, and forming an undercut beneath the pedestal portion by wet-etching the second insulating layer.
    Type: Grant
    Filed: September 13, 1996
    Date of Patent: March 3, 1998
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-lyul Park, Jung-min Ha, Dae-hong Ko, Sang-in Lee