Abstract: Semiconductor devices, methods of manufacture thereof, and IMD structures are disclosed. In some embodiments, a semiconductor device includes an adhesion layer disposed over a workpiece. The adhesion layer has a dielectric constant of about 4.0 or less and includes a substantially homogeneous material. An insulating material layer is disposed over the adhesion layer. The insulating material layer has a dielectric constant of about 2.6 or less. The adhesion layer and the insulating material layer comprise an IMD structure.

Abstract: Disclosed herein are methods of doping a patterned substrate in a reaction chamber. The methods may include forming a first conformal film layer which has a dopant source including a dopant, and driving some of the dopant into the substrate to form a conformal doping profile. In some embodiments, forming the first film layer may include introducing a dopant precursor into the reaction chamber, adsorbing the dopant precursor under conditions whereby it forms an adsorption-limited layer, and reacting the adsorbed dopant precursor to form the dopant source. Also disclosed herein are apparatuses for doping a substrate which may include a reaction chamber, a gas inlet, and a controller having machine readable code including instructions for operating the gas inlet to introduce dopant precursor into the reaction chamber so that it is adsorbed, and instructions for reacting the adsorbed dopant precursor to form a film layer containing a dopant source.

Abstract: An electrically conductive multilayer stack including a first metal oxide layer including titanium oxide, a metal layer on the first metal oxide layer, and a second metal oxide layer including titanium oxide on the metal layer, at least one of the first metal oxide layer and the second metal oxide layer including a first region, a second region on the first region, and a third region on the second region, the first region and the third region each having a higher oxygen concentration than that of the second region is disclosed. Methods of manufacturing an electrically conductive multilayer stack are also disclosed.

Abstract: Embodiments related to metal oxide protective layers formed on a surface of a halogen-sensitive metal-including layer present on a substrate processed in a semiconductor processing reactor are provided. In one example, a method for forming a metal oxide protective layer is provided. The example method includes forming a metal-including active species on the halogen-sensitive metal-including layer, the metal-including active species being derived from a non-halogenated metal oxide precursor. The example method also includes reacting an oxygen-containing reactant with the metal-including active species to form the metal oxide protective layer.

Abstract: Methods for depositing a material, such as a metal or a transition metal oxide, using an ALD (atomic layer deposition) process and resulting structures are disclosed. Such methods include treating a surface of a semiconductor structure periodically throughout the ALD process to regenerate a blocking material or to coat a blocking material that enables selective deposition of the material on a surface of a substrate. The surface treatment may reactivate a surface of the substrate toward the blocking material, may restore the blocking material after degradation occurs during the ALD process, and/or may coat the blocking material to prevent further degradation during the ALD process. For example, the surface treatment may be applied after performing one or more ALD cycles. Accordingly, the presently disclosed methods enable in situ restoration of blocking materials in ALD process that are generally incompatible with the blocking material and also enables selective deposition in recessed structures.

Abstract: Method for crystal growth from a surfactant of a metal-nonmetal (MN) compound, including the procedures of providing a seed crystal, introducing atoms of a first metal to the seed crystal thus forming a thin liquid metal wetting layer on a surface of the seed crystal, setting a temperature of the seed crystal below a minimal temperature required for dissolving MN molecules in the wetting layer and above a melting point of the first metal, each one of the MN molecules being formed from an atom of a second metal and an atom of a first nonmetal, introducing the MN molecules which form an MN surfactant monolayer, thereby facilitating a formation of the wetting layer between the MN surfactant monolayer and the surface of the seed crystal, and regulating a thickness of the wetting layer, thereby growing an epitaxial layer of the MN compound on the seed crystal.

Abstract: A semiconductor device is provided that includes a diffusion barrier layer between a compound semiconductor layer and a dielectric layer, as well as a method of fabricating the semiconductor device, such that the semiconductor device includes a compound semiconductor layer; a dielectric layer; and a diffusion barrier layer including an oxynitride formed between the compound semiconductor layer and the dielectric layer.

Abstract: There is provided a method of cleaning an inside of a process chamber, which is formed by a reaction tube and a manifold configured to support the reaction tube and installed under a heater, after forming a stacked film of oxide and nitride films on a substrate in the process chamber by alternately performing forming the oxide film on the substrate and forming the nitride film thereon. The method includes supplying a hydrogen-free fluorine-based gas from a first nozzle, which is installed in the manifold to extend upward from the manifold to an inside of the reaction tube, to an inner wall of the reaction tube; and supplying a hydrogen fluoride gas from a second nozzle, which is installed in the manifold, to an inner wall of the manifold.

Abstract: Methods of forming fine patterns are provided. The method includes reinforcing a hydrophobic property of a hard mask layer using a surface treatment process to form a neutral layer, forming a block co-polymer layer on the neutral layer, and phase-separating the block co-polymer layer into first domains and second domains.

Abstract: A semiconductor device manufacturing method that includes: forming a gate insulating film containing a hafnium oxide and a zirconium oxide on a workpiece having a source, a drain and a channel; and subjecting the gate insulating film to a crystallization heat treatment at a temperature of 600 degrees C. or less is provided. The gate insulating film subjected to the crystallization heat treatment has a relative permittivity of 27 or more.

Abstract: A non-volatile semiconductor memory free from adverse effects due to process charge is provided. The non-volatile semiconductor memory includes: a silicon substrate; a first silicon oxide film; a second silicon oxide film; a first silicon nitride film; and a second silicon nitride film, wherein the first silicon oxide film is layered on the silicon substrate, the first silicon nitride film is layered on the first silicon oxide film, the second silicon oxide film is layered on the first silicon nitride film, and the second silicon nitride film is layered to have a first part that is in contact with the first silicon nitride film and a second part that is in contact with the silicon substrate.

Abstract: Provided are methods for depositing a cerium doped hafnium containing high-k dielectric film on a substrate. The reagents of specific methods include hafnium tetrachloride, an organometallic complex of cerium and water.

Abstract: Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.

Abstract: Among other things, one or more wafer edge protection structures and techniques for forming such wafer edge protection structures are provided. A substrate of a semiconductor wafer comprises an edge, such as a beveled wafer edge portion, that is susceptible to Epi growth which results in undesirable particle contamination of the semiconductor wafer. Accordingly, a wafer edge protection structure is formed over the beveled wafer edge portion. The wafer edge protection structure comprises an Epi growth resistant material, such as an amorphous material, a non-crystalline material, oxide, or other material. In this way, the wafer edge protection structure mitigates Epi growth on the beveled wafer edge portion, where the Epi growth increases a likelihood of particle contamination from cracking or peeling of an Epi film resulting from the Epi growth. The wafer edge protection structure thus mitigates at least some contamination of the wafer.

Abstract: The present disclosure relates to spin-on compositions containing at least one metal oxide dicarboxylate and an organic solvent into which the metal oxide dicarboxylate is soluble or colloidally stable. The dicarboxylate is capable of decomposing during heat treatment to give a cured metal oxide film. The present disclosure also relates to method of using the spin-on compositions.

Abstract: A method of producing a patterned inorganic thin film element includes providing a substrate. A thin layer of polymeric inhibitor is uniformly depositing on the substrate. A patterned mask having open areas is provided on the thin layer of polymeric inhibitor. The thin layer of polymeric inhibitor is patterned by removing inhibitor from areas exposed by the open areas of the patterned mask using a highly reactive oxygen process. An inorganic thin film layer is deposited on the substrate in the areas exposed by the removal of the thin layer of polymeric inhibitor using an atomic layer deposition process.

Abstract: A method of producing a patterned inorganic thin film element includes providing a substrate. A thin layer of polymeric inhibitor is uniformly depositing on the substrate. A patterned mask having open areas is provided on the thin layer of polymeric inhibitor. The thin layer of polymeric inhibitor is patterned by removing inhibitor from areas exposed by the open areas of the patterned mask using a highly reactive oxygen process. An inorganic thin film layer is deposited on the substrate in the areas exposed by the removal of the thin layer of polymeric inhibitor using an atomic layer deposition process.

Abstract: A method of making a lithography mask with a stress-relief treatment is disclosed. The method includes providing a substrate and depositing an opaque layer on the substrate. The opaque layer is patterned to form a patterned mask. A stress-relief treatment is applied to the patterned mask by using an radiation exposure.

Abstract: The surface recombination velocity of a silicon sample is reduced by deposition of a thin hydrogenated amorphous silicon or hydrogenated amorphous silicon carbide film, followed by deposition of a thin hydrogenated silicon nitride film. The surface recombination velocity is further decreased by a subsequent anneal. Silicon solar cell structures using this new method for efficient reduction of the surface recombination velocity is claimed.

Abstract: A semiconductor/dielectric interface having reduced interface trap density and a method of manufacturing the interface are disclosed. In an exemplary embodiment, the method of forming a semiconductor device includes receiving a substrate and forming a termination layer on a top surface of the substrate. The termination layer includes at least one of hydrogen, deuterium, or nitrogen. The method further includes depositing a dielectric layer on the termination layer such that the depositing of the dielectric layer does not disrupt the termination layer. The termination layer may be formed by a first deposition process that deposits a first material of the termination layer and a subsequent deposition process that introduces a second material of the termination layer into the first material. The termination layer may also be formed by a single deposition process that deposits both a first material and a second material of the termination layer.

Abstract: A plating bath for electroless deposition of gold and gold alloy layers on such silicon-based substrates, includes Na(AuCl4) and/or other gold (III) chloride salts as a gold ion source. The bath is formed as a binary bath solution formed from mixing first and second bath components. The first bath component includes gold salts in concentrations up to 40 g/L, boric acid, in amounts of up to 30 g/L, and a metal hydroxide in amounts up to 20 g/L. The second bath component includes an acid salt, in amounts up to 25 g/L, sodium thiosulfate in amounts up to 30 g/L, and suitable acid, such as boric acid in amounts up to 20 g/L.

Abstract: Provided is a method of manufacturing a semiconductor device having a structure in which an oxide film and a nitride film are stacked. The method includes forming a stacked film having an oxide film and a nitride film stacked therein on a substrate in a processing container by alternately performing a first cycle and a second cycle a predetermined number of times, the first cycle comprising forming the oxide film by supplying a source gas, a nitriding gas and an oxidizing gas to the substrate in the processing container a predetermined number of times, and the second cycle comprising forming the nitride film by supplying the source gas and the nitriding gas to the substrate in the processing container a predetermined number of times, wherein the forming of the oxide film and the forming of the nitride film are consecutively performed while retaining a temperature of the substrate constant.

Abstract: A method for making a chemical contrast pattern uses directed self-assembly of block copolymers (BCPs) and sequential infiltration synthesis (SIS) of an inorganic material. For an example with poly(styrene-block-methyl methacrylate) (PS-b-PMMA) as the BCP and alumina as the inorganic material, the PS and PMMA self-assemble on a suitable substrate. The PMMA is removed and the PS is oxidized. A surface modification polymer (SMP) is deposited on the oxidized PS and the exposed substrate and the SMP not bound to the substrate is removed. The structure is placed in an atomic layer deposition chamber. Alumina precursors reactive with the oxidized PS are introduced and infuse by SIS into the oxidized PS, thereby forming on the substrate a chemical contrast pattern of SMP and alumina. The resulting chemical contrast pattern can be used for lithographic masks, for example to etch the underlying substrate to make an imprint template.

Abstract: A method of forming a nitrogen-doped amorphous carbon layer on a substrate in a processing chamber is provided. The method generally includes depositing a predetermined thickness of a sacrificial dielectric layer over a substrate, forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate, depositing conformally a predetermined thickness of a nitrogen-doped amorphous carbon layer on the patterned features and the exposed upper surface of the substrate, selectively removing the nitrogen-doped amorphous carbon layer from an upper surface of the patterned features and the upper surface of the substrate using an anisotropic etching process to provide the patterned features filled within sidewall spacers formed from the nitrogen-doped amorphous carbon layer, and removing the patterned features from the substrate.

Abstract: A thin-film encapsulation for an optoelectronic semiconductor body includes a PVD layer deposited by a PVD method, and a CVD layer deposited by a CVD method, wherein the CVD layer is applied directly on the PVD layer, and the CVD layer is etched back such that the CVD layer only fills weak points in the PVD layer.

Abstract: The method and apparatus disclosed herein relate to preparing a stack structure for an electronic device on a semiconductor substrate. A particularly beneficial application of the method is in reduction of internal stress in a stack containing multiple layers of silicon. Typically, though not necessarily, the internal stress is a compressive stress, which often manifests as wafer bow. In some embodiments, the method reduces the internal stress of a work piece by depositing phosphorus doped silicon layers having low internal compressive stress or even tensile stress. The method and apparatus disclosed herein can be used to reduce compressive bow in stacks containing silicon.

Abstract: Techniques include a method of forming an interfacial passivation layer between a first semiconductor material (such as germanium) and a high-k gate dielectric. Such techniques include using a hydrogen-based plasma formed using a slotted-plane antenna plasma processing system. Such a plasma treatment can be executed with substrate temperatures less than 380 degrees Celsius, and even down to about 200 degrees Celsius or below.

Abstract: Carbon layers with reduced hydrogen content may be deposited by plasma-enhanced chemical vapor deposition by selecting processing parameters accordingly. Such carbon layers may be subjected to high temperature processing without showing excessive shrinking.

Abstract: Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of a first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nm2 over and electrically coupled to the bottom electrodes, and a cell material over the electrical contacts.

Abstract: The method of forming a silicon oxycarbonitride film on a base includes stacking a silicon carbonitride film and a silicon oxynitride film on the base to form the silicon oxycarbonitride film.

Abstract: Provided is a method of manufacturing a semiconductor device which includes, in the following order: a first step of preparing a semiconductor element which includes a pn junction exposure portion; a second step of forming an insulation layer such that the insulation layer covers the pn junction exposure portion; and a third step of forming a glass layer on the insulation layer where a layer made of glass composition for protecting a semiconductor junction is formed on the insulation layer and, thereafter, the layer made of glass composition for protecting a semiconductor junction is baked.

Abstract: A method of depositing a silicon oxide film and a silicon nitride film includes depositing the silicon oxide film and the silicon nitride film on a substrate, and a gas for forming the silicon nitride film further includes boron.

Abstract: The method for forming wavelike coherent nanostructures by irradiating a surface of a material by a homogeneous flow of ions is disclosed. The rate of coherency is increased by applying preliminary preprocessing steps.

Abstract: A dielectric cap and related methods are disclosed. In one embodiment, the dielectric cap includes a dielectric material having an optical band gap (e.g., greater than about 3.0 electron-Volts) to substantially block ultraviolet radiation during a curing treatment, and including nitrogen with electron donor, double bond electrons. The dielectric cap exhibits a high modulus and is stable under post ULK UV curing treatments for, for example, copper low k back-end-of-line (BEOL) nanoelectronic devices, leading to less film and device cracking and improved reliability.

Abstract: There is provided a method of manufacturing a thin-film device, the method including forming a first substrate on a supporting base by a coating method, the first substrate being formed by using a resin material; forming a second substrate on the first substrate by using any one of a thermosetting resin and energy ray-curable resin; forming an active element on the second substrate; and removing the supporting base from the first substrate. The resin material used to form the first substrate has a glass transition temperature of at least 180° C.

Abstract: Methods are provided for forming gates in gate-last processes. The methods may include performing chemical mechanical polishing (CMP) on an interlayer dielectric (ILD) that is on a plurality of dummy gates, each of the plurality of dummy gates including a gate mask in an upper portion thereof, and the CMP exposing the gate mask. The methods may also include removing the gate mask by etching the gate mask. The methods may further include performing CMP on the ILD.

Abstract: The negative effect of oxygen on some metal films can be reduced or prevented by contacting the films with a treatment agent comprising silane or borane. In some embodiments, one or more films in an NMOS gate stack are contacted with a treatment agent comprising silane or borane during or after deposition.

Abstract: Provided is a two-step ALD deposition process for forming a gate dielectric involving an erbium oxide layer deposition followed by a hafnium oxide layer deposition. Hafnium oxide can provide a high dielectric constant, high density, large bandgap and good thermal stability. Erbium oxide can act as a barrier against oxygen diffusion, which can lead to increasing an effective oxide thickness of the gate dielectric and preventing hafnium-silicon reactions that may lead to higher leakage current.

Abstract: A mold having an open interior volume is used to define patterns. The mold has a ceiling, floor and sidewalls that define the interior volume and inhibit deposition. One end of the mold is open and an opposite end has a sidewall that acts as a seed sidewall. A first material is deposited on the seed sidewall. A second material is deposited on the deposited first material. The deposition of the first and second materials is alternated, thereby forming alternating rows of the first and second materials in the interior volume. The mold and seed layer are subsequently selectively removed. In addition, one of the first or second materials is selectively removed, thereby forming a pattern including free-standing rows of the remaining material. The free-standing rows can be utilized as structures in a final product, e.g., an integrated circuit, or can be used as hard mask structures to pattern an underlying substrate. The mold and rows of material can be formed on multiple levels.

Abstract: Provided is a two-step ALD deposition process for forming a gate dielectric involving an erbium oxide layer deposition followed by a hafnium oxide layer deposition. Hafnium oxide can provide a high dielectric constant, high density, large bandgap and good thermal stability. Erbium oxide can act as a barrier against oxygen diffusion, which can lead to increasing an effective oxide thickness of the gate dielectric and preventing hafnium-silicon reactions that may lead to higher leakage current.

Abstract: According to example embodiments, a method of forming a layer includes: forming a dielectric layer using a metal precursor expressed by one of R3yM(NR1R2)x-y and M(OR1R2) and using a silicon precursor expressed by HzSi(NR4R5)4-z. Each of “R1”, “R2”, “R3”, “R4”, and “R5” are hydrogen or hydrocarbon; “R3” is different than “R1” and “R2”; “x” is in the range of 3 to 5; “y” is in the range of 1 to 4; “z” is in the range of 2 to 3; and “M” is a metal. The dielectric layer is a metal silicate layer or a metal nitride layer doped with silicon.

Abstract: Methods and apparatus for high rate formation of multi-layer stacks on semiconductor substrate is provided. A chamber for forming such stacks at high rates includes a first precursor line and a second precursor line. The first precursor line is coupled to a first diverter, which is coupled to a gas inlet in a lid assembly of the chamber. The second precursor line is coupled to a second diverter, which is also coupled to the gas inlet. The first diverter is also coupled to a first divert line, and the second diverter is coupled to a second divert line. Each of the first and second divert lines is coupled to a divert exhaust system. A chamber exhaust system is coupled to the chamber. The diverters are typically located close to the lid assembly.

Abstract: Embodiments of an integrated platform for fabricating n-type metal oxide semiconductor (NMOS) devices are provided herein. In some embodiments, an integrated platform for fabricating n-type metal oxide semiconductor (NMOS) devices may include a first deposition chamber configured to deposit a first layer atop the substrate, the first layer comprising titanium oxide (TiO2) or selenium (Se); a second deposition chamber configured to deposit a second layer atop the first layer, the second layer comprising titanium; a third deposition chamber configured to deposit a third layer atop the second layer, the third layer comprising one of titanium nitride (TiN) or tungsten nitride (WN).

Abstract: Methods of treating metal-containing thin films, such as films comprising titanium carbide, with a silane/borane agent are provided. In some embodiments a film comprising titanium carbide is deposited on a substrate by an atomic layer deposition (ALD) process. The process may include a plurality of deposition cycles involving alternating and sequential pulses of a first source chemical that comprises titanium and at least one halide ligand, a second source chemical comprising metal and carbon, wherein the metal and the carbon from the second source chemical are incorporated into the thin film, and a third source chemical, wherein the third source chemical is a silane or borane that at least partially reduces oxidized portions of the titanium carbide layer formed by the first and second source chemicals. In some embodiments treatment forms a capping layer on the metal carbide film.

Abstract: There is provided a resist composition including a crosslinking material configured to cause crosslinking in the presence of an acid, an inclusion compound, and a solvent.

Abstract: Methods for fabricating guide patterns and methods for fabricating integrated circuits using guide patterns are provided. In an embodiment, a method for fabricating a guide pattern includes forming a coating of a material with latent grafting sites and a photosensitive component configured to activate the latent grafting sites upon exposure over a substrate. The method exposes selected latent grafting sites in the coating to convert the selected latent grafting sites to active grafting sites. A grafting agent is bonded to the active grafting sites to form the guide pattern.

Abstract: A method is provided for patterning a layered substrate that includes loading a substrate into a coater-developer processing system; coating the substrate with a photoresist material layer; patterning the photoresist material layer to form a photoresist pattern; transferring the substrate to a deposition processing system; and depositing a neutral layer over the photoresist pattern and exposed portions of the substrate. The neutral layer can deposited using a gas cluster ion beam (GCIB) process, or an atomic layer deposition (ALD) process, which has minimal topography. The method may further include lifting off a portion of the neutral layer deposited over the photoresist pattern to expose a neutral layer template for subsequent directed self-assembly (DSA) patterning; depositing a DSA material layer over the neutral layer template; baking the DSA material layer to form a DSA pattern; and developing the DSA material layer to expose the final DSA pattern for subsequent feature etching.

Abstract: A trialkylsilane-based silicon precursor compound may be expressed by the following chemical formula 1. In the chemical formula 1, each of “R1”, “R2”, and “R3” is a hydrogen or an alkyl having 1˜5 carbon(s), all of “R1”, “R2”, and “R3” are not hydrogen, “X” is one of hydrogen, a hydroxyl group, an amide group, an alkoxide group, a halide group, or Si(R*)3, and “R*” is a hydrogen or an alkyl group having 1˜5 carbon(s).

Abstract: Methods for creating chemical guide patterns by DSA lithography for fabricating an integrated circuit are provided. In one example, an integrated circuit includes forming a bifunctional brush layer of a polymeric material overlying an anti-reflective coating on a semiconductor substrate. The polymeric material has a neutral polymeric block portion and a pinning polymeric block portion that are coupled together. The bifunctional brush layer includes a neutral layer that is formed of the neutral polymeric block portion and a pinning layer that is formed of the pinning polymeric block portion. A portion of the neutral layer or the pinning layer is selectively removed to define a chemical guide pattern. A block copolymer layer is deposited overlying the chemical guide pattern. The block copolymer layer is phase separated to define a nanopattern that is registered to the chemical guide pattern.

Abstract: A limited number of cycles of atomic layer deposition (ALD) of Hi-K material followed by deposition of an interlayer dielectric and application of further Hi-K material and optional but preferred annealing provides increased Hi-K material content and increased breakdown voltage for input/output (I/O) transistors compared with logic transistors formed on the same chip or wafer while providing scalability of the inversion layer of the I/O and logic transistors without significantly compromising performance or bias temperature instability (BTI) parameters.