Layers Formed Of Diverse Composition Or By Diverse Coating Processes Patents (Class 438/763)
  • Patent number: 9006802
    Abstract: Semiconductor device manufacturing methods and methods of forming insulating material layers are disclosed. In one embodiment, a method of forming a composite insulating material layer of a semiconductor device includes providing a workpiece and forming a first sub-layer of the insulating material layer over the workpiece using a first plasma power level. A second sub-layer of the insulating material layer is formed over the first sub-layer of the insulating material layer using a second plasma power level, and the workpiece is annealed.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Gin-Chen Huang, Tsai-Fu Hsiao, Ching-Hong Jiang, Neng-Kuo Chen, Hongfa Luan, Sey-Ping Sun, Clement Hsingjen Wann
  • Publication number: 20150099373
    Abstract: In order to extend the cycle of gas cleaning for a film-forming device, a method for manufacturing a semiconductor device includes: a substrate carry-in process for carrying a substrate into a processing chamber; a film forming process for laminating at least two types of films on the substrate in the processing chamber; a substrate carry-out process for carrying the film laminated substrate out from the processing chamber; an etching process for supplying an etching gas into the processing chamber while the substrate is not in the processing chamber after the substrate carry-out process. The etching process includes a first cleaning process for supplying a fluorine-containing gas activated by plasma excitation into the processing chamber as an etching gas; and a second cleaning process for supplying a fluorine-containing gas activated by heat into the processing chamber as an etching gas.
    Type: Application
    Filed: March 22, 2013
    Publication date: April 9, 2015
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Atsushi Sano, Masayuki Asai, Masahiro Yonebayashi
  • Patent number: 8999859
    Abstract: Methods of depositing a film on a substrate surface include surface mediated reactions in which a film is grown over one or more cycles of reactant adsorption and reaction. In one aspect, the method is characterized by intermittent delivery of dopant species to the film between the cycles of adsorption and reaction.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: April 7, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Shankar Swaminathan, Jon Henri, Dennis M. Hausmann, Pramod Subramonium, Mandyam Sriram, Vishwanathan Rangarajan, Kirthi K. Kattige, Bart K. van Schravendijk, Andrew J. McKerrow
  • Publication number: 20150093912
    Abstract: Disclosed herein is a formulation for depositing a cured underlayer for promoting the formation of self assembled structures. The underlayer comprises: (a) a polymer comprising at least one pendant vinyl ether monomer repeat unit having the structure, (I): wherein R is chosen from H, C1-C4 alkyl, or halogen, and W is a divalent group chosen from C1-C6 alkylene, C6-C20 arylene, benzylene, or C2-C20 alkyleneoxyalkylene; (ii) optional thermal acid generator; and (c) a solvent. The invention also relates to processes of forming a pattern using the underlayer.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Applicant: AZ ELECTRONIC MATERIALS (LUXEMBOURG) S.A.R.L.
    Inventors: Hengpeng WU, Jian YIN, Guanyang LIN, JiHoon KIM, Jianhui SHAN
  • Patent number: 8993455
    Abstract: Atomic layer deposition (ALD) can be used to form a dielectric layer of zirconium aluminum oxynitride (ZrAlON) for use in a variety of electronic devices. Forming the dielectric layer may include depositing zirconium oxide using atomic layer deposition and precursor chemicals, followed by depositing aluminum nitride using precursor chemicals, and repeating. The dielectric layer may be used as the gate insulator of a MOSFET, a capacitor dielectric, and a tunnel gate insulator in flash memories.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: March 31, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8993456
    Abstract: Provided is a method of operating a film forming apparatus capable of suppressing generation of particles by improving an adhesion of a carbon film to surfaces of members which are formed of a quartz material and contact a processing space in a processing container. The method includes forming a carbon film on each of surfaces of a plurality of objects held by a holding unit in a processing container formed of a quartz material, wherein the method further includes forming an adhesion film to improve the adhesion of the carbon film, on surfaces of members which are formed of a quartz material and contact a processing space in the processing container. Accordingly, the adhesion of the carbon film to the surface of the member formed of a quartz material contacting the processing space in the processing container is improved, thereby suppressing generation of particles.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: March 31, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Atsushi Endo, Satoshi Mizunaga, Takehiro Otsuka
  • Patent number: 8993457
    Abstract: A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a tunneling dielectric and a charge-trapping layer overlying the tunneling dielectric; depositing a first cap layer comprising an oxide over the dielectric stack; forming a second cap layer comprising a nitride over the first cap layer; patterning the first and second cap layers and the dielectric stack to form a gate stack of a memory device; removing the second cap layer; and performing an oxidation process to form a blocking oxide over the charge-trapping layer, wherein the oxidation process consumes the first cap layer. Other embodiments are also described.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: March 31, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Hui-Mei (Mei) Shih
  • Patent number: 8993459
    Abstract: A method comprises depositing a first portion of a first material layer on a semiconductor structure. A first run of a post-treatment process is performed for modifying at least the first portion of the first material layer. After the first run of the post-treatment process, a second portion of the first material layer is deposited. The second portion is formed of substantially the same material as the first portion. After the deposition of the second portion of the first material layer, a second run of the post-treatment process is performed for modifying at least the second portion of the first material layer.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: March 31, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Carsten Grass, Martin Trentzsch, Boris Bayha, Peter Krottenthaler
  • Patent number: 8987147
    Abstract: A method of depositing a film on substrates using an apparatus including a turntable mounting substrates, first and second process areas above the upper surface of the turntable provided with gas supplying portions, a separation gas supplying portion between the first and second process areas, and a separation area including depositing a first oxide film by rotating the turntable first turns while supplying a first reaction gas, the oxidation gas from the second gas supplying portion, and the separation gas; rotating at least one turn while supplying the separation gas from the first gas supplying portion and the separation gas supplying portion, and the oxidation gas from the second gas supplying portion; and rotating at least second turns to deposit a second oxide film while supplying a second reaction gas from the first gas supplying portion, the oxidation gas from the second gas supplying portion, and the separation gas.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: March 24, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Hiroaki Ikegawa, Masahiko Kaminishi, Kosuke Takahashi, Masato Koakutsu, Jun Ogawa
  • Publication number: 20150079804
    Abstract: An under layer film having excellent surface planarity is provided. In one aspect, the under layer film-forming composition for imprints includes a (meth)acrylic resin (A) containing an ethylenic unsaturated group (P) and a nonionic hydrophilic group (Q), and having a weight average molecular weight of 1,000 or larger; and a solvent (B), the resin (A) having an acid value of smaller than 1.0 mmol/g. In another aspect, the under layer film-forming composition for imprints includes a (meth)acrylic resin (A2) containing an ethylenic unsaturated group (P), and containing, as a nonionic hydrophilic group (Q), a cyclic substituent (Q2) having a carbonyl group in the cyclic structure thereof, with a weight average molecular weight of 1,000 or larger; and a solvent (B).
    Type: Application
    Filed: November 20, 2014
    Publication date: March 19, 2015
    Applicant: FUJIFILM Corporation
    Inventors: Hirotaka KITAGAWA, Akiko HATTORI, Yuichiro ENOMOTO
  • Publication number: 20150076663
    Abstract: Some embodiments include methods of patterning a base. First and second masking features are formed over the base. The first and second masking features include pedestals of carbon-containing material capped with silicon oxynitride. A mask is formed over the second masking features, and the silicon oxynitride caps are removed from the first masking features. Spacers are formed along sidewalls of the first masking features. The mask and the carbon-containing material of the first masking features are removed. Patterns of the spacers and second masking features are transferred into one or more materials of the base to pattern said one or more materials. Some embodiments include patterned bases.
    Type: Application
    Filed: November 19, 2014
    Publication date: March 19, 2015
    Inventor: John D. Hopkins
  • Patent number: 8981466
    Abstract: Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Alfred Grill, Seth L. Knupp, Son V. Nguyen, Vamsi K. Paruchuri, Deepika Priyadarshini, Hosadurga K. Shobha
  • Patent number: 8980765
    Abstract: Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material on the first region formed using the first precursor, wherein the first material is different from a second material formed on a second region of the substrate.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: March 17, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Sunil Shanker, Tony P. Chiang
  • Patent number: 8980715
    Abstract: Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Alfred Grill, Seth L. Knupp, Son V. Nguyen, Vamsi K. Paruchuri, Deepika Priyadarshini, Hosadurga K. Shobha
  • Patent number: 8968864
    Abstract: A method for at least partially sealing a porous material is provided, comprising forming a sealing layer onto the porous material by applying a sealing compound comprising oligomers wherein the oligomers are formed by ageing a precursor solution comprising cyclic carbon bridged organosilica and/or bridged organosilanes. The method is especially designed for low k dielectric porous materials to be incorporated into semiconductor devices.
    Type: Grant
    Filed: September 18, 2012
    Date of Patent: March 3, 2015
    Assignees: IMEC, Universiteit Gent
    Inventors: Frederik Goethals, Pascal Van Der Voort, Isabel Van Driessche, Mikhail Baklanov
  • Publication number: 20150054143
    Abstract: A passivation structure includes a bottom dielectric layer. The passivation structure further includes a doped dielectric layer over the bottom dielectric layer. The doped dielectric layer includes a first doped layer and a second doped layer. The passivation structure further includes a top dielectric layer over the doped dielectric layer.
    Type: Application
    Filed: October 20, 2014
    Publication date: February 26, 2015
    Inventors: Cheng-Chi CHUANG, Kun-Ming HUANG, Hsuan-Hui HUNG, Ming-Yi LIN
  • Patent number: 8962493
    Abstract: A manufacturing method to form a memory device includes: (1) forming a dielectric layer adjacent to a magnetic stack; (2) forming an opening in the dielectric layer; (3) applying a hard mask material adjacent to the dielectric layer to form a pillar disposed in the opening of the dielectric layer; and (4) using the pillar as a hard mask, patterning the magnetic stack to form a MRAM cell.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: February 24, 2015
    Assignee: Crocus Technology Inc.
    Inventors: Amitay Levi, Dafna Beery
  • Publication number: 20150048488
    Abstract: Semiconductor devices, methods of manufacture thereof, and IMD structures are disclosed. In some embodiments, a semiconductor device includes an adhesion layer disposed over a workpiece. The adhesion layer has a dielectric constant of about 4.0 or less and includes a substantially homogeneous material. An insulating material layer is disposed over the adhesion layer. The insulating material layer has a dielectric constant of about 2.6 or less. The adhesion layer and the insulating material layer comprise an IMD structure.
    Type: Application
    Filed: August 15, 2013
    Publication date: February 19, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Yun Peng, Keng-Chu Lin, Joung-Wei Liou, Kuang-Yuan Hsu
  • Patent number: 8956983
    Abstract: Disclosed herein are methods of doping a patterned substrate in a reaction chamber. The methods may include forming a first conformal film layer which has a dopant source including a dopant, and driving some of the dopant into the substrate to form a conformal doping profile. In some embodiments, forming the first film layer may include introducing a dopant precursor into the reaction chamber, adsorbing the dopant precursor under conditions whereby it forms an adsorption-limited layer, and reacting the adsorbed dopant precursor to form the dopant source. Also disclosed herein are apparatuses for doping a substrate which may include a reaction chamber, a gas inlet, and a controller having machine readable code including instructions for operating the gas inlet to introduce dopant precursor into the reaction chamber so that it is adsorbed, and instructions for reacting the adsorbed dopant precursor to form a film layer containing a dopant source.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: February 17, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Shankar Swaminathan, Mandyam Sriram, Bart van Schravendijk, Pramod Subramonium, Adrien LaVoie
  • Patent number: 8956730
    Abstract: An electrically conductive multilayer stack including a first metal oxide layer including titanium oxide, a metal layer on the first metal oxide layer, and a second metal oxide layer including titanium oxide on the metal layer, at least one of the first metal oxide layer and the second metal oxide layer including a first region, a second region on the first region, and a third region on the second region, the first region and the third region each having a higher oxygen concentration than that of the second region is disclosed. Methods of manufacturing an electrically conductive multilayer stack are also disclosed.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: February 17, 2015
    Assignee: PPG Industries Ohio, Inc.
    Inventors: Krishna K. Uprety, Alexander Bimanand, Khushroo H. Lakdawala
  • Patent number: 8945302
    Abstract: Method for crystal growth from a surfactant of a metal-nonmetal (MN) compound, including the procedures of providing a seed crystal, introducing atoms of a first metal to the seed crystal thus forming a thin liquid metal wetting layer on a surface of the seed crystal, setting a temperature of the seed crystal below a minimal temperature required for dissolving MN molecules in the wetting layer and above a melting point of the first metal, each one of the MN molecules being formed from an atom of a second metal and an atom of a first nonmetal, introducing the MN molecules which form an MN surfactant monolayer, thereby facilitating a formation of the wetting layer between the MN surfactant monolayer and the surface of the seed crystal, and regulating a thickness of the wetting layer, thereby growing an epitaxial layer of the MN compound on the seed crystal.
    Type: Grant
    Filed: March 4, 2012
    Date of Patent: February 3, 2015
    Assignee: Mosaic Crystals Ltd.
    Inventor: Moshe Einav
  • Patent number: 8946830
    Abstract: Embodiments related to metal oxide protective layers formed on a surface of a halogen-sensitive metal-including layer present on a substrate processed in a semiconductor processing reactor are provided. In one example, a method for forming a metal oxide protective layer is provided. The example method includes forming a metal-including active species on the halogen-sensitive metal-including layer, the metal-including active species being derived from a non-halogenated metal oxide precursor. The example method also includes reacting an oxygen-containing reactant with the metal-including active species to form the metal oxide protective layer.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: February 3, 2015
    Assignee: ASM IP Holdings B.V.
    Inventor: Sung-Hoon Jung
  • Patent number: 8945305
    Abstract: Methods for depositing a material, such as a metal or a transition metal oxide, using an ALD (atomic layer deposition) process and resulting structures are disclosed. Such methods include treating a surface of a semiconductor structure periodically throughout the ALD process to regenerate a blocking material or to coat a blocking material that enables selective deposition of the material on a surface of a substrate. The surface treatment may reactivate a surface of the substrate toward the blocking material, may restore the blocking material after degradation occurs during the ALD process, and/or may coat the blocking material to prevent further degradation during the ALD process. For example, the surface treatment may be applied after performing one or more ALD cycles. Accordingly, the presently disclosed methods enable in situ restoration of blocking materials in ALD process that are generally incompatible with the blocking material and also enables selective deposition in recessed structures.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh
  • Publication number: 20150028458
    Abstract: A semiconductor device is provided that includes a diffusion barrier layer between a compound semiconductor layer and a dielectric layer, as well as a method of fabricating the semiconductor device, such that the semiconductor device includes a compound semiconductor layer; a dielectric layer; and a diffusion barrier layer including an oxynitride formed between the compound semiconductor layer and the dielectric layer.
    Type: Application
    Filed: March 14, 2014
    Publication date: January 29, 2015
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dong-soo Lee, Eui-chul Hwang, Seong-ho Cho, Myoung-jae Lee, Sang-moon Lee, Sung-hun Lee, Rakib Uddin Mohammad, David Seo, Moon-seung Yang, Ji-hyun Hur
  • Publication number: 20150031210
    Abstract: Methods of forming fine patterns are provided. The method includes reinforcing a hydrophobic property of a hard mask layer using a surface treatment process to form a neutral layer, forming a block co-polymer layer on the neutral layer, and phase-separating the block co-polymer layer into first domains and second domains.
    Type: Application
    Filed: December 19, 2013
    Publication date: January 29, 2015
    Applicant: SK HYNIX INC.
    Inventors: Keun Do BAN, Cheol Kyu BOK, Myoung Soo KIM, Ki Lyoung LEE, Hyun Kyung SHIM
  • Publication number: 20150031216
    Abstract: There is provided a method of cleaning an inside of a process chamber, which is formed by a reaction tube and a manifold configured to support the reaction tube and installed under a heater, after forming a stacked film of oxide and nitride films on a substrate in the process chamber by alternately performing forming the oxide film on the substrate and forming the nitride film thereon. The method includes supplying a hydrogen-free fluorine-based gas from a first nozzle, which is installed in the manifold to extend upward from the manifold to an inside of the reaction tube, to an inner wall of the reaction tube; and supplying a hydrogen fluoride gas from a second nozzle, which is installed in the manifold, to an inner wall of the manifold.
    Type: Application
    Filed: July 25, 2014
    Publication date: January 29, 2015
    Applicant: HITACHI KOKUSAI ELECTRIC, INC.
    Inventors: Naonori AKAE, Kenji KAMEDA
  • Publication number: 20150017813
    Abstract: A semiconductor device manufacturing method that includes: forming a gate insulating film containing a hafnium oxide and a zirconium oxide on a workpiece having a source, a drain and a channel; and subjecting the gate insulating film to a crystallization heat treatment at a temperature of 600 degrees C. or less is provided. The gate insulating film subjected to the crystallization heat treatment has a relative permittivity of 27 or more.
    Type: Application
    Filed: October 2, 2014
    Publication date: January 15, 2015
    Inventors: Koji AKIYAMA, Hirokazu HIGASHIJIMA, Chihiro TAMURA, Shintaro AOYAMA, Yu WAMURA
  • Publication number: 20150008500
    Abstract: A non-volatile semiconductor memory free from adverse effects due to process charge is provided. The non-volatile semiconductor memory includes: a silicon substrate; a first silicon oxide film; a second silicon oxide film; a first silicon nitride film; and a second silicon nitride film, wherein the first silicon oxide film is layered on the silicon substrate, the first silicon nitride film is layered on the first silicon oxide film, the second silicon oxide film is layered on the first silicon nitride film, and the second silicon nitride film is layered to have a first part that is in contact with the first silicon nitride film and a second part that is in contact with the silicon substrate.
    Type: Application
    Filed: February 22, 2013
    Publication date: January 8, 2015
    Inventors: Yohei Fukumoto, Takaoki Sasaki
  • Patent number: 8927438
    Abstract: Provided are methods for depositing a cerium doped hafnium containing high-k dielectric film on a substrate. The reagents of specific methods include hafnium tetrachloride, an organometallic complex of cerium and water.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: January 6, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Hyungjun Kim, Woo-Hee Kim, Min-Kyu Kim, Steven Hung, Atif Noori, David Thompson, Jeffrey W. Anthis
  • Publication number: 20150001682
    Abstract: Among other things, one or more wafer edge protection structures and techniques for forming such wafer edge protection structures are provided. A substrate of a semiconductor wafer comprises an edge, such as a beveled wafer edge portion, that is susceptible to Epi growth which results in undesirable particle contamination of the semiconductor wafer. Accordingly, a wafer edge protection structure is formed over the beveled wafer edge portion. The wafer edge protection structure comprises an Epi growth resistant material, such as an amorphous material, a non-crystalline material, oxide, or other material. In this way, the wafer edge protection structure mitigates Epi growth on the beveled wafer edge portion, where the Epi growth increases a likelihood of particle contamination from cracking or peeling of an Epi film resulting from the Epi growth. The wafer edge protection structure thus mitigates at least some contamination of the wafer.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: Ming Chyi Liu, Sheng-de Liu, Chi-Ming Chen, Yuan-Tai Tseng, Chung-Yen Chou, Chia-Shiung Tsai
  • Publication number: 20150004802
    Abstract: Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.
    Type: Application
    Filed: September 16, 2014
    Publication date: January 1, 2015
    Inventors: Deok-kee Kim, Kenneth T. Settlemyer, JR., Kangguo Cheng, Ramachandra Divakaruni, Carl J. Radens, Dirk Pfeiffer, Timothy J. Dalton, Katherina E. Babich, Arpan P. Mohorowala, Harald Okorn-Schmidt
  • Publication number: 20150004801
    Abstract: The present disclosure relates to spin-on compositions containing at least one metal oxide dicarboxylate and an organic solvent into which the metal oxide dicarboxylate is soluble or colloidally stable. The dicarboxylate is capable of decomposing during heat treatment to give a cured metal oxide film. The present disclosure also relates to method of using the spin-on compositions.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Applicant: AZ ELECTRONIC MATERIALS (LUXEMBOURG) S.A.R.L.
    Inventors: M. Dalil RAHMAN, Venkata Gopal Reddy CHADA, Huirong YAO, Clement ANYADIEGWU, Douglas MCKENZIE
  • Patent number: 8921236
    Abstract: A method of producing a patterned inorganic thin film element includes providing a substrate. A thin layer of polymeric inhibitor is uniformly depositing on the substrate. A patterned mask having open areas is provided on the thin layer of polymeric inhibitor. The thin layer of polymeric inhibitor is patterned by removing inhibitor from areas exposed by the open areas of the patterned mask using a highly reactive oxygen process. An inorganic thin film layer is deposited on the substrate in the areas exposed by the removal of the thin layer of polymeric inhibitor using an atomic layer deposition process.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: December 30, 2014
    Assignee: Eastman Kodak Company
    Inventors: Carolyn R. Ellinger, Shelby F. Nelson, Kurt D. Sieber
  • Publication number: 20140377963
    Abstract: A method of producing a patterned inorganic thin film element includes providing a substrate. A thin layer of polymeric inhibitor is uniformly depositing on the substrate. A patterned mask having open areas is provided on the thin layer of polymeric inhibitor. The thin layer of polymeric inhibitor is patterned by removing inhibitor from areas exposed by the open areas of the patterned mask using a highly reactive oxygen process. An inorganic thin film layer is deposited on the substrate in the areas exposed by the removal of the thin layer of polymeric inhibitor using an atomic layer deposition process.
    Type: Application
    Filed: June 21, 2013
    Publication date: December 25, 2014
    Inventors: Carolyn R. Ellinger, Shelby F. Nelson, Kurt D. Sieber
  • Patent number: 8916768
    Abstract: The surface recombination velocity of a silicon sample is reduced by deposition of a thin hydrogenated amorphous silicon or hydrogenated amorphous silicon carbide film, followed by deposition of a thin hydrogenated silicon nitride film. The surface recombination velocity is further decreased by a subsequent anneal. Silicon solar cell structures using this new method for efficient reduction of the surface recombination velocity is claimed.
    Type: Grant
    Filed: April 12, 2006
    Date of Patent: December 23, 2014
    Assignees: Rec Solar Pte. Ltd., Universitetet I Oslo, Instititt for Energiteknikk
    Inventors: Alexander Ulyashin, Andreas Bentzen, Bengt Svensson, Arve Holt, Erik Sauar
  • Patent number: 8916482
    Abstract: A method of making a lithography mask with a stress-relief treatment is disclosed. The method includes providing a substrate and depositing an opaque layer on the substrate. The opaque layer is patterned to form a patterned mask. A stress-relief treatment is applied to the patterned mask by using an radiation exposure.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: December 23, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Chang Lee, Yun-Yue Lin, Hung-Chang Hsieh, Chia-Jen Chen, Yih-Chen Su, Ta-Cheng Lien, Anthony Yen
  • Publication number: 20140353771
    Abstract: A semiconductor/dielectric interface having reduced interface trap density and a method of manufacturing the interface are disclosed. In an exemplary embodiment, the method of forming a semiconductor device includes receiving a substrate and forming a termination layer on a top surface of the substrate. The termination layer includes at least one of hydrogen, deuterium, or nitrogen. The method further includes depositing a dielectric layer on the termination layer such that the depositing of the dielectric layer does not disrupt the termination layer. The termination layer may be formed by a first deposition process that deposits a first material of the termination layer and a subsequent deposition process that introduces a second material of the termination layer into the first material. The termination layer may also be formed by a single deposition process that deposits both a first material and a second material of the termination layer.
    Type: Application
    Filed: August 20, 2014
    Publication date: December 4, 2014
    Inventors: Chien-Hsun Wang, Shih-Wei Wang, Gerben Doornbos, Georgios Vellianitis, Matthias Passlack
  • Patent number: 8900998
    Abstract: A plating bath for electroless deposition of gold and gold alloy layers on such silicon-based substrates, includes Na(AuCl4) and/or other gold (III) chloride salts as a gold ion source. The bath is formed as a binary bath solution formed from mixing first and second bath components. The first bath component includes gold salts in concentrations up to 40 g/L, boric acid, in amounts of up to 30 g/L, and a metal hydroxide in amounts up to 20 g/L. The second bath component includes an acid salt, in amounts up to 25 g/L, sodium thiosulfate in amounts up to 30 g/L, and suitable acid, such as boric acid in amounts up to 20 g/L.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: December 2, 2014
    Assignee: University of Windsor
    Inventors: Mordechay Schlesinger, Robert Andrew Petro
  • Patent number: 8901014
    Abstract: Provided is a method of manufacturing a semiconductor device having a structure in which an oxide film and a nitride film are stacked. The method includes forming a stacked film having an oxide film and a nitride film stacked therein on a substrate in a processing container by alternately performing a first cycle and a second cycle a predetermined number of times, the first cycle comprising forming the oxide film by supplying a source gas, a nitriding gas and an oxidizing gas to the substrate in the processing container a predetermined number of times, and the second cycle comprising forming the nitride film by supplying the source gas and the nitriding gas to the substrate in the processing container a predetermined number of times, wherein the forming of the oxide film and the forming of the nitride film are consecutively performed while retaining a temperature of the substrate constant.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: December 2, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Yosuke Ota, Naonori Akae, Yoshiro Hirose, Ryota Sasajima
  • Patent number: 8900467
    Abstract: A method for making a chemical contrast pattern uses directed self-assembly of block copolymers (BCPs) and sequential infiltration synthesis (SIS) of an inorganic material. For an example with poly(styrene-block-methyl methacrylate) (PS-b-PMMA) as the BCP and alumina as the inorganic material, the PS and PMMA self-assemble on a suitable substrate. The PMMA is removed and the PS is oxidized. A surface modification polymer (SMP) is deposited on the oxidized PS and the exposed substrate and the SMP not bound to the substrate is removed. The structure is placed in an atomic layer deposition chamber. Alumina precursors reactive with the oxidized PS are introduced and infuse by SIS into the oxidized PS, thereby forming on the substrate a chemical contrast pattern of SMP and alumina. The resulting chemical contrast pattern can be used for lithographic masks, for example to etch the underlying substrate to make an imprint template.
    Type: Grant
    Filed: May 25, 2013
    Date of Patent: December 2, 2014
    Assignee: HGST Netherlands B.V.
    Inventors: Yves-Andre Chapuis, Ricardo Ruiz, Lei Wan
  • Publication number: 20140349490
    Abstract: A method of forming a nitrogen-doped amorphous carbon layer on a substrate in a processing chamber is provided. The method generally includes depositing a predetermined thickness of a sacrificial dielectric layer over a substrate, forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate, depositing conformally a predetermined thickness of a nitrogen-doped amorphous carbon layer on the patterned features and the exposed upper surface of the substrate, selectively removing the nitrogen-doped amorphous carbon layer from an upper surface of the patterned features and the upper surface of the substrate using an anisotropic etching process to provide the patterned features filled within sidewall spacers formed from the nitrogen-doped amorphous carbon layer, and removing the patterned features from the substrate.
    Type: Application
    Filed: January 16, 2013
    Publication date: November 27, 2014
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Sungjin Kim, Deenesh Padhi, Sung Hyun Hong, Bok Hoen Kim, Derek R. Witty
  • Patent number: 8896019
    Abstract: A thin-film encapsulation for an optoelectronic semiconductor body includes a PVD layer deposited by a PVD method, and a CVD layer deposited by a CVD method, wherein the CVD layer is applied directly on the PVD layer, and the CVD layer is etched back such that the CVD layer only fills weak points in the PVD layer.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: November 25, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Franz Eberhard, Sebastian Taeger, Korbinian Perzlmaier
  • Patent number: 8895415
    Abstract: The method and apparatus disclosed herein relate to preparing a stack structure for an electronic device on a semiconductor substrate. A particularly beneficial application of the method is in reduction of internal stress in a stack containing multiple layers of silicon. Typically, though not necessarily, the internal stress is a compressive stress, which often manifests as wafer bow. In some embodiments, the method reduces the internal stress of a work piece by depositing phosphorus doped silicon layers having low internal compressive stress or even tensile stress. The method and apparatus disclosed herein can be used to reduce compressive bow in stacks containing silicon.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: November 25, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Keith Fox, Dong Niu, Joseph L. Womack
  • Publication number: 20140342575
    Abstract: Techniques include a method of forming an interfacial passivation layer between a first semiconductor material (such as germanium) and a high-k gate dielectric. Such techniques include using a hydrogen-based plasma formed using a slotted-plane antenna plasma processing system. Such a plasma treatment can be executed with substrate temperatures less than 380 degrees Celsius, and even down to about 200 degrees Celsius or below.
    Type: Application
    Filed: May 12, 2014
    Publication date: November 20, 2014
    Applicant: Tokyo Electron Limited
    Inventors: Toru Ito, Paul C. Mcintyre
  • Publication number: 20140335700
    Abstract: Carbon layers with reduced hydrogen content may be deposited by plasma-enhanced chemical vapor deposition by selecting processing parameters accordingly. Such carbon layers may be subjected to high temperature processing without showing excessive shrinking.
    Type: Application
    Filed: May 10, 2013
    Publication date: November 13, 2014
    Inventors: Guenter Denifl, Markus Kahn, Helmut Schoenherr, Daniel Maurer, Thomas Grille, Joachim Hirschler, Ursula Hedenig, Roland Moennich, Matthias Kuenle
  • Patent number: 8877628
    Abstract: Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of a first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nm2 over and electrically coupled to the bottom electrodes, and a cell material over the electrical contacts.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: November 4, 2014
    Assignee: Micron Technologies, Inc.
    Inventors: Jun Liu, Kunal R. Parekh
  • Patent number: 8871655
    Abstract: The method of forming a silicon oxycarbonitride film on a base includes stacking a silicon carbonitride film and a silicon oxynitride film on the base to form the silicon oxycarbonitride film.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: October 28, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Keisuke Suzuki, Kentaro Kadonaga, Byoung Hoon Lee, Eun Jo Lee, Sung Duk Son, Jae Hyuk Jang, Do Hyun Park
  • Publication number: 20140312472
    Abstract: Provided is a method of manufacturing a semiconductor device which includes, in the following order: a first step of preparing a semiconductor element which includes a pn junction exposure portion; a second step of forming an insulation layer such that the insulation layer covers the pn junction exposure portion; and a third step of forming a glass layer on the insulation layer where a layer made of glass composition for protecting a semiconductor junction is formed on the insulation layer and, thereafter, the layer made of glass composition for protecting a semiconductor junction is baked.
    Type: Application
    Filed: November 28, 2012
    Publication date: October 23, 2014
    Inventors: Atsushi Ogasawara, Koji Ito, Kazuhiko Ito, Koya Muyari
  • Publication number: 20140308820
    Abstract: A method of depositing a silicon oxide film and a silicon nitride film includes depositing the silicon oxide film and the silicon nitride film on a substrate, and a gas for forming the silicon nitride film further includes boron.
    Type: Application
    Filed: June 26, 2014
    Publication date: October 16, 2014
    Inventors: Atsushi ENDO, Masaki KUROKAWA, Hiroki IRIUDA
  • Patent number: 8859440
    Abstract: The method for forming wavelike coherent nanostructures by irradiating a surface of a material by a homogeneous flow of ions is disclosed. The rate of coherency is increased by applying preliminary preprocessing steps.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: October 14, 2014
    Assignee: Wostec, Inc.
    Inventors: Valery K. Smirnov, Dmitry S. Kibalov