Abstract: A method for fabricating an electronic device that includes a metal-insulator-semiconductor (M-I-S) structure includes: providing a semiconductor layer; forming a primary insulation layer of a first thickness over the semiconductor layer; forming a reactive metal layer of a second thickness over the primary insulation layer, where the second thickness is greater than the first thickness; forming a primary capping layer of a third thickness over the reactive metal layer, where the third thickness is greater than the second thickness; and performing a thermal treatment.

Abstract: A method of integrating a silicon-oxide-nitride-oxide-silicon (SONOS) transistor into a complementary metal-oxide-silicon (CMOS) baseline process. The method includes the steps of forming the gate oxide layer of at least one metal-oxide-silicon (MOS) transistor prior to forming a non-volatile (NV) gate stack of the SONOS transistor.

Abstract: A method of manufacturing a semiconductor device, including forming a laminated film on a substrate by performing a cycle a first predetermined number of times. The cycle includes forming a first film which contains a predetermined element, boron, and nitrogen, and forming a second film which contains boron and nitrogen. A composition ratio of boron to nitrogen in the second film is different from that in the first film. The first film and the second film are laminated to form the laminated film.

Abstract: A method of manufacturing a semiconductor device, including forming a laminated film on a substrate by performing a cycle a first predetermined number of times. The cycle includes forming a first film which contains a predetermined element, boron, and nitrogen, and forming a second film which contains boron and nitrogen. A composition ratio of boron to nitrogen in the second film is different from that in the first film. The first film and the second film are laminated to form the laminated film.

Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern.

Abstract: According to the present disclosure, a film containing carbon added at a high concentration is formed with high controllability. A method of manufacturing a semiconductor device includes forming a film containing silicon, carbon and a predetermined element on a substrate by performing a cycle a predetermined number of times. The predetermined element is one of nitrogen and oxygen. The cycle includes supplying a precursor gas containing at least two silicon atoms per one molecule, carbon and a halogen element and having an Si—C bonding to the substrate, and supplying a modifying gas containing the predetermined element to the substrate.

Abstract: The present invention increases controllability of a composition ratio of a multi-element film that contains a predetermined element and at least one element selected from the group consisting of boron, oxygen, carbon and nitrogen. There is provided a method of manufacturing a semiconductor device, including: forming a laminated film where a first film and a second film are laminated on a substrate by performing a cycle a predetermined number of times, the cycle including: (a) forming the first film being free of borazine ring structure and including a predetermined element and at least one element selected from the group consisting of oxygen, carbon and nitrogen; and (b) forming the second film having a borazine ring structure and including at least boron and nitrogen.

Abstract: A semiconductor device and a method for manufacturing the same are provided in the present invention. The semiconductor device includes a substrate, agate structure on the substrate and two spacers on both sidewalls of the gate structure. Each spacer comprises an inner first spacer portion made of SiCN and an outer second spacer portion made of SiOCN.

Abstract: Methods for using high-speed EUV resists including resists having additives that may be detrimental to etch chambers. Methods include using reversal materials and/or reversal techniques, as well as diffusion-limited etch-back and slimming for pattern creation and transfer. A substrate with high-speed EUV resist is lithographically patterned and developed into a patterned resist mask. An image reversal material is then over-coated on the patterned resist mask such that the image reversal material fills and covers the patterned resist mask. An upper portion of the image reversal material is removed such that top surfaces of the patterned resist mask are exposed. The patterned resist mask is removed such that the image reversal material remains resulting in a patterned image reversal material mask. Residual resist material is removed via a slimming process using an acid diffusion and subsequent development.

Abstract: A method for manufacturing an optoelectric device comprising a semiconductor substrate, pads on a surface of the substrate; semiconductor elements, each element being in contact with a pad; and a dielectric region extending in the substrate from the surface and connecting, for each pair of pads, one of the pads in the pair to the other pad in the pair, the method successively comprising the forming of the pads and the forming of the region, wherein the region is formed by nitriding of the substrate, the method comprising the successive steps of: depositing a layer on the substrate; forming portions on the layer; etching the parts of the layer which are not covered with the portions to form the pads; removing the portions; and nitriding the pads and the parts of the substrate which are not covered with the pads, wherein the nitriding step successively comprises: a first step of nitriding of the pads at a first temperature; and a second step of nitriding of the parts of the substrate which are not covered with

Abstract: A method of fabricating a light-scattering substrate, a light-scattering substrate fabricated by the same method, and an organic light-emitting device (OLED) including the same light-scattering substrate, in which a light-scattering layer of the light-scattering substrate can improve a light extraction efficiency. The method fabricates the light-scattering substrate by chemical vapor deposition, and includes loading a base substrate into a chamber, and forming a light-scattering layer on the base substrate by supplying a Ti source and an oxidizer including H2O into the chamber. In the process of forming the light-scattering layer, the mole ratio of the H2O with respect to the Ti is 10 or greater.

Abstract: An object of the present invention is to form a good thin film while suppressing generation of foreign substances in a low temperature region. Provided is a method of manufacturing a semiconductor device, including: (a) forming a thin film containing at least a predetermined element and carbon on a substrate by performing a cycle a predetermined number of times, the cycle including: (a-1) supplying a source gas containing the predetermined element and a halogen element to the substrate in a process container; and (a-2) supplying a reaction gas composed of carbon, nitrogen, and hydrogen to the substrate in the process container; and (b) modifying byproduct adhered to an inside of the process container by supplying a nitriding gas into the process container after (a).

Abstract: The invention relates to a method for correcting at least one error on wafers processed by at least one photolithographic mask, the method comprises: (a) measuring the at least one error on a wafer at a wafer processing site, and (b) modifying the at least one photolithographic mask by introducing at least one arrangement of local persistent modifications in the at least one photolithographic mask.

Abstract: Provided is a technique of controlling a work function of a metal film. A composite metal nitride film is formed on a substrate present in a process chamber by alternately supplying a first source and a second source to the substrate, wherein the first source contains a first metal element, the second source contains an ethyl ligand and a second metal element that is different from the first metal element, and a bond between the second metal element and a nitrogen element in the composite metal nitride film has crystallinity.

Abstract: The present disclosure suppresses oxidation of a base film on a substrate surface during the formation of an oxide film. A method of manufacturing a semiconductor device according to the present disclosure includes forming an initial layer including a predetermined element and having a thickness of several atomic layers on a substrate in a process chamber by supplying a predetermined-element-containing gas to the substrate, and forming an oxide film including the predetermined element on the initial layer by performing a cycle a predetermined number of times, the cycle including supplying a precursor gas including the predetermined element to the substrate in the process chamber and supplying an oxygen-containing gas and a hydrogen-containing gas to the substrate heated in the process chamber under a pressure lower than an atmospheric pressure.

Abstract: According to one embodiment, a method for processing a semiconductor device is provided including forming a final metal layer forming a passivation layer over the final metal layer and structuring the passivation layer and the final metal layer to form a patterned metal layer and a patterned passivation layer, wherein the patterned metal layer includes a pad region covered by the patterned passivation layer.

Abstract: A method for reducing dark current in image sensors comprises providing a backside illuminated image sensor wafer, depositing a first passivation layer on a backside of the backside illuminated image sensor wafer, depositing a plasma enhanced passivation layer on the first passivation layer and depositing a second passivation layer on the plasma enhanced passivation layer.

Abstract: Provided a method including forming a laminated film where a first film and a second film are laminated on a substrate by performing a cycle a predetermined number of times under a condition where a borazine ring structure in a fourth process gas is maintained. The cycle includes: (a) forming the first film by performing a first set a predetermined number of times, wherein the first set includes supplying a first process gas and supplying a second process gas to the substrate; and (b) forming the second film by performing a second set a predetermined number of times, wherein the second set includes supplying a third process gas and supplying the fourth process gas to the substrate.

Abstract: A method includes forming a first pad oxide layer and a second pad oxide layer over a first active region and a second active region, respectively, of a semiconductor substrate, forming a dielectric protection layer overlapping the first pad oxide layer, removing the second pad oxide layer, and forming a floating gate dielectric over the second active region. A floating gate layer is then formed to include a first portion over the dielectric protection layer, and a second portion over the floating gate dielectric. A planarization is performed on the first portion and the second portion of the floating gate layer. A blocking layer, a control gate layer, and a hard mask layer are formed over the second portion of the floating gate layer. The hard mask layer, the control gate layer, and the blocking layer are patterned to form a gate stack for a flash memory cell.

Abstract: In one embodiment, a method is proposed for etching a boron dope hardmask layer. The method includes flowing a process gas comprising at least CH4 into a processing chamber. Forming a plasma in the process chamber from the process gas and etching the boron doped hardmask layer in the presence of the plasma. In other embodiments, the process gas utilized to etch the boron doped hardmask layer includes CH4, Cl2, SF6 and O2.

Abstract: A sodium niobate powder includes sodium niobate particles having a shape of a cuboid and having a side average length of 0.1 ?m or more and 100 ?m or less, wherein at least one face of each of the sodium niobate particles is a (100) plane in the pseudocubic notation and a moisture content of the sodium niobate powder is 0.15 mass % or less. A method for producing a ceramic using the sodium niobate powder is provided. A method for producing a sodium niobate powder includes a step of holding an aqueous alkali dispersion liquid containing a niobium component and a sodium component at a pressure exceeding 0.1 MPa, a step of isolating a solid matter from the aqueous dispersion liquid after the holding, and a step of heat treating the solid matter at 500° C. to 700° C.

Abstract: Various embodiments provide transistors and fabrication methods. An exemplary transistor can include a silicon nitride layer disposed between a gate dielectric layer and a gate electrode layer. The silicon nitride layer can have a first surface in contact with the gate dielectric layer and a second surface in contact with the gate electrode layer. The second surface can include silicon atoms having a concentration higher than the first surface. A sidewall spacer can be formed on the semiconductor substrate along sidewalls of each of the gate electrode layer, the silicon nitride layer, and the gate dielectric layer. The disclosed transistor can have a reduced turn-on voltage with reduced power consumption.

Abstract: A first photosensitive organic insulating film (PO1) formed in contact with a passivation film (PL) covers the entire circumference of a stepped portion (TRE) at a surface of the passivation film PL formed by a topmost conductive layer (TCL) and has an outer circumferential edge (ED1) positioned, along the entire circumference, on the outer circumferential side with respect to the stepped portion (TRE). This can prevent the first photosensitive organic insulating film (PO1) from peeling off the passivation film (PL).

Abstract: A solution for manufacturing semiconductors is provided. An embodiment provides a chemical vapor deposition reactor, which includes a chemical vapor deposition chamber. A substrate holder located in the chemical vapor deposition chamber can be rotated about its own axis at a first angular speed, and a gas injection component located in the chemical vapor deposition chamber can be rotated about an axis of the gas injection component at a second angular speed. The angular speeds are independently selectable and can be configured to cause each point on a surface of a substrate wafer to travel in an epicyclical trajectory within a gas flow injected by the gas injection component. An angle between the substrate holder axis and the gas injection component axis and/or a distance between the substrate holder axis and the gas injection component axis can be controlled variables.

Abstract: A multi-mode thin film deposition apparatus including a reaction chamber, a carrying seat, a showerhead, an inert gas supplying source, a first gas inflow system and a second gas inflow system is provided. The carrying seat is disposed in the reaction chamber. The showerhead has a gas mixing room and gas holes disposed at a side of the gas mixing room. The gas mixing room is connected to the reaction chamber through the plurality of gas holes which faces the carrying seat. The first gas inflow system is connected to the reaction chamber and supplies a first process gas during a first thin film deposition process mode. The inert gas supplying source is connected to the gas mixing room for supplying an inert gas. The second gas inflow system is connected to the gas mixing room to supply a second process gas during a second thin film deposition process mode.

Abstract: A method of making a semiconductor device, the method includes forming an active region in a substrate. The method further includes forming a first gate structure over the active region, where the forming the first gate structure includes forming a first interfacial layer. An entirety of a top surface of the first interfacial layer is a curved convex surface. Furthermore, the method includes forming a first high-k dielectric over the first interfacial layer. Additionally, the method includes forming a first gate electrode over a first portion of the first high-k dielectric and surrounded by a second portion of the first high-k dielectric.

Abstract: Methods for depositing a material, such as a metal or a transition metal oxide, using an ALD (atomic layer deposition) process and resulting structures are disclosed. Such methods include treating a surface of a semiconductor structure periodically throughout the ALD process to regenerate a blocking material or to coat a blocking material that enables selective deposition of the material on a surface of a substrate. The surface treatment may reactivate a surface of the substrate toward the blocking material, may restore the blocking material after degradation occurs during the ALD process, and/or may coat the blocking material to prevent further degradation during the ALD process. For example, the surface treatment may be applied after performing one or more ALD cycles. Accordingly, the presently disclosed methods enable in situ restoration of blocking materials in ALD process that are generally incompatible with the blocking material and also enables selective deposition in recessed structures.

Abstract: Methods of forming an insulative element are described, including forming a first metal oxide material having a first dielectric constant, forming a second metal oxide material having a second dielectric constant different from the first, and heating at least portions of the structure to crystallize at least a portion of at least one of the first dielectric material and the second dielectric material. Methods of forming a capacitor are described, including forming a first electrode, forming a dielectric material with a first oxide and a second oxide over the first electrode, and forming a second electrode over the dielectric material. Structures including dielectric materials are also described.

Abstract: Methods for fabricating sublithographic, nanoscale microstructures in line arrays utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. Semiconductor structures may include self-assembled block copolymer materials in the form of lines of half-cylinders of a minority block matrix of a majority block of the block copolymer. The lines of half-cylinders may be within trenches in the semiconductor structures.

Abstract: Techniques are provided for manufacturing a light-emitting device having high internal quantum efficiency, consuming less power, having high luminance, and having high reliability. The techniques include forming a conductive light-transmitting oxide layer comprising a conductive light-transmitting oxide material and silicon oxide, forming a barrier layer in which density of the silicon oxide is higher than that in the conductive light-transmitting oxide layer over the conductive light-transmitting oxide layer, forming an anode having the conductive light-transmitting oxide layer and the barrier layer, heating the anode under a vacuum atmosphere, forming an electroluminescent layer over the heated anode, and forming a cathode over the electroluminescent layer. According to the techniques, the barrier layer is formed between the electroluminescent layer and the conductive light-transmitting oxide layer.

Abstract: Methods of scaling thickness of a gate dielectric structure that overlies a semiconductor substrate, methods of forming an integrated circuit, and integrated circuits are provided. A method of scaling thickness of a gate dielectric structure that overlies a semiconductor substrate includes providing the semiconductor substrate. An interfacial oxide layer is formed in or on the semiconductor substrate. A high-k dielectric layer is formed over the interfacial oxide layer. An oxygen reservoir is formed over at least a portion of the high-k dielectric layer. A sealant layer is formed over the oxygen reservoir. The semiconductor substrate including the oxygen reservoir disposed thereon is annealed to diffuse oxygen through the high-k dielectric layer and the interfacial oxide layer from the oxygen reservoir.

Abstract: The present disclosure provides A gate insulating layer comprising: a first silicon nitride film having a first thickness and a first content of N—H bonds; a second silicon nitride film having a second thickness and a second content of N—H bonds, disposed on the first silicon nitride film; and a third silicon nitride film having a third thickness and a third content of N—H bonds, disposed on the second silicon nitride film; wherein both the first thickness and the third thickness are less than the second thickness, both the N—H bonds in the first content and the third content are less than that in the second N—H bonds content, and a difference of the N—H bonds between the third content and the first content is no less than 5%. The present disclosure also provides a method for forming the above gate insulating layer.

Abstract: There is provided a dry film photoresist including a substrate layer constituted by a certain substrate, a resist layer disposed over the substrate layer, the resist layer including a plurality of layers, and a protective film layer disposed over the resist layer, the protective film layer protecting the resist layer. A photosensitive layer is positioned on a side of the substrate layer of the resist layer, the photosensitive layer having a dissolution rate to a certain developer that decreases by being exposed to light, and a non-photosensitive layer is positioned on a side of the protective film layer of the resist layer, the non-photosensitive layer being soluble to the developer. A dissolution rate of the non-photosensitive layer to the developer is higher than a dissolution rate of an unexposed portion in the photosensitive layer to the developer.

Abstract: The invention relates to a device and a method for depositing semiconductor layers, in particular made of a plurality of components on one or more substrates (21) contacting a susceptor (2), wherein process gases can be introduced into the process chamber (1) through flow channels (15, 16; 18) of a gas inlet organ (8), together with a carrier gas, said carrier gas permeating the process chamber (1) substantially parallel to the susceptor and exits through a gas outlet organ (7), wherein the products of decomposition build up the process gases as a coating at least in regions on the substrate surface and on the surface of the gas outlet organ (7) disposed downstream of the susceptor (2) at a distance (D) from the downstream edge (21) thereof.

Abstract: To provide a resin composition for sealing an optical semiconductor, which is a raw material for a sealing resin layer having good curability and excellent storage stability; preferably a raw material for a sealing resin layer further having excellent weather resistance. The surface sealant for an optical semiconductor of Embodiment 1 according to the present invention contains epoxy resin (a) having two or more epoxy groups in a molecule, and metal complex (b1) which contains at least one metal ion selected from the group consisting of Zn, Bi, Ca, Al, Cd, La and Zr, a tertiary amine capable of forming a complex with the metal ion and having no N—H bond and an anionic ligand having a molecular weight of 17 to 200, in which the surface sealant has a viscosity of 10 to 10000 mPa·s, as measured by E-type viscometer at 25° C. and 1.0 rpm.

Abstract: An object is to improve water resistance and reliability of a semiconductor device by reducing the degree of peeling of a film. In a semiconductor device, a first inorganic insulating layer, a semiconductor element layer, a second inorganic insulating layer, an organic insulating layer, and a third inorganic insulating layer are sequentially stacked over a substrate. The second inorganic insulating layer is in contact with the first inorganic insulating layer in an opening portion provided in the semiconductor element layer. The third inorganic insulating layer is in contact with the second inorganic insulating layer in an opening portion provided in the organic insulating layer. In a region where the second inorganic insulating layer and the third inorganic insulating layer are in contact with each other, the second inorganic insulating layer has a plurality of irregularities or openings.

Abstract: Semiconductor device manufacturing methods and methods of forming insulating material layers are disclosed. In one embodiment, a method of forming a composite insulating material layer of a semiconductor device includes providing a workpiece and forming a first sub-layer of the insulating material layer over the workpiece using a first plasma power level. A second sub-layer of the insulating material layer is formed over the first sub-layer of the insulating material layer using a second plasma power level, and the workpiece is annealed.

Abstract: A gate dielectric can be formed by depositing a first silicon oxide material by a first atomic layer deposition process. The thickness of the first silicon oxide material is selected to correspond to at least 10 deposition cycles of the first atomic layer deposition process. The first silicon oxide material is converted into a first silicon oxynitride material by a first plasma nitridation process. A second silicon oxide material is subsequently deposited by a second atomic layer deposition process. The second silicon oxide material is converted into a second silicon oxynitride material by a second plasma nitridation process. Multiple repetitions of the atomic layer deposition process and the plasma nitridation process provides a silicon oxynitride material having a ratio of nitrogen atoms to oxygen atoms greater than 1/3, which can be advantageously employed to reduce the leakage current through a gate dielectric.

Abstract: In order to extend the cycle of gas cleaning for a film-forming device, a method for manufacturing a semiconductor device includes: a substrate carry-in process for carrying a substrate into a processing chamber; a film forming process for laminating at least two types of films on the substrate in the processing chamber; a substrate carry-out process for carrying the film laminated substrate out from the processing chamber; an etching process for supplying an etching gas into the processing chamber while the substrate is not in the processing chamber after the substrate carry-out process. The etching process includes a first cleaning process for supplying a fluorine-containing gas activated by plasma excitation into the processing chamber as an etching gas; and a second cleaning process for supplying a fluorine-containing gas activated by heat into the processing chamber as an etching gas.

Abstract: Methods of depositing a film on a substrate surface include surface mediated reactions in which a film is grown over one or more cycles of reactant adsorption and reaction. In one aspect, the method is characterized by intermittent delivery of dopant species to the film between the cycles of adsorption and reaction.

Abstract: Disclosed herein is a formulation for depositing a cured underlayer for promoting the formation of self assembled structures. The underlayer comprises: (a) a polymer comprising at least one pendant vinyl ether monomer repeat unit having the structure, (I): wherein R is chosen from H, C1-C4 alkyl, or halogen, and W is a divalent group chosen from C1-C6 alkylene, C6-C20 arylene, benzylene, or C2-C20 alkyleneoxyalkylene; (ii) optional thermal acid generator; and (c) a solvent. The invention also relates to processes of forming a pattern using the underlayer.

Abstract: Atomic layer deposition (ALD) can be used to form a dielectric layer of zirconium aluminum oxynitride (ZrAlON) for use in a variety of electronic devices. Forming the dielectric layer may include depositing zirconium oxide using atomic layer deposition and precursor chemicals, followed by depositing aluminum nitride using precursor chemicals, and repeating. The dielectric layer may be used as the gate insulator of a MOSFET, a capacitor dielectric, and a tunnel gate insulator in flash memories.

Abstract: A method comprises depositing a first portion of a first material layer on a semiconductor structure. A first run of a post-treatment process is performed for modifying at least the first portion of the first material layer. After the first run of the post-treatment process, a second portion of the first material layer is deposited. The second portion is formed of substantially the same material as the first portion. After the deposition of the second portion of the first material layer, a second run of the post-treatment process is performed for modifying at least the second portion of the first material layer.

Abstract: Provided is a method of operating a film forming apparatus capable of suppressing generation of particles by improving an adhesion of a carbon film to surfaces of members which are formed of a quartz material and contact a processing space in a processing container. The method includes forming a carbon film on each of surfaces of a plurality of objects held by a holding unit in a processing container formed of a quartz material, wherein the method further includes forming an adhesion film to improve the adhesion of the carbon film, on surfaces of members which are formed of a quartz material and contact a processing space in the processing container. Accordingly, the adhesion of the carbon film to the surface of the member formed of a quartz material contacting the processing space in the processing container is improved, thereby suppressing generation of particles.

Abstract: A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a tunneling dielectric and a charge-trapping layer overlying the tunneling dielectric; depositing a first cap layer comprising an oxide over the dielectric stack; forming a second cap layer comprising a nitride over the first cap layer; patterning the first and second cap layers and the dielectric stack to form a gate stack of a memory device; removing the second cap layer; and performing an oxidation process to form a blocking oxide over the charge-trapping layer, wherein the oxidation process consumes the first cap layer. Other embodiments are also described.

Abstract: A method of depositing a film on substrates using an apparatus including a turntable mounting substrates, first and second process areas above the upper surface of the turntable provided with gas supplying portions, a separation gas supplying portion between the first and second process areas, and a separation area including depositing a first oxide film by rotating the turntable first turns while supplying a first reaction gas, the oxidation gas from the second gas supplying portion, and the separation gas; rotating at least one turn while supplying the separation gas from the first gas supplying portion and the separation gas supplying portion, and the oxidation gas from the second gas supplying portion; and rotating at least second turns to deposit a second oxide film while supplying a second reaction gas from the first gas supplying portion, the oxidation gas from the second gas supplying portion, and the separation gas.

Abstract: Some embodiments include methods of patterning a base. First and second masking features are formed over the base. The first and second masking features include pedestals of carbon-containing material capped with silicon oxynitride. A mask is formed over the second masking features, and the silicon oxynitride caps are removed from the first masking features. Spacers are formed along sidewalls of the first masking features. The mask and the carbon-containing material of the first masking features are removed. Patterns of the spacers and second masking features are transferred into one or more materials of the base to pattern said one or more materials. Some embodiments include patterned bases.

Abstract: An under layer film having excellent surface planarity is provided. In one aspect, the under layer film-forming composition for imprints includes a (meth)acrylic resin (A) containing an ethylenic unsaturated group (P) and a nonionic hydrophilic group (Q), and having a weight average molecular weight of 1,000 or larger; and a solvent (B), the resin (A) having an acid value of smaller than 1.0 mmol/g. In another aspect, the under layer film-forming composition for imprints includes a (meth)acrylic resin (A2) containing an ethylenic unsaturated group (P), and containing, as a nonionic hydrophilic group (Q), a cyclic substituent (Q2) having a carbonyl group in the cyclic structure thereof, with a weight average molecular weight of 1,000 or larger; and a solvent (B).

Abstract: Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material on the first region formed using the first precursor, wherein the first material is different from a second material formed on a second region of the substrate.

Abstract: Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.