Layers Formed Of Diverse Composition Or By Diverse Coating Processes Patents (Class 438/763)
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Publication number: 20110042801Abstract: A packaging scheme for MEMS device is provided. A method of packaging MEMS device in a semiconductor structure includes forming an insulation fence that surrounds the MEMS device on the semiconductor structure. The method further includes attaching a wafer of dielectric material to the insulation fence. The lid wafer, the insulation fence, and the semiconductor structure enclose the MEMS device.Type: ApplicationFiled: December 31, 2009Publication date: February 24, 2011Applicant: STMICROELECTRONICS, INC.Inventors: Venkatesh Mohanakrishnaswamy, Loi N. Nguyen, Venkata Ramana Yogi Mallela
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Patent number: 7893522Abstract: The present invention includes a substrate structural body having a high electrostatic chuck force at a low voltage even when an insulated board is used, and a method for manufacturing the substrate structural body. As the substrate structural body, there is provided a substrate structural body for attaining its fixing by an electrostatic chuck mechanism, comprising at least a first polycrystalline silicon film formed on the back surface of a substrate comprised of an insulating material or its back and side surfaces, wherein a top layer of part of the back surface or the back and side surfaces is of a first silicon insulating film.Type: GrantFiled: September 15, 2008Date of Patent: February 22, 2011Assignee: Oki Semiconductor Co., Ltd.Inventors: Shuichi Noda, Kimiaki Shimokawa
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Publication number: 20110039419Abstract: Methods for forming a dielectric layer on a substrate are provided herein. In some embodiments a method for forming a dielectric layer on a substrate may include exposing the substrate to a first source gas comprising a silicon (Si) precursor and an oxidizer for a first period of time to form a first layer comprising silicon and oxygen; and exposing the substrate to a second source gas comprising a metal precursor and the silicon precursor for a second period of time to form a second layer comprising silicon and a metal, where in the first layer and the second layer form the dielectric layer.Type: ApplicationFiled: July 14, 2010Publication date: February 17, 2011Applicant: APPLIED MATERIALS, INC.Inventors: Lucien Date, Paul William Turnbull
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Publication number: 20110034023Abstract: A silicon carbide (SiC) film for use in backend processing of integrated circuit manufacturing, is generated by including hydrogen in the reaction gas mixture. This SiC containing film is suitable for integration into etch stop layers, dielectric cap layers and hardmask layers in interconnects of integrated circuits.Type: ApplicationFiled: July 12, 2010Publication date: February 10, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Laura M. Matz, Ping Jiang, William Wesley Dostalik, Ting Tsui
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Publication number: 20110034036Abstract: Provided is a method of manufacturing a semiconductor device. In the method, after a thin liner is formed on a substrate on which a lower interconnection is formed, a silicon source is supplied to form a silicide layer under the liner by a reaction between the silicon source and the lower interconnection, and the silicide layer is nitrided and an etch stop layer is formed. Therefore, the lower interconnection is prevented from making contact with the silicon source, variations of the surface resistance of the lower interconnection can be prevented, and thus high-speed devices can be fabricated.Type: ApplicationFiled: July 28, 2010Publication date: February 10, 2011Applicant: ATTO CO., LTD.Inventor: Young Soo Kwon
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Patent number: 7883906Abstract: The use of a conductive bidimensional perovskite as an interface between a silicon, metal, or amorphous oxide substrate and an insulating perovskite deposited by epitaxy, as well as an integrated circuit and its manufacturing process comprising a layer of an insulating perovskite deposited by epitaxy to form the dielectric of capacitive elements having at least an electrode formed of a conductive bidimensional perovskite forming an interface between said dielectric and an underlying silicon, metal, or amorphous oxide substrate.Type: GrantFiled: March 3, 2010Date of Patent: February 8, 2011Assignees: STMicroelectronics S.A., Universite Francois RabelaisInventors: Ludovic Goux, Monique Gervais
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Patent number: 7883967Abstract: A nonvolatile semiconductor memory device includes a gate portion formed by laminating a tunnel insulating film, floating gate electrode, inter-poly insulating film and control gate electrode on a semiconductor substrate, and source and drain regions formed on the substrate. The tunnel insulating film has a three-layered structure having a silicon nitride film sandwiched between silicon oxide films. The silicon nitride film is continuous in an in-plane direction and has 3-coordinate nitrogen bonds and at least one of second neighboring atoms of nitrogen is nitrogen.Type: GrantFiled: July 24, 2006Date of Patent: February 8, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yuuichiro Mitani, Daisuke Matsushita, Ryuji Ooba, Isao Kamioka, Yoshio Ozawa
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Patent number: 7884022Abstract: Pitch multiplication is performed using a two step process to deposit spacer material on mandrels. The precursors of the first step react minimally with the mandrels, forming a barrier layer against chemical reactions for the deposition process of the second step, which uses precursors more reactive with the mandrels. Where the mandrels are formed of amorphous carbon and the spacer material is silicon oxide, the silicon oxide is first deposited by a plasma enhanced deposition process and then by a thermal chemical vapor deposition process. Oxygen gas and plasma-enhanced tetraethylorthosilicate (TEOS) are used as reactants in the plasma enhanced process, while ozone and TEOS are used as reactants in the thermal chemical vapor deposition process. The oxygen gas is less reactive with the amorphous carbon than ozone, thereby minimizing deformation of the mandrels caused by oxidation of the amorphous carbon.Type: GrantFiled: January 19, 2007Date of Patent: February 8, 2011Assignee: Round Rock Research, LLCInventors: Jingyi Bai, Gurtej S Sandhu, Shuang Meng
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Publication number: 20110027979Abstract: To provide a method of manufacturing a dielectric film having a high dielectric constant. In an embodiment of the present invention, an HfN/Hf laminated film is formed on a substrate on which a thin silicon oxide film is formed and a dielectric film of a metal nitride made of a mixture of Hf, Si, O and N is manufactured by annealing treatment. According to the present invention, it is possible to (1) reduce an EOT, (2) reduce a leak current to Jg=1.0×10?1 A/cm2 or less, (3) suppress hysteresis caused by the generation of fixed charges, and (4) prevent an increase in EOT even if heat treatment at 700° C. or more is performed and obtain excellent heat resistance.Type: ApplicationFiled: July 21, 2010Publication date: February 3, 2011Applicant: CANON ANELVA CORPORATIONInventors: Takuya Seino, Takashi Nakagawa, Naomu Kitano, Toru Tatsumi
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Patent number: 7879710Abstract: Methods for substrate processing are described. The methods include forming a material layer on a substrate. The methods include selecting constituents of a molecular masking layer (MML) to remove an effect of variations in the material layer as a result of substrate processing. The methods include normalizing the surface characteristics of the material layer by selectively depositing the MML on the material layer.Type: GrantFiled: December 29, 2006Date of Patent: February 1, 2011Assignee: Intermolecular, Inc.Inventors: Zachary Fresco, Chi-I Lang, Sandra G. Malhotra, Tony P. Chiang, Thomas R. Boussie, Nitin Kumar, Jinhong Tong, Anh Duong
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Publication number: 20110021036Abstract: A method of sealing an air gap in a layer of a semiconductor structure comprises providing a first layer of the semiconductor structure having at least one air gap for providing isolation between at least two conductive lines formed in the first layer. The at least one air gap extends into the first layer from a first surface of the first layer. The method further comprises forming a barrier layer of a barrier dielectric material over the first surface of the first layer and the at least one air gap. The barrier dielectric material is selected to have a dielectric constant less than 3.5 and to provide a barrier to prevent chemicals entering the at least one air gap.Type: ApplicationFiled: April 17, 2008Publication date: January 27, 2011Inventors: Greg Braecklmann, Marius Orlowski, Andreas Wild
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Publication number: 20110020999Abstract: Some embodiments include dielectric structures. The structures include first and second portions that are directly against one another. The first portion may contain a homogeneous mixture of a first phase and a second phase. The first phase may have a dielectric constant of greater than or equal to 25, and the second phase may have a dielectric constant of less than or equal to 20. The second portion may be entirely a single composition having a dielectric constant of greater than or equal to 25. Some embodiments include electrical components, such as capacitors and transistors, containing dielectric structures of the type described above. Some embodiments include methods of forming dielectric structures, and some embodiments include methods of forming electrical components.Type: ApplicationFiled: September 30, 2010Publication date: January 27, 2011Applicant: Micron Technology, Inc.Inventors: Noel Rocklein, Chris M. Carlson, Dave Peterson, Cunyu Yang, Praveen Vaidyanathan, Vishwanath Bhat
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Patent number: 7871926Abstract: A method for forming a structure includes forming at least one feature across a surface of a substrate. A nitrogen-containing dielectric layer is formed over the at least one feature. A first portion of the nitrogen-containing layer on at least one sidewall of the at least one feature is removed at a first rate and a second portion of the nitrogen-containing layer over the substrate adjacent to a bottom region of the at least one feature is removed at a second rate. The first rate is greater than the second rate. A dielectric layer is formed over the nitrogen-containing dielectric layer.Type: GrantFiled: October 22, 2007Date of Patent: January 18, 2011Assignee: Applied Materials, Inc.Inventors: Li-Qun Xia, Mihaela Balseanu, Victor Nguyen, Derek R. Witty, Hichem M'Saad, Haichun Yang, Xinliang Lu, Chien-Teh Kao, Mei Chang
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Publication number: 20110008970Abstract: The invention includes methods of forming isolation regions for semiconductor constructions. A hard mask can be formed and patterned over a semiconductor substrate, with the patterned hard mask exposing a region of the substrate. Such exposed region can be etched to form a first opening having a first width. The first opening is narrowed with a conformal layer of carbon-containing material. The conformal layer is punched through to expose substrate along a bottom of the narrowed opening. The exposed substrate is removed to form a second opening which joins to the first opening, and which has a second width less than the first width. The carbon-containing material is then removed from within the first opening, and electrically insulative material is formed within the first and second openings The electrically insulative material can substantially fill the first opening, and leave a void within the second opening.Type: ApplicationFiled: September 20, 2010Publication date: January 13, 2011Inventors: Ramakanth Alapati, Ardavan Niroomand, Gurtej S. Sandhu, Luan C. Tran
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Patent number: 7867914Abstract: An apparatus and method for forming an integrated barrier layer on a substrate is described. The integrated barrier layer comprises at least a first refractory metal layer and a second refractory metal layer. The integrated barrier layer is formed using a dual-mode deposition process comprising a chemical vapor deposition (CVD) step and a cyclical deposition step. The dual-mode deposition process may be performed in a single process chamber.Type: GrantFiled: June 29, 2007Date of Patent: January 11, 2011Assignee: Applied Materials, Inc.Inventors: Ming Xi, Michael Yang, Hui Zhang
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Publication number: 20110003481Abstract: It is made possible to restrain generation of defects at the time of insulating film formation. A method for manufacturing a semiconductor device, includes: placing a semiconductor substrate into an atmosphere, thereby forming a nitride film on a surface of the semiconductor substrate, the atmosphere containing a first nitriding gas nitriding the surface of the semiconductor substrate and a first diluent gas not actually reacting with the semiconductor substrate, the ratio of the sum of the partial pressure of the first diluent gas and the partial pressure of the first nitriding gas to the partial pressure of the first nitriding gas being 5 or higher, and the total pressure of the atmosphere being 40 Torr or lower.Type: ApplicationFiled: July 1, 2010Publication date: January 6, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Daisuke Matsushita, Koichi Muraoka, Koichi Kato, Yasushi Nakasaki, Yuichiro Mitani
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Publication number: 20110003482Abstract: Provided is a method of manufacturing a semiconductor device. In the method, an aluminium-containing insulation film is formed on an electrode film of a substrate by alternately repeating a process of supplying an aluminium precursor into a processing chamber in which the substrate is accommodated and exhausting the aluminium precursor from the processing chamber and a process of supplying an oxidizing or nitriding precursor into the processing chamber and exhausting the oxidizing or nitriding precursor from the processing chamber; and a high permittivity insulation film different from the aluminium-containing insulation film is formed on the aluminium-containing insulation film by alternately repeating a process of supplying a precursor into the processing chamber and exhausting the precursor from the processing chamber and a process of supplying an oxidizing precursor into the processing chamber and exhausting the oxidizing precursor from the processing chamber.Type: ApplicationFiled: June 28, 2010Publication date: January 6, 2011Applicant: HITACHI-KOKUSAI ELECTRIC INC.Inventors: Arito Ogawa, Sadayoshi Horii, Taketoshi SATO, Hideharu Itatani, Nobuyuki MISE, Osamu Tonomura
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Patent number: 7863199Abstract: The invention includes methods of forming particle-containing materials, and also includes semiconductor constructions comprising particle-containing materials. One aspect of the invention includes a method in which a first monolayer is formed across at least a portion of a semiconductor substrate, particles are adhered to the first monolayer, and a second monolayer is formed over the particles. Another aspect of the invention includes a construction containing a semiconductor substrate and a particle-impregnated conductive material over at least a portion of the semiconductor substrate. The particle-impregnated conductive material can include tungsten-containing particles within a layer which includes tantalum or tungsten.Type: GrantFiled: October 29, 2009Date of Patent: January 4, 2011Assignee: Micron Technology, Inc.Inventors: Garo J. Derderian, Gurtej S. Sandhu
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Patent number: 7863650Abstract: A process for fabricating a multilayer structure is provided as well as the structure itself. In accordance with one embodiment, the process includes growing a growth layer on a silicon substrate by epitaxial growth, forming at least one pattern from the growth layer, depositing an oxide layer on the silicon substrate, transferring a silicon active layer onto the oxide layer, forming a cavity in the silicon active layer oxide layer above the pattern, and growing a III-V material in the cavity.Type: GrantFiled: September 22, 2009Date of Patent: January 4, 2011Assignee: S.O.I. TEC Silicon on Insulator TechnologiesInventor: Fabrice Letertre
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Publication number: 20100327377Abstract: An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.Type: ApplicationFiled: June 26, 2009Publication date: December 30, 2010Inventors: Gilbert Dewey, Niloy Mukherjee, Matthew Metz, Jack T. Kavalieros, Nancy M. Zelick, Robert S. Chau
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Patent number: 7858531Abstract: A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising at least one transistor element. An etch stop layer is formed over the transistor element. A stressed first dielectric layer is formed over the etch stop layer. A protective layer adapted to reduce an intrusion of moisture into the first dielectric layer is formed over the first dielectric layer. At least one electrical connection to the transistor element is formed. At least a portion of the protective layer remains over the first dielectric layer after completion of the formation of the at least one electrical connection.Type: GrantFiled: January 22, 2008Date of Patent: December 28, 2010Assignee: Advanced Micro Devices, Inc.Inventors: Ralf Richter, Joerg Hohage, Michael Finken, Jana Schlott
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Patent number: 7859060Abstract: In one embodiment, the invention is a method and apparatus for fabricating an ultra thin silicon on insulator. One embodiment of a method for fabricating an ultra thin silicon on insulator includes providing a silicon layer, saturating the silicon layer with at least one reactant gas at a first temperature, the first temperature being low enough to substantially prevent the occurrence of any reactions involving the reactant gas, and raising the first temperature to a second temperature, the second temperature being approximately a dissociation temperature of the reactant gas.Type: GrantFiled: August 4, 2009Date of Patent: December 28, 2010Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Jakub Kedzierski, Raymond M. Sicina
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Patent number: 7858525Abstract: A method including introducing a fluorine-free organometallic precursor in the presence of a substrate; and forming a conductive layer including a moiety of the organometallic precursor on the substrate according to an atomic layer or chemical vapor deposition process. A method including forming an opening through a dielectric layer to a contact point; introducing a fluorine-free copper film precursor and a co-reactant; and forming a copper-containing seed layer in the opening. A system including a computer including a microprocessor electrically coupled to a printed circuit board, the microprocessor including conductive interconnect structures formed from fluorine-free organometallic precursor.Type: GrantFiled: March 30, 2007Date of Patent: December 28, 2010Assignee: Intel CorporationInventors: Juan E. Dominguez, Adrien R. Lavoie, John J. Plombon, Joseph H. Han, Harsono S. Simka, Bryan C. Hendrix, Gregory T. Stauf
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Patent number: 7855145Abstract: A gap filling method and a method for forming a memory device, including forming an insulating layer on a substrate, forming a gap region in the insulating layer, and repeatedly forming a phase change material layer and etching the phase change material layer to form a phase change material layer pattern in the gap region.Type: GrantFiled: April 13, 2007Date of Patent: December 21, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Il Lee, Choong-Man Lee, Sung-Lae Cho, Sang-Wook Lim, Hye-Young Park, Young-Lim Park
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Patent number: 7851294Abstract: A method for manufacturing a nanotube non-volatile memory cell is proposed. The method includes the steps of: forming a source electrode and a drain electrode, forming a nanotube implementing a conduction channel between the source electrode and the drain electrode, forming an insulated floating gate for storing electric charges by passivating conductive nanoparticles with passivation molecules and arranging a disposition of passivated conductive nanoparticles on the nanotube, the conductive nanoparticles being adapted to store the electric charges and being insulated by the passivation molecules from the nanotube, and forming a control gate coupled with the channel.Type: GrantFiled: September 8, 2006Date of Patent: December 14, 2010Assignee: STMicroelectronics, S.r.l.Inventors: Andrea Basco, Maria Viviana Volpe, Maria Fortuna Bevilacqua, Valeria Casuscelli
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Patent number: 7851380Abstract: The present invention relates to a process of making thin film electronic components and devices, such as thin film transistors, environmental barrier layers, capacitors, insulators and bus lines, where most or all of the layers are made by an atmospheric atomic layer deposition process.Type: GrantFiled: September 26, 2007Date of Patent: December 14, 2010Assignee: Eastman Kodak CompanyInventors: Shelby F. Nelson, David H. Levy, Lyn M. Irving, Peter J. Cowdery-Corvan, Diane C. Freeman, Carolyn R. Ellinger
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Patent number: 7842581Abstract: When a metal layer formed by reaction of a metal source and an oxygen (O2) source is deposited, oxidization of a conductive layer disposed under or on the metal layer can be reduced and/or prevented by a method of forming the metal layer and a method of fabricating a capacitor using the same. Between forming the conductive layer and the metal layer, and between forming the metal layer and the conductive layer, a cycle of supplying a metal source, purging, supplying an oxygen source, purging, plasma processing of reduction gas and purging is repeated at least once. In this case, the metal layer is formed by repeating a cycle of supplying a metal source, purging, supplying an oxygen source and purging.Type: GrantFiled: December 27, 2006Date of Patent: November 30, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Suk-Jin Chung, Jin-Yong Kim, Wan-Don Kim, Kwang-Hee Lee, Cha-Young Yoo
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Publication number: 20100283106Abstract: A semiconductor device in which a semiconductor layer is formed on an insulating substrate with a front-end insulating layer interposed between the semiconductor layer and the insulating substrate is provided which is capable of preventing action of an impurity contained in the insulating substrate on the semiconductor layer and of improving reliability of the semiconductor device. In a TFT (Thin Film Transistor), boron is made to be contained in a region located about 100 nm or less apart from a surface of the insulating substrate so that boron concentration decreases at an average rate being about 1/1000-fold per 1 nm from the surface of the insulating substrate toward the semiconductor layer.Type: ApplicationFiled: July 22, 2010Publication date: November 11, 2010Applicants: NEC CORPORATION, NEC LCD TECHNOLOGIES, LTD.Inventor: Shigeru MORI
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Patent number: 7824997Abstract: A method for micro-machining a varactor that is part of a membrane suspended MEMS tunable filter. In one non-limiting embodiment, the method includes providing a main substrate; depositing a membrane on the main substrate; depositing and patterning a plurality of sacrificial photoresist layers at predetermined times during the fabrication of the varactor; depositing metal layers that define a fabricated varactor structure enclosed within photoresist; coupling a carrier substrate to the fabricated structure opposite to the main substrate using a release layer; etching a central portion of the main substrate to expose the membrane; removing the carrier substrate by dissolving the release layer in a material that attacks the release layer but does not dissolve the photoresist; and removing the photoresist layers to provide a released varactor.Type: GrantFiled: March 27, 2008Date of Patent: November 2, 2010Assignee: EMAG Technologies, Inc.Inventors: Alexandros Margomenos, Linda P. B. Katehi, Yuxing Tang
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Patent number: 7825037Abstract: In accordance with the invention, there is a method of forming a nanochannel including depositing a photosensitive film stack over a substrate and forming a pattern on the film stack using interferometric lithography. The method can further include depositing a plurality of silica nanoparticles to form a structure over the pattern and removing the pattern while retaining the structure formed by the plurality of silica nanoparticles, wherein the structure comprises an enclosed nanochannel.Type: GrantFiled: October 16, 2006Date of Patent: November 2, 2010Assignee: STC.UNMInventors: Steven R. J. Brueck, Deying Xia
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Publication number: 20100273321Abstract: A system to form a wet soluble lithography layer on a semiconductor substrate includes providing the substrate, depositing a first layer comprising a first material on the substrate, and depositing a second layer comprising a second material on the substrate. In an embodiment, the first material comprises a different composition than the second material and one of the first layer and the second layer includes silicon.Type: ApplicationFiled: April 27, 2009Publication date: October 28, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien-Wei Wang, Ching-Yu Chang
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Patent number: 7820506Abstract: Some embodiments include dielectric structures. The structures include first and second portions that are directly against one another. The first portion may contain a homogeneous mixture of a first phase and a second phase. The first phase may have a dielectric constant of greater than or equal to 25, and the second phase may have a dielectric constant of less than or equal to 20. The second portion may be entirely a single composition having a dielectric constant of greater than or equal to 25. Some embodiments include electrical components, such as capacitors and transistors, containing dielectric structures of the type described above. Some embodiments include methods of forming dielectric structures, and some embodiments include methods of forming electrical components.Type: GrantFiled: October 15, 2008Date of Patent: October 26, 2010Assignee: Micron Technology, Inc.Inventors: Noel Rocklein, Chris M. Carlson, Dave Peterson, Cunyu Yang, Praveen Vaidyanathan, Vishwanath Bhat
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Patent number: 7816281Abstract: A method for manufacturing a semiconductor device includes the steps of forming a silicon oxide film on a silicon substrate, and forming a silicon nitride film on the silicon oxide film. The step of forming the silicon nitride film includes the steps of growing a first silicon layer having a thickness larger than a thickness of a monoatomic silicon layer, nitriding the first silicon layer to form a first silicon nitride layer, growing a second silicon layer on the first silicon layer on the first silicon nitride layer, and nitriding the second silicon oxide layer to form a second silicon nitride layer.Type: GrantFiled: March 18, 2008Date of Patent: October 19, 2010Assignee: Elpida Memory, Inc.Inventor: Motoyuki Kono
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Patent number: 7816278Abstract: An in-situ hybrid film deposition method for forming a high-k dielectric film on a plurality of substrates in a batch processing system. The method includes loading the plurality of substrates into a process chamber of the batch processing system, depositing by atomic layer deposition (ALD) a first portion of a high-k dielectric film on the plurality of substrates, after depositing the first portion, and without removing the plurality of substrates from the process chamber, depositing by chemical vapor deposition (CVD) a second portion of the high-k dielectric film on the first portion, and removing the plurality of substrates from the process chamber. The method can further include alternatingly repeating the deposition of the first and second portions until the high-k dielectric film has a desired thickness. The method can still further include pre-treating the substrates and post-treating the high-k dielectric film in-situ prior to the removing.Type: GrantFiled: March 28, 2008Date of Patent: October 19, 2010Assignee: Tokyo Electron LimitedInventors: Kimberly G. Reid, Anthony Dip
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Patent number: 7816280Abstract: A method of forming a multi-layered insulation film includes forming a first insulation layer using a first feed gas, the first insulation layer including methyl silsesquioxane (MSQ), forming a second insulation layer using a second feed gas, the second insulation layer including a polysiloxane compound having an Si—H group such that the second insulation layer is in contact with a top of the first insulation layer, and forming a third insulation layer including an inorganic material such that the third insulation layer is in contact with a top of the second insulation layer.Type: GrantFiled: January 15, 2009Date of Patent: October 19, 2010Assignee: NEC Electronics CorporationInventor: Tatsuya Usami
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Patent number: 7816215Abstract: A semiconductor device manufacturing method comprises: forming a gate insulative film on a semiconductor substrate by: forming a first nitride film on the substrate; forming a first oxide film and a second oxide film, the first oxide film being between the substrate and the first nitride film, the second oxide film being on the first nitride film; and nitriding the second oxide film to form, on the first nitride film, one of either: a second nitride film or an SiON film; and forming a gate electrode on the gate insulative film; wherein the equivalent oxide thickness of the gate insulative film is equal to or less than 1 nm.Type: GrantFiled: September 16, 2004Date of Patent: October 19, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Daisuke Matsushita, Koichi Muraoka, Seiji Inumiya, Koichi Kato, Kazuhiro Eguchi, Mariko Takayanagi, Yasushi Nakasaki
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Patent number: 7811944Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the aforementioned semiconductor device. The semiconductor device, in accordance with the principles of the present invention, may include a substrate, and a graded capping layer located over the substrate, wherein the graded capping layer includes at least two different layers, wherein first and second layers of the at least two different layers have different stress values.Type: GrantFiled: June 27, 2005Date of Patent: October 12, 2010Assignee: Agere Systems Inc.Inventors: Nace Rossi, Alvaro Maury
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Publication number: 20100255651Abstract: A semiconductor device including a multilayer dielectric film and a method for fabricating the semiconductor device are disclosed. The multilayer dielectric film includes a type-one dielectric film having a tetragonal crystalline structure, wherein the type-one dielectric film comprises a first substance. The multilayer dielectric film also comprises a type-two dielectric film also having a tetragonal crystalline structure, wherein the type-two dielectric film comprises a second substance different from the first substance and a dielectric constant of the type-two dielectric film is greater than a dielectric constant of the type-one dielectric film.Type: ApplicationFiled: December 10, 2009Publication date: October 7, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-yeol KANG, Jong-cheol LEE, Ki-vin LIM, Hoon-sang CHOI, Eun-ae CHUNG
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Patent number: 7807584Abstract: Example embodiments are directed to methods of forming a metallic oxide film using Atomic Layer Deposition while controlling the power reflected by a reactor. The method may include feeding metallic source gases, for example, first and second metallic source gases, and/or a reactant gas including oxygen into the reactor individually. One of the metallic source gases may include an amino-group or an alkoxy-group and another metallic source gas may include neither an amino-group nor an alkoxy-group. A plasma may be produced in the reactor from the reactant gas.Type: GrantFiled: June 22, 2007Date of Patent: October 5, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Ju-youn Kim, Seok-jun Won, Weon-hong Kim, Min-woo Song, Jung-min Park
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Patent number: 7807551Abstract: In a method for fabricating a flexible pixel array substrate, first, a release layer is formed on a rigid substrate. Next, on the release layer, a polymer film is formed, the adhesive strength between the rigid substrate and the release layer being higher than that between the release layer and the polymer film. The polymer film is formed by spin coating a polymer monomer and performing a curing process to form a polymer layer. Afterwards, a pixel array is formed on the polymer film. The polymer film with the pixel array formed thereon is separated from the rigid substrate.Type: GrantFiled: June 19, 2009Date of Patent: October 5, 2010Assignee: Industrial Technology Research InstituteInventors: Chin-Jen Huang, Jung-Fang Chang, Yih-Rong Luo, Yu-Hung Chen
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Publication number: 20100248460Abstract: A method of forming an information storage pattern, includes placing a semiconductor substrate in a process chamber, injecting first, second and third process gases into the process chamber during a first process to form a lower layer on the substrate based on a first injection time and/or a first pause time, injecting the second process gas into the process chamber during a second process, wherein the second process gas is injected into the process chamber during a first elimination time, injecting a fourth process gas together with the second and third process gases into the process chamber during a third process in accordance with a second injection time and/or a second pause time to form an upper layer on the lower layer, and injecting the second process gas into the process chamber during a fourth process, wherein the second process gas is injected into the process chamber during a second elimination.Type: ApplicationFiled: March 26, 2010Publication date: September 30, 2010Inventors: Jin-Il Lee, Urazaev Vladimir, Jin-Ha Jeong, Seung-Back Shin, Sung-Lae Cho, Hyeong-Geun An, Dong-Hyun Im, Jung-Hyeon Kim
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Publication number: 20100244206Abstract: A method of forming a device includes providing a substrate, forming an interfacial layer on the substrate, depositing a high-k dielectric layer on the interfacial layer, depositing an oxygen scavenging layer on the high-k dielectric layer and performing an anneal. A high-k metal gate transistor includes a substrate, an interfacial layer on the substrate, a high-k dielectric layer on the interfacial layer and an oxygen scavenging layer on the high-k dielectric layer.Type: ApplicationFiled: March 31, 2009Publication date: September 30, 2010Applicant: International Business Machines CorporationInventors: Huiming Bu, Michael P. Chudzik, Wei He, Rashmi Jha, Young-Hee Kim, Siddarth A. Krishnan, Renee T. Mo, Naim Moumen, Wesley C. Natzle
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Publication number: 20100237442Abstract: A shallow trench isolation structure is formed in a semiconductor substrate adjacent to an active semiconductor region. A selective self-assembling oxygen barrier layer is formed on the surface of the shallow trench isolation structure that includes a dielectric oxide material. The formation of the selective self-assembling oxygen barrier layer is selective in that it is not formed on the surface the active semiconductor region having a semiconductor surface. The selective self-assembling oxygen barrier layer is a self-assembled monomer layer of a chemical which is a derivative of alkylsilanes including at least one alkylene moiety. The silicon containing portion of the chemical forms polysiloxane, which is bonded to surface silanol groups via Si—O—Si bonds. The monolayer of the chemical is the selective self-assembling oxygen barrier layer that prevents diffusion of oxygen to a high dielectric constant material layer that is subsequently deposited as a gate dielectric.Type: ApplicationFiled: March 19, 2009Publication date: September 23, 2010Applicant: International Business Machines CorporationInventors: ZHENGWEN LI, ANTONIO L.P. ROTONDARO, MARK R. VISOKAY
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Publication number: 20100240208Abstract: Provided is a floating gate having multiple charge storage layers, a non-volatile memory device using the same, and a method of fabricating the floating gate and the non-volatile memory device, in which the multiple charge storage layers using metallic/semiconducting nano-particles is formed to thereby enhance a charge storage capacity of the memory device. The floating gate includes a polymer electrolytic film which is deposited on a tunneling oxide film, and is formed of at least one stage in which at least one thin film is deposited on each stage, and at least one metal nano-particle layer which is self-assembled on the upper surface of each stage of the polymer electrolytic film and on which a number of nano-particles for trapping charges are formed. The floating gate is made by self-assembling the nano-particles on the polymer electrolytic film, and thus can be fabricated without undergoing a heat treatment process at high temperature.Type: ApplicationFiled: June 1, 2010Publication date: September 23, 2010Applicant: KOOKMIN UNIVERSITY INDUSTRY ACADEMY COOPERATION FOUNDATIONInventors: JANG-SIK LEE, JINHAN CHO, JAEGAB LEE
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Patent number: 7795156Abstract: Disclosed is a producing method of a semiconductor device comprising a step of forming a tunnel insulating film of a flash device comprising a first nitridation step of forming a first silicon oxynitride film by nitriding a silicon oxide film formed on a semiconductor silicon base by one of plasma nitridation and thermal nitridation, the plasma nitridation carrying out nitridation process by using a gas activated by plasma discharging a first gas including a first compound which has at least a nitrogen atom in a chemical formula thereof, and the thermal nitridation carrying out nitridation process using heat by using a second gas including a second compound which has at least a nitrogen atom in a chemical formula thereof, and a second nitridation step of forming a second silicon oxynitride film by nitriding the first silicon oxynitride film by the other of the plasma nitridation and the thermal nitridation.Type: GrantFiled: October 31, 2005Date of Patent: September 14, 2010Assignee: Hitachi Kokusai Electric Inc.Inventors: Tadashi Terasaki, Akito Hirano, Masanori Nakayama, Unryu Ogawa
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Patent number: 7790613Abstract: A semiconductor device includes: a semiconductor substrate; a memory cell selection transistor that is formed on the semiconductor substrate and has a source and a drain; a contact plug; a polysilicon interlayer film that is formed above the memory cell selection transistor and has a cylinder-shaped through-hole; and a storage capacity part that is formed in the through-hole and is connected to the source and the drain of the memory cell selection transistor via the contact plug, wherein a boundary between a bottom and a side wall of the through-hole has a curved surface.Type: GrantFiled: January 28, 2008Date of Patent: September 7, 2010Assignee: Elpida Memory, Inc.Inventor: Mitsuhiro Horikawa
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Publication number: 20100221923Abstract: A semiconductor device includes: a structure comprising at least two heterogeneous layers having different stress levels; and a stress relief layer disposed between the two heterogeneous layers to relive a difference in the stress levels. The stress relief layer may include: a first layer formed over a first heterogeneous layer; a second layer formed over the first layer; and a third layer formed between the second layer and a second heterogeneous layer.Type: ApplicationFiled: March 31, 2010Publication date: September 2, 2010Inventors: Hyun AHN, Jeong-Hoon PARK
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Publication number: 20100213518Abstract: An ultra-violet (UV) protection layer is formed over a semiconductor workpiece before depositing a UV curable dielectric layer. The UV protection layer prevents UV light from reaching and damaging underlying material layers and electrical devices. The UV protection layer comprises a layer of silicon doped with an impurity, wherein the impurity comprises O, C, H, N, or combinations thereof. The UV protection layer may comprise SiOC:H, SiON, SiN, SiCO:H, combinations thereof, or multiple layers thereof, as examples.Type: ApplicationFiled: May 5, 2010Publication date: August 26, 2010Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zhen-Cheng Wu, Yung-Cheng Lu, Chung-Chi Ko
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Patent number: 7781270Abstract: Electronic devices integrated on a single substrate and a method for fabricating the same are provided. The method includes providing a substrate, and forming at least two electronic devices on the substrate, wherein the at least two electronic devices are selected from a thin film transistor, a memory, a diode, a capacitor, a resistor and an inductor. The at least two electronic devices are formed from a plurality of film layers, each film layer is formed over the substrate at the same time, and at least one layer of the film layers is formed by printing process.Type: GrantFiled: December 11, 2006Date of Patent: August 24, 2010Assignee: Industrial Technology Research InstituteInventor: Zing-Way Pei
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Patent number: 7776396Abstract: An improved vapor-phase deposition method and apparatus for the application of multilayered films/coatings on substrates is described. The method is used to deposit multilayered coatings where the thickness of an oxide-based layer in direct contact with a substrate is controlled as a function of the chemical composition of the substrate, whereby a subsequently deposited layer bonds better to the oxide-based layer. The improved method is used to deposit multilayered coatings where an oxide-based layer is deposited directly over a substrate and an organic-based layer is directly deposited over the oxide-based layer. Typically, a series of alternating layers of oxide-based layer and organic-based layer are applied.Type: GrantFiled: April 21, 2005Date of Patent: August 17, 2010Assignee: Applied Microstructures, Inc.Inventors: Boris Kobrin, Jeffrey D. Chinn, Romuald Nowak, Richard C. Yi