Abstract: A method is provided for treating a leadframe comprising copper or copper alloy to enhance adhesion of molding compound to it. The leadframe is oxidized in an oxidation treatment bath to form copper oxide on the surface of the leadframe. It is then dipped in a complexing or chelating agent to enhance the purity of the copper oxide formed. Thereafter, the leadframe is cleaned with an acid to remove any contaminants remaining on the leadframe.

Abstract: A method of making a device includes forming at least one anodizable metal layer over at least one of an electrode or a semiconductor device, forming a plurality of pores in the anodizable metal layer by anodization of the anodizable metal layer to expose a portion of the electrode or semiconductor device, and filling at least one pore with a rewritable material such that at least some of the rewritable material is in electrical contact with the electrode or semiconductor device.

Abstract: A method of manufacturing the semiconductor device is provided, which provides a prevention for a “dug” of a silicon substrate caused by the etching in regions except a region for forming a film during a removal of the film with a chemical solution. A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a first silicon oxide film on a surface of a silicon substrate or on a surface of a gate electrode when a silicon nitride film for a dummy side wall is etched off, to provide a protection for such surfaces, and then etching a portion of the silicon nitride film with a chemical solution, and then a second oxide film for supplementing a simultaneously-etched portion of the first silicon oxide film is formed, and eventually performing an etching for completely removing the silicon nitride film for the dummy side wall.

Abstract: A process for forming a patterned thin film structure on a substrate is disclosed. A pattern is printed with a material, such as a masking coating or an ink, on the substrate, the pattern being such that, in one embodiment, the desired thin film structures will be formed in the areas where the printed material is not present, i.e., a negative image of thin film structure to be formed is printed. In another embodiment, the pattern is printed with a material that is difficult to strip from the substrate, and the desired thin film structures will be formed in the areas where the printed material is present, i.e., a positive image of the thin film structure is printed. The thin film material is deposited on the patterned substrate, and the undesired area is stripped, leaving behind the patterned thin film structures.

Abstract: Methods and structures relating to the formation of mixed SAMs for preventing undesirable growth or nucleation on exposed surfaces inside a reactor are described. A mixed SAM can be formed on surfaces for which nucleation is not desired by introducing a first SAM precursor having molecules of a first length and a second SAM precursor having molecules of a second length shorter than the first. Examples of exposed surfaces for which a mixed SAM can be provided over include reactor surfaces and select surfaces of integrated circuit structures, such as insulator and dielectric layers.

Abstract: A non-volatile memory device is provided in which quantum dots are embedded in an oxide thin film formed on a substrate. A conventional Si CMOS process can be used to manufacture the non-volatile memory device in a cost-effective way. Also, a photonic device and an electronic/photonic device, which can store a light signal or emit a stored signal as light, can be produced on a Si wafer in a cost-effective manner.

Abstract: A first resist film is formed on a substrate, and first pattern exposure is performed such that the first resist film is irradiated with exposure light through a first mask. Then, the first resist film is developed, thereby forming a first resist pattern out of the first resist film. Subsequently, a nano-carbon material is attached to the surface of the first resist pattern, and then a second resist film is formed on the substrate including the first resist pattern. Thereafter, second pattern exposure is performed such that the second resist film is irradiated with exposure light through a second mask. Then, the second resist film is developed, thereby forming a second resist pattern out of the second resist film.

Abstract: A chemical vapor deposition method such as an atomic-layer-deposition method for forming a patterned thin film includes applying a deposition inhibitor material to a substrate. The deposition inhibitor material is a hydrophilic polymer that is soluble in an aqueous solution comprising at least 50 weight % water and has an acid content of less than 2.5 meq/g of polymer. The deposition inhibitor material is patterned simultaneously or subsequently to its application to the substrate, to provide selected areas of the substrate effectively not having the deposition inhibitor material. A thin film is substantially deposited only in the selected areas of the substrate not having the deposition inhibitor material.

Abstract: In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nMOS and pMOS transistors), carrier mobility is enhanced or otherwise regulated through the use of layering various stressed films over either the nMOS or pMOS transistor (or both), depending on the properties of the layer and isolating stressed layers from each other and other structures with an additional layer in a selected location. Thus both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.

Abstract: A method for forming a laminated structure including an amorphous carbon film on an underlying layer includes forming an initial layer containing Si—C bonds on a surface of the underlying layer, by supplying an organic silicon gas onto the underlying layer; and forming the amorphous carbon film by thermal film formation on the underlying layer with the initial layer formed on the surface thereof, by supplying a film formation gas containing a hydrocarbon compound gas onto the underlying layer.

Abstract: A method for encapsulating a micro component positioned on and/or in a substrate, including the following steps: depositing at least one sacrificial material covering the micro component, making a cap covering the sacrificial material, removing the sacrificial material via at least one opening formed through the cap, forming a cavity in which the micro component is positioned, depositing, on the cap, at least one layer of plugging material capable of plugging the opening, localized deposition of a portion of mechanically reinforcing material of the cap, covering at least the cap.

Abstract: A transistor formed on a monocrystalline Si wafer is temporarily transferred onto a first temporary supporting substrate. The first temporarily supporting substrate is heat-treated at high heat so as to repair crystal defects generated in a transistor channel of the monocrystalline Si wafer when transferring the transistor. The transistor is then made into a chip and transferred onto a TFT substrate. In order to transfer the transistor which has been once separated from the monocrystalline Si wafer, a different method from a stripping method utilizing ion doping is employed.

Abstract: A method of preventing the formation of cracks on the backside of a silicon (Si) semiconductor chip or wafer during the processing thereof. Also provided is a method for inhibiting the propagation of cracks, which have already formed in the backside of a silicon chip during the processing thereof and prior to the joining thereto of a substrate during the fabrication of an electronic package. The methods entail either treating the backside with a wet etch, or alternatively, applying a protective film layer thereon prior to forming an electronic package incorporating the chip or wafer.

Abstract: Some embodiments include methods of forming isolation regions in which spin-on material (for example, polysilazane) is converted to a silicon dioxide-containing composition. The conversion may utilize one or more oxygen-containing species (such as ozone) and a temperature of less than or equal to 300° C. In some embodiments, the spin-on material is formed within an opening in a semiconductor material to form a trenched isolation region. Other dielectric materials may be formed within the opening in addition to the silicon dioxide-containing composition formed from the spin-on material. Such other dielectric materials may include silicon dioxide formed by chemical vapor deposition and/or silicon dioxide formed by high-density plasma chemical vapor deposition.

Abstract: The method for forming wavelike coherent nanostructures by irradiating a surface of a material by a homogeneous flow of ions is disclosed. The rate of coherency is increased by applying preliminary preprocessing steps.

Abstract: A process for forming a patterned thin film structure on a substrate or in-mold decoration film is disclosed. A pattern is printed with a material, such as a masking coating or ink, on the substrate, the pattern being such that, in one embodiment, the desired structures will be formed in the areas where the printed material is not present, i.e., a negative image of thin film structure to be formed is printed. In another embodiment, the pattern is printed with a material that is difficult to strip from the substrate, and the desired thin film structures will be formed in the areas where the printed material is present, i.e., a positive image of the thin film structure is printed. The thin film material is deposited on the patterned substrate, and the undesired area is stripped, leaving behind the patterned thin film structure.

Abstract: A method of forming a conformal dielectric film having Si—N bonds on a semiconductor substrate by plasma enhanced chemical vapor deposition (PECVD) includes: introducing a nitrogen- and hydrogen-containing reactive gas and a rare gas into a reaction space inside which a semiconductor substrate is placed; applying RF power to the reaction space; and introducing a hydrogen-containing silicon precursor as a first precursor and a hydrocarbon gas as a second precursor in pulses into the reaction space wherein a plasma is excited, thereby forming a conformal dielectric film doped with carbon and having Si—N bonds on the substrate.

Abstract: Electronic apparatus and methods of forming the electronic apparatus include a gallium lanthanide oxide film for use in a variety of electronic systems. The gallium lanthanide oxide film may be structured as one or more monolayers. The gallium lanthanide oxide film may be formed using atomic layer deposition.

Abstract: The present disclosure is related to a dielectric layer comprising a rare-earth aluminate (RExAl2-xO3 with 0<x<2) and having a perovskite crystalline structure, wherein the rare-earth aluminate comprises a rare-earth element having an atomic number higher than or equal to 63 and lower than or equal to 71. The disclosure also relates to method of manufacturing of a dielectric stack and a dielectric stack comprising said rare-earth aluminate dielectric layer and further comprising a template stack comprising at least an upper template layer, wherein the upper template layer has a perovskite structure, and wherein the upper template layer is underlying and in contact with the rare-earth aluminate dielectric layer. In a preferred embodiment the dielectric stack further comprises a lower template layer having a crystalline structure, wherein the lower template layer is underlying and in contact with the upper template layer.

Abstract: A method for forming a semiconductor structure includes forming a plurality of features across a surface of a substrate, with at least one space being between two adjacent features. A first dielectric layer is formed on the features and within the at least one space. A portion of the first dielectric layer interacts with a reactant derived from a first precursor and a second precursor to form a first solid product. The first solid product is decomposed to substantially remove the portion of the first dielectric layer. A second dielectric layer is formed to substantially fill the at least one space.

Abstract: Multiple sequential processes are conducted in a reaction chamber to form ultra high quality silicon-containing compound layers, including silicon nitride layers. In a preferred embodiment, a silicon layer is deposited on a substrate using trisilane as the silicon precursor. A silicon nitride layer is then formed by nitriding the silicon layer. By repeating these steps, a silicon nitride layer of a desired thickness is formed.

Abstract: A zinc oxide (ZnO) film is fabricated. Metal-organic chemical vapor deposition (MOCVD) is used to obtain the film with few defects, high integrity and low cost through an easy procedure. The ZnO film above a silicon substrate has a matching crystal orientation to the substrate. Thus, the ZnO film is fit for ultraviolet light-emitting diodes (UV LED), solar cells and related laser devices.

Abstract: Disclosed herein is a high-quality group III-nitride semiconductor thin film and group III-nitride semiconductor light emitting device using the same. To obtain the group III-nitride semiconductor thin film, an AlInN buffer layer is formed on a (1-102)-plane (so called r-plane) sapphire substrate by use of a MOCVD apparatus under atmospheric pressure while controlling a temperature of the substrate within a range from 850 to 950 degrees Celsius, and then, GaN-based compound, such as GaN, AlGaN or the like, is epitaxially grown on the buffer layer at a high temperature. The group III-nitride semiconductor light emitting device is fabricated by using the group III-nitride semiconductor thin film as a base layer.

Abstract: A method of forming a micromagnetic device on a substrate including forming a first insulating layer above the substrate, a first seed layer above the first insulating layer, a first conductive winding layer above the first seed layer, and a second insulating layer above the first conductive winding layer. The method also includes forming a first magnetic core layer above the second insulating layer, a third insulating layer above the first magnetic core layer, and a second magnetic core layer above the third insulating layer. The method still further includes forming a fourth insulating layer above the second magnetic core layer, a second seed layer above the fourth insulating layer, and a second conductive winding layer above the second seed layer and in vias to the first conductive winding layer. The first and second conductive winding layers form a winding for the micromagnetic device.

Abstract: The present invention relates to an organic/inorganic hybrid thin film passivation layer comprising an organic polymer passivation layer prepared by a UV/ozone curing process and an inorganic thin film passivation layer for blocking moisture and oxygen transmission of an organic electronic device fabricated on a substrate and improving gas barrier property of a plastic substrate; and a fabrication method thereof. Since the organic/inorganic hybrid thin film passivation layer of the present invention converts the surface polarity of an organic polymer passivation layer into hydrophilic by using the UV/ozone curing process, it can improve the adhesion strength between the passivation layer interfaces, increase the light transmission rate due to surface planarization of the organic polymer passivation layer, and enhance gas barrier property by effectively blocking moisture and oxygen transmission.

Abstract: An atomic layer deposition-deposited silicon dioxide/metal oxide-nanolaminate, comprising at least one layer of silicon dioxide and at least one layer of a metal oxide, and having a wet etch rate in an etchant, said wet etch rate being either greater or smaller than both a wet etch rate of a film of silicon dioxide and a wet etch rate of a film of said metal oxide in said etchant. Also provided is a method for manufacturing the same.

Abstract: A method of forming a micro pattern in a semiconductor device includes: forming an target layer, a hard mask layer and first sacrificial patterns over a semiconductor substrate on which a cell gate region, a selective transistor region and a periphery circuit region are defined; forming an insulating layer and a second sacrificial layer on the hard mask layer and the first sacrificial patterns; removing the insulating layer and the second sacrificial layer formed in the selective transistor region and the periphery circuit region; performing the first etch process so as to allow the second sacrificial layer formed in the cell gate region to remain on the insulating layer between the first sacrificial patterns for forming second sacrificial patterns; removing the insulating layer placed on the first sacrificial patterns and between the first and second sacrificial patterns in the cell gate region; etching the hard mask layer using the second etch process utilizing the first and second sacrificial patterns as t

Abstract: The present invention comprises a method of reducing photoresist mask collapse when the photoresist mask is dried after immersion development. As feature sizes continue to shrink, the capillary force of water used to rinse a photoresist mask approaches the point of being greater than adhesion force of the photoresist to the ARC. When the capillary force exceeds the adhesion force, the features of the mask may collapse because the water pulls adjacent features together as the water dries. By depositing a hermetic oxide layer over the ARC before depositing the photoresist, the adhesion force may exceed the capillary force and the features of the photoresist mask may not collapse.

Abstract: A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.

Abstract: A method of forming a dielectric layer on a further layer of a semiconductor device is disclosed. The method comprises depositing a dielectric precursor compound and a further precursor compound over the further layer, the dielectric precursor compound comprising a metal ion from the group consisting of Yttrium and the Lanthanide series elements, and the further precursor compound comprising a metal ion from the group consisting of group IV and group V metals; and chemically converting the dielectric precursor compound and the further precursor compound into a dielectric compound and a further compound respectively, the further compound self-assembling during said conversion into a plurality of nanocluster nuclei within the dielectric layer formed from the first dielectric precursor compound. The nanoclusters may be dielectric or metallic in nature. Consequently, a dielectric layer is formed that has excellent charge trapping capabilities.

Abstract: Methods of processing films on substrates are provided. In one aspect, the methods comprise treating a patterned low dielectric constant film after a photoresist is removed form the film by depositing a thin layer comprising silicon, carbon, and optionally oxygen and/or nitrogen on the film. The thin layer provides a carbon-rich, hydrophobic surface for the patterned low dielectric constant film. The thin layer also protects the low dielectric constant film from subsequent wet cleaning processes and penetration by precursors for layers that are subsequently deposited on the low dielectric constant film.

Abstract: A patternable adhesive film is formed in a double-layered structure of an adhesive layer having patternability and an adhesive layer having both adhesion and developability. Thus, the double-layered patternable adhesive film can effectively have both patternability and adhesion.

Abstract: A method of forming silicon oxide includes depositing a silicon nitride-comprising material over a substrate. The silicon nitride-comprising material has an elevationally outermost silicon nitride-comprising surface. Such surface is treated with a fluid that is at least 99.5% H2O by volume. A polysilazane-comprising spin-on dielectric material is formed onto the H2O-treated silicon nitride-comprising surface. The polysilazane-comprising spin-on dielectric material is oxidized to form silicon oxide. Other implementations are contemplated.

Abstract: A disclosed selective etching method comprises mixing a polymer with carbon nanotubes, applying the mixture to an etching target layer to form a carbon nanotube-polymer composite layer, forming a hard mask by patterning the carbon nanotube-polymer composite layer, such that a part of the etching target layer is selectively exposed, and selectively etching the etching target layer exposed through the hard mask. The polymer preferably includes a photoresist. Also disclosed is a method for forming an isolation structure of a memory device using the selective etching method.

Abstract: A method of forming an integrated circuit structure includes forming an opening in a substrate, with the opening extending from a top surface of the substrate into the substrate. The opening is filled with a filling material until a top surface of the filling material is substantially level with the top surface of the substrate. A device is formed over the top surface of the substrate, wherein the device includes a storage opening adjoining the filling material. A backside of the substrate is grinded until the filling material is exposed. The filling material is removed from the channel until the storage opening of the device is exposed.

Abstract: A high-k dielectric film, a method of forming the high-k dielectric film, and a method of forming a related semiconductor device are provided. The high-k dielectric film includes a bottom layer of metal-silicon-oxynitride having a first nitrogen content and a first silicon content and a top layer of metal-silicon-oxynitride having a second nitrogen content and a second silicon content. The second nitrogen content is higher than the first nitrogen content and the second silicon content is higher than the first silicon content.

Abstract: A silicon-containing insulating film is formed on a target substrate by CVD, in a process field to be selectively supplied with a first process gas including di-iso-propylaminosilane gas and a second process gas including an oxidizing gas or nitriding gas. The film is formed by performing a plurality of times a cycle alternately including first and second steps. The first step performs supply of the first process gas, thereby forming an adsorption layer containing silicon on a surface of the target substrate. The second performs supply of the second process gas, thereby oxidizing or nitriding the adsorption layer on the surface of the target substrate. The second step includes an excitation period of supplying the second process gas to the process field while exciting the second process gas by an exciting mechanism.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of etch mask patterns over an etch target layer, each of the etch mask patterns including a first hard mask, a first pad layer, and a second pad layer, forming spacers on both sidewalls of the etch mask patterns, the spacers including a material substantially the same as that of the first pad layer, forming a second hard mask over the resulting substrate structure until gaps between the etch mask patterns are filled, the second hard mask including a material different from that of the first hard mask but substantially the same as that of the second pad layer, planarizing the second hard mask until the first pad layer is exposed, removing the first pad layer and the spacers, and etching the etch target layer using the remaining first and second hard masks as an etch barrier layer.

Abstract: Disclosed is a stress buffer structure intended to be disposed adjacent a face of a semiconductor substrate. The stress buffer structure includes at least one polymer layer formed on the face of the semiconductor substrate and a plurality of metal plates disposed over the polymer layer, wherein the metal plates is physically and electrically isolated from the bond pads of the semiconductor substrate. The disclosed stress buffer structure provides protection to semiconductor components that are sensitive to stress. Also disclosed are semiconductor packages having the disclosed stress buffer structure and the methods of making the semiconductor packages.

Abstract: A method of forming a conformal dielectric film having Si—N bonds on a semiconductor substrate by plasma enhanced chemical vapor deposition (PECVD) includes: introducing a nitrogen- and hydrogen-containing reactive gas and an additive gas into a reaction space inside which a semiconductor substrate is placed; applying RF power to the reaction space; and introducing a hydrogen-containing silicon precursor in pulses into the reaction space wherein a plasma is excited, thereby forming a conformal dielectric film having Si—N bonds on the substrate.

Abstract: A semiconductor die and a related method of processing a semiconductor wafer are disclosed in which a first interlayer insulator having a recess region of varying configuration and defining a scribe line is associated with at least one protective layer formed with a characterizing inclined side surface.

Abstract: Embodiments of semiconductor devices are provided. In one embodiment, the semiconductor device includes a substrate, an etch stop layer formed on the substrate, an adhesion promotion layer formed directly on the etch stop layer, and a dielectric layer formed directly on the adhesion promotion layer. The etch stop layer may include silicon, carbon, and nitrogen. The dielectric layer may include silicon, oxygen, and carbon. The adhesion promotion layer may include carbon, oxygen, and nitrogen. An example of an adhesion promotion layer includes polyimide.

Abstract: Films having high hermeticity and a low dielectric constant can be used as copper diffusion barrier films, etch stop films, CMP stop films and other hardmasks during IC fabrication. Hermetic films can protect the underlying layers, such as layers of metal and dielectric, from exposure to atmospheric moisture and oxygen, thereby preventing undesirable oxidation of metal surfaces and absorption of moisture by a dielectric. Specifically, a bi-layer film having a hermetic bottom layer composed of hydrogen doped carbon and a low dielectric constant (low-k) top layer composed of low-k silicon carbide (e.g., high carbon content hydrogen doped silicon carbide) can be employed. Such bi-layer film can be deposited by PECVD methods on a partially fabricated semiconductor substrate having exposed layers of dielectric and metal.

Abstract: A method of manufacturing a semiconductor device including a substrate; an insulating film formed thereon; a first semiconductor layer where strain is induced in the directions parallel to the surface of the substrate, the first semiconductor layer being on the insulating film; a source region and a drain region formed in the first semiconductor layer; and a gate layered body formed of a gate insulating film and a gate electrode on the first semiconductor layer is disclosed. The method includes the steps of (a) forming a second semiconductor layer by epitaxial growth on the first semiconductor layer; (b) heating the second semiconductor layer; and (c) removing the second semiconductor layer. The second semiconductor layer is different in lattice constant in an in-plane direction from the first semiconductor layer. Step (b) induces the strain in the first semiconductor layer by exposing the surface of the second semiconductor layer to energy lines.

Abstract: The present disclosure describes methods for preparing semiconductor structures, comprising forming a Ge layer on a semiconductor substrate using an admixture of (a) (GeH3)2CH2 and Ge2H6; (b) GeH3CH3 and Ge2H6; or (c) (GeH3)2CH2, GeH3CH3 and Ge2H6, wherein in all cases, Ge2H6 is in excess. The disclosure further provides semiconductor structures formed according to the methods of the invention as well as compositions comprising an admixture of (GeH3)2CH2 and/or GeH3CH3 and Ge2H6 in a ratio of between about 1:5 and 1:30. The methods herein provide, and the semiconductor structures provide, Ge layers formed on semiconductor substrates having threading dislocation density below 105/cm2 which can be useful in semiconductor devices.

Abstract: A nitrided region is formed on a surface of a polysilicon layer by a nitriding treatment wherein plasma of a processing gas is generated by introducing microwaves into a processing chamber by a planar antenna having a plurality of slots. Then, a CVD oxide film or the like is formed on the nitrided region and after patterning the polysilicon layer and the like after the prescribed shape, and then, a thermal oxide film is formed by thermal oxidation on exposed side walls and the like of the polysilicon layer by having the nitrided region as an oxidation barrier layer. Thus, generation of bird's beak can be suppressed in the process at a temperature lower than the temperature in a conventional process.

Abstract: A method for fabricating a dielectric layer structure includes providing a substrate, blanketly forming a low-k dielectric layer of an interlayer dielectric (ILD) layer, the low-k dielectric layer covering at least a first metal interconnect structure on the substrate, blanketly forming a single tensile film of the ILD layer having a thickness of 200-1500 angstroms on the low-k dielectric layer, and performing a moisture preventing treatment on the single tensile film. The single tensile layer possesses a stress comparative to a stress of the low-k dielectric layer and a hydrophobic characteristic that prevents itself from absorbing moisture.

Abstract: A method of manufacturing a semiconductor device comprising: forming a p type region and an n type region in a main surface of a semiconductor substrate, the p type region and the n type region being insulated from each other with an element-isolation region; forming a first insulating film on the p type region and on the n type region, the first insulating film being made of any one of a silicon oxide film and a silicon oxynitride film; forming a lanthanum oxide film on the first insulating film on the p type region; forming a second insulating film both on the lanthanum oxide film on the p type region and on the first insulating film on the n type region, the second insulating film containing any one of hafnium and zirconium; and forming a titanium nitride film on the second insulating film, the titanium nitride film satisfying TixNy where x/y<1.

Abstract: A method, in one embodiment, can include forming a tunnel oxide layer on a substrate. In addition, the method can include depositing via atomic layer deposition a first layer of silicon nitride over the tunnel oxide layer. Note that the first layer of silicon nitride includes a first silicon richness. The method can also include depositing via atomic layer deposition a second layer of silicon nitride over the first layer of silicon nitride. The second layer of silicon nitride includes a second silicon richness that is different than the first silicon richness.

Abstract: In one embodiment, a method is provided for forming stress in a semiconductor device. The semiconductor device may include a gate structure on a substrate, wherein the gate structure includes at least one dummy material that is present on a gate conductor. A conformal dielectric layer is formed atop the semiconductor device, and an interlevel dielectric layer is formed on the conformal dielectric layer. The interlevel dielectric layer may be planarized to expose at least a portion of the conformal dielectric layer that is atop the gate structure, in which the exposed portion of the conformal dielectric layer may be removed to expose an upper surface of the gate structure. The upper surface of the gate structure may be removed to expose the gate conductor. A stress inducing material may then be formed atop the at least one gate conductor.