Abstract: A method including forming a non-planar conducting channel of a multi-gate device on a substrate, the channel including a height dimension defined from a base at a surface of the substrate; modifying less than an entire portion of the channel; and forming a gate stack on the channel, the gate stack including a dielectric material and a gate electrode. An apparatus including a non-planar multi-gate device on a substrate including a channel including a height dimension defining a conducting portion and an oxidized portion and a gate stack disposed on the channel, the gate stack including a dielectric material and a gate electrode.

Abstract: A novel material is provided. A composite oxide semiconductor includes a first region and a second region. The first region contains indium. The second region contains an element M (the element M is one or more of Ga, Al, Hf, Y, and Sn). The first region and the second region are arranged in a mosaic pattern. The composite oxide semiconductor further includes a third region. The element M is gallium. The first region contains indium oxide or indium zinc oxide. The second region contains gallium oxide or gallium zinc oxide. The third region contains zinc oxide.

Abstract: The present invention is a method for manufacturing a bonded SOI wafer, including: preparing, as a base wafer, a silicon single crystal wafer whose initial interstitial oxygen concentration is 15 ppma or more ('79ASTM); forming a silicon oxide film on a surface of the base wafer by heating the base wafer in an oxidizing atmosphere such that a feeding temperature at which the base wafer is fed into a heat treatment furnace for the heat treatment is 800° C. or more, and the base wafer is heated at the feeding temperature or higher; bonding the base wafer to the bond wafer with the silicon oxide film interposed therebetween; and thinning the bonded bond wafer to form an SOI layer. This provides a method for manufacturing a bonded SOI wafer by a base oxidation method which suppresses the formation of oxide precipitates in a base wafer while suppressing slip dislocation.

Abstract: Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibiting reduced parasitic resistance relative to conventional devices. In some example embodiments, the source/drain regions each includes a thin p-type silicon or germanium or SiGe deposition with the remainder of the source/drain material deposition being p-type germanium or a germanium alloy (e.g., germanium:tin or other suitable strain inducer, and having a germanium content of at least 80 atomic % and 20 atomic % or less other components). In some cases, evidence of strain relaxation may be observed in the germanium rich cap layer, including misfit dislocations and/or threading dislocations and/or twins. Numerous transistor configurations can be used, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors), as well as strained and unstrained channel structures.

Abstract: The substrate processing method according to an exemplary embodiment includes a low temperature dissolving processing and an etching processing. The low temperature dissolving processing dissolves oxygen in an alkaline aqueous solution cooled to a predetermined temperature lower than the room temperature. The etching processing etches a substrate by supplying the alkaline aqueous solution in which oxygen is dissolved to the substrate.

Abstract: The present invention relates to a micro LED grip body for vacuum-sucking micro LEDs. More particularly, the present invention relates to a micro LED grip body provided with a mask below a porous member to increase vacuum pressure for vacuum-sucking micro LEDs such that the micro LEDs are transferred without deviation.

Abstract: A method of forming an oxide layer on an exposed surface of a semiconductor device which contains a p-n junction is disclosed, the method comprising: immersing the exposed surface of the semiconductor device in an electrolyte; producing an electric field in the semiconductor device such that the p-n junction is forward-biased and the exposed surface is anodic; and electrochemically oxidizing the exposed surface to form an oxide layer.

Abstract: The present disclosure relates to a semiconductor device including an oxygen gettering layer between a group III-V compound semiconductor layer and a dielectric layer, and a method of fabricating the semiconductor device. The semiconductor device may include a compound semiconductor layer; a dielectric layer disposed on the compound semiconductor layer; and an oxygen gettering layer interposed between the compound semiconductor layer and the dielectric layer. The oxygen gettering layer includes a material having a higher oxygen affinity than a material of the compound semiconductor layer.

Abstract: Semiconductor devices having copper interconnects and methods for their fabrication are provided. In one embodiment, a semiconductor device is fabricated with a copper interconnect on substrate such as an FEOL processed substrate. The method includes forming a copper layer on a substrate. The copper layer is formed from grains. The copper layer is modified such that the modified copper layer has an average grain size of larger than about 0.05 microns. In the method, the modified copper layer is etched to form a line along the substrate and a via extending upwards from the line.

Abstract: A semiconductor device is provided that includes a diffusion barrier layer between a compound semiconductor layer and a dielectric layer, as well as a method of fabricating the semiconductor device, such that the semiconductor device includes a compound semiconductor layer; a dielectric layer; and a diffusion barrier layer including an oxynitride formed between the compound semiconductor layer and the dielectric layer.

Abstract: This invention provides a semiconductor having a functionalized surface that is resistant to oxidation and that includes a plurality of atoms of a Group III element bonded to organic groups. The functionalized surface has less than or equal to about 1 atom of the Group III element bonded to an oxygen atom per every 1,000 atoms of the Group III element bonded to the organic groups, as determined using X-ray photoelectron spectroscopy. This invention also provides a method of functionalizing the surface and includes the step of halogenating at least one of the plurality of atoms of the Group III element to form halogenated Group III element atoms. The method also includes the step of reacting at least one of the halogenated Group III element atoms with a Grignard reagent to form a bond between the at least one Group III element atom and the organic groups.

Abstract: A gate dielectric can be formed by depositing a first silicon oxide material by a first atomic layer deposition process. The thickness of the first silicon oxide material is selected to correspond to at least 10 deposition cycles of the first atomic layer deposition process. The first silicon oxide material is converted into a first silicon oxynitride material by a first plasma nitridation process. A second silicon oxide material is subsequently deposited by a second atomic layer deposition process. The second silicon oxide material is converted into a second silicon oxynitride material by a second plasma nitridation process. Multiple repetitions of the atomic layer deposition process and the plasma nitridation process provides a silicon oxynitride material having a ratio of nitrogen atoms to oxygen atoms greater than 1/3, which can be advantageously employed to reduce the leakage current through a gate dielectric.

Abstract: Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber enclosing a substrate support, a remote plasma source, and a showerhead. A substrate heater can be mounted in the substrate support. A transport system moves the substrate support and is capable of positioning the substrate. The plasma system may be used to generate activated hydrogen species. The activated hydrogen species can be used to etch/clean semiconductor oxide surfaces such as silicon oxide or germanium oxide.

Abstract: A method of manufacturing a semiconductor device may include: forming active patterns of pillar-shapes upward protruding from a substrate, the active patterns fully doped with dopants of one conductivity type; forming a gate electrode extending in one direction, the gate electrode overlapped with sidewalls of the active patterns; and forming a gate insulating layer between the gate electrode and the active patterns.

Abstract: Method for crystal growth from a surfactant of a metal-nonmetal (MN) compound, including the procedures of providing a seed crystal, introducing atoms of a first metal to the seed crystal thus forming a thin liquid metal wetting layer on a surface of the seed crystal, setting a temperature of the seed crystal below a minimal temperature required for dissolving MN molecules in the wetting layer and above a melting point of the first metal, each one of the MN molecules being formed from an atom of a second metal and an atom of a first nonmetal, introducing the MN molecules which form an MN surfactant monolayer, thereby facilitating a formation of the wetting layer between the MN surfactant monolayer and the surface of the seed crystal, and regulating a thickness of the wetting layer, thereby growing an epitaxial layer of the MN compound on the seed crystal.

Abstract: Embodiments of the present invention provide a method for surface treatment on a metal oxide and a method for preparing a thin film transistor. The method for surface treatment on a metal oxide comprises: utilizing plasma to perform a surface treatment on a device to be processed; the plasma comprises a mixture gas of an F-based gas and O2, and the device to be processed is a metal oxide or a manufactured article coated with a metal oxide. The embodiments provided by the present invention can reduce the contact resistance between a metal oxide and other electrodes, and improve the effect of ohmic contact of the metal oxide.

Abstract: A patterned substrate is provided having at least two mesa surface portions, and a recessed surface located beneath and positioned between the at least two mesa surface portions. A Group III nitride material is grown atop the mesa surface portions of the patterned substrate and atop the recessed surface. Growth of the Group III nitride material is continued merging the Group III nitride material that is grown atop the mesa surface portions. When the Group III nitride material located atop the mesa surface portions merge, the Group III nitride material growth on the recessed surface ceases. The merged Group III nitride material forms a first Group III nitride material structure, and the Group III nitride material formed in the recessed surface forms a second material structure. The first and second material structures are disjoined from each other and are separated by an air gap.

Abstract: A method to fabricate monolithically-integrated optoelectronic module apparatuses (100) comprising at least two series-interconnected optoelectronic components (104, 106, 108). The method includes deposition and scribing on an insulating substrate or superstate (110) of a 3-layer stack in order (a, b, c) or (c, b, a) comprising: (a) back-contact electrodes (122, 124, 126, 128), (b) semiconductive layer (130), and (c) front-contact components (152, 154, 156, 158). Via holes (153, 155, 157) are drilled so that heat of the drilling process causes a metallization at the surface of said via holes that renders conductive the semi-conductive layer's surface (132, 134, 136, 138) of said via holes, thereby establishing series-interconnecting electrical paths between optoelectronic components (104, 106, 108) by connecting first front-contact components (154, 156) to second back-contact electrodes (124, 126).

Abstract: An improved insulated gate field effect device is obtained by providing a substrate desirably comprising a III-V semiconductor, having a further semiconductor layer on the substrate adapted to contain the channel of the device between spaced apart source-drain electrodes formed on the semiconductor layer. A dielectric layer is formed on the semiconductor layer. A sealing layer is formed on the dielectric layer and exposed to an oxygen plasma. A gate electrode is formed on the dielectric layer between the source-drain electrodes. The dielectric layer preferably comprises gallium-oxide and/or gadolinium-gallium oxide, and the oxygen plasma is preferably an inductively coupled plasma. A further sealing layer of, for example, silicon nitride is desirably provided above the sealing layer. Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.

Abstract: Methods and apparatus for forming nitrogen-containing layers are provided herein. In some embodiments, a method includes placing a substrate having a first layer disposed thereon on a substrate support of a process chamber; heating the substrate to a first temperature; and exposing the first layer to an RF plasma formed from a process gas comprising ammonia (NH3) to transform the first layer into a nitrogen-containing layer, wherein the plasma has an ion energy of less than about 8 eV.

Abstract: A nitride semiconductor light-emitting device includes an n-type nitride semiconductor layer, a V pit generation layer, an intermediate layer, a multiple quantum well light-emitting layer, and a p-type nitride semiconductor layer provided in this order. The multiple quantum well light-emitting layer is a layer formed by alternately stacking a barrier layer and a well layer having a bandgap energy smaller than that of the barrier layer. A V pit is partly formed in the multiple quantum well light-emitting layer, and an average position of starting point of the V pit is located in the intermediate layer.

Abstract: A method of cleaning a SiC semiconductor includes the steps of forming an oxide film at the surface of a SiC semiconductor, and removing the oxide film. At the step of forming an oxide film, an oxide film is formed using ozone water having a concentration greater than or equal to 30 ppm. The forming step preferably includes the step of heating at least one of the surface of the SiC semiconductor and the ozone water. Thus, there can be obtained a method of cleaning a SiC semiconductor that can exhibit cleaning effect on the SiC semiconductor.

Abstract: A semiconductor device has an active layer, a first semiconductor layer of first conductive type, an overflow prevention layer disposed between the active layer and the first semiconductor layer, which is doped with impurities of first conductive type and which prevents overflow of electrons or holes, a second semiconductor layer of first conductive type disposed at least one of between the active layer and the overflow prevention layer and between the overflow prevention layer and the first semiconductor layer, and an impurity diffusion prevention layer disposed between the first semiconductor layer and the active layer, which has a band gap smaller than those of the overflow prevention layer, the first semiconductor layer and the second semiconductor layer and which prevents diffusion of impurities of first conductive type.

Abstract: A vapor deposition reactor includes a chamber filled with a first material, and at least one reaction module in the chamber. The reaction module may be configured to make a substrate pass the reaction module through a relative motion between the substrate and the reaction module. The reaction module may include an injection unit for injecting a second material to the substrate. A method for forming thin film includes positioning a substrate in a chamber, filling a first material in the chamber, moving the substrate relative to a reaction module in the chamber, and injecting a second material to the substrate while the substrate passes the reaction module.

Abstract: Provided are processes for the low temperature deposition of silicon-containing films using carbosilane precursors containing a carbon atom bridging at least two silicon atoms. Certain methods comprise providing a substrate; in a PECVD process, exposing the substrate surface to a carbosilane precursor containing at least one carbon atom bridging at least two silicon atoms; exposing the carbosilane precursor to a low-powered energy sourcedirect plasma to provide a carbosilane at the substrate surface; and densifying the carbosilanestripping away at least some of the hydrogen atoms to provide a film comprising SiC. The SiC film may be exposed to the carbosilane surface to a nitrogen source to provide a film comprising SiCN.

Abstract: A method for fabrication of a III-nitride film over a silicon wafer that includes forming control joints to allow for overall stress relief in the III-nitride film during the growth thereof.

Abstract: A method of fabricating semiconductor devices is disclosed. The method comprises providing a substrate with a plurality of epitaxial layers mounted on the substrate and separating the substrate from the plurality of epitaxial layers while the plurality of epitaxial layers is intact. This preserves the electrical, optical, and mechanical properties of the plurality of epitaxial layers.

Abstract: A method of fabricating a silicon-containing oxide layer that includes providing a chemical oxide layer on a surface of a semiconductor substrate, removing the chemical oxide layer in an oxygen-free environment at a temperature of 1000° C. or greater to provide a bare surface of the semiconductor substrate, and introducing an oxygen-containing gas at a flow rate to the bare surface of the semiconductor substrate for a first time period at the temperature of 1000° C. The temperature is then reduced to room temperature during a second time period while maintaining the flow rate of the oxygen containing gas to provide a silicon-containing oxide layer having a thickness ranging from 0.5 ? to 10 ?.

Abstract: The present invention discloses a method and a device for preparing a compound semiconductor film. The method comprises the steps of: providing a substrate above at least an evaporation source in a vacuum condition; heating a source material contained in the evaporation source so that the source material is vapor-deposited on the substrate; and taking out the substrate under protection of an inert gas. The substrate may be rotated around an axis of a plane where the evaporation source is positioned, and the substrate is tilted by a predetermined angle with respect to the plane. The compound semi-conductive film thus prepared has a uniform thickness with a larger area. The method provides a simplified process and enhanced efficiency.

Abstract: This invention provides methods that permit wafers to be loaded and unloaded in a gas-phase epitaxial growth chamber at high temperatures. Specifically, this invention provides a method for moving wafers or substrates that can bathe a substrate being moved in active gases that are optionally temperature controlled. The active gases can act to limit or prevent sublimation or decomposition of the wafer surface, and can be temperature controlled to limit or prevent thermal damage. Thereby, previously-necessary temperature ramping of growth chambers can be reduced or eliminated leading to improvement in wafer throughput and system efficiency.

Abstract: Methods for deposition of silicon carbide films on a substrate surface are provided. The methods include the use of vapor phase carbosilane precursors and may employ plasma enhanced atomic layer deposition processes. The methods may be carried out at temperatures less than 600° C., for example between about 23° C. and about 200° C. or at about 100° C. This silicon carbide layer may then be densified to remove hydrogen content. Additionally, the silicon carbide layer may be exposed to a nitrogen source to provide reactive N—H groups, which can then be used to continue film deposition using other methods. Plasma processing conditions can be used to adjust the carbon, hydrogen and/or nitrogen content of the films.

Abstract: The present invention belongs to the technical field of semiconductor materials and specifically relates to a method for cleaning & passivizing gallium arsenide (GaAs) surface autologous oxide and depositing an Al2O3 dielectric. This method includes: use a new-type of sulfur passivant to react with the autologous oxide on the GaAs surface to clean it and generate a passive sulfide film to separate the GaAs from the outside environment, thus preventing the GaAs from oxidizing again; further cleaning the residuals such as autologous oxides and sulfides on the GaAs surface through the pretreatment reaction of the reaction source trimethyl aluminum (TMA) of the Al2O3 ALD with the GaAs surface, and then deposit high-quality Al2O3 dielectric through ALD as the gate dielectric which fully separates the GaAs from the outside environment. The present invention features a simple process and good effects, and can provide preconditions for manufacturing the GaAs devices.

Abstract: Methods for selectively depositing high quality epitaxial material include introducing pulses of a silicon-source containing vapor while maintaining a continuous etchant flow. Epitaxial material is deposited on areas of a substrate, such as source and drain recesses. Between pulses, the etchant flow continues such that lower quality epitaxial material may be removed, as well as any non-epitaxial material that may have been deposited. The pulse of silicon-source containing vapor may be repeated until a desired thickness of epitaxial material is selectively achieved in semiconductor windows, such as recessed source/drain regions.

Abstract: A silicon carbide substrate is prepared. By exposing the silicon carbide substrate to an atmosphere having a nitrogen dioxide concentration greater than or equal to 2 ?g/m3, an oxide film is formed on the silicon carbide substrate.

Abstract: A method of fabricating a silicon-containing oxide layer that includes providing a chemical oxide layer on a surface of a semiconductor substrate, removing the chemical oxide layer in an oxygen-free environment at a temperature of 1000° C. or greater to provide a bare surface of the semiconductor substrate, and introducing an oxygen-containing gas at a flow rate to the bare surface of the semiconductor substrate for a first time period at the temperature of 1000° C. The temperature is then reduced to room temperature during a second time period while maintaining the flow rate of the oxygen containing gas to provide a silicon-containing oxide layer having a thickness ranging from 0.5 ? to 10 ?.

Abstract: The present invention provides a method of producing a silicon carbide semiconductor substrate in which a silicon carbide buffer layer doped with germanium and a semiconductor device layer are sequentially laminated on the buffer layer, a silicon carbide semiconductor substrate obtained by the method and a silicon carbide semiconductor in which electrodes are disposed on the silicon carbide semiconductor substrate.

Abstract: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, a conductive layer is located within a dielectric layer and a top surface of the conductive layer has either a recess, a convex surface, or is planar. An alloy layer overlies the conductive layer and is a silicide alloy having a first material from the conductive layer and a second material of germanium, arsenic, tungsten, or gallium.

Abstract: The invention provides methods which can be applied during the epitaxial growth of two or more layers of Group III-nitride semiconductor materials so that the qualities of successive layer are successively improved. In preferred embodiments, surface defects interact with a protective layer of a protective material to form amorphous complex regions capable of preventing the further propagation of defects and dislocations. The invention also includes semiconductor structures fabricated by these methods.

Abstract: A method of electrically activating a structure having one or more graphene layers formed on a silicon carbide layer includes subjecting the structure to an oxidation process so as to form a silicon oxide layer disposed between the silicon carbide layer and a bottommost of the one or more graphene layers, thereby electrically activating the bottommost graphene layer.

Abstract: In one embodiment, a method for forming a non-conductive crystalline oxide layer on an AlSb crystal includes heat treating an AlSb crystal in a partial vacuum atmosphere at a temperature conducive for air adsorbed molecules to desorb, surface molecule groups to decompose, and elemental Sb to evaporate from a surface of the AlSb crystal and exposing the AlSb crystal to an atmosphere comprising oxygen to form a crystalline oxide layer on the surface of the AlSb crystal. In another embodiment, a method for forming a non-conductive crystalline oxide layer on an AlSb crystal includes heat treating an AlSb crystal in a non-oxidizing atmosphere at a temperature conducive for decomposition of an amorphous oxidized surface layer and evaporation of elemental Sb from the AlSb crystal surface and forming stable oxides of Al and Sb from residual surface oxygen to form a crystalline oxide layer on the surface of the AlSb crystal.

Abstract: This invention provides methods that permit wafers to be loaded and unloaded in a gas-phase epitaxial growth chamber at high temperatures. Specifically, this invention provides a method for moving wafers or substrates that can bathe a substrate being moved in active gases that are optionally temperature controlled. The active gases can act to limit or prevent sublimation or decomposition of the wafer surface, and can be temperature controlled to limit or prevent thermal damage. Thereby, previously-necessary temperature ramping of growth chambers can be reduced or eliminated leading to improvement in wafer throughput and system efficiency.

Abstract: This invention provides apparatus, protocols, and methods that permit wafers to be loaded and unloaded in a gas-phase epitaxial growth chamber at high temperatures. Specifically, this invention provides a device for moving wafers or substrates that can bath a substrate being moved in active gases that are optionally temperature controlled. The active gases can act to limit or prevent sublimation or decomposition of the wafer surface, and can be temperature controlled to limit or prevent thermal damage. Thereby, previously-necessary temperature ramping of growth chambers can be reduced or eliminated leading to improvement in wafer throughput and system efficiency.

Abstract: A method and apparatus for the deposition of thin films is described. In embodiments, systems and methods for epitaxial thin film formation are provided, including systems and methods for forming binary compound epitaxial thin films. Methods and systems of embodiments of the invention may be used to form direct bandgap semiconducting binary compound epitaxial thin films, such as, for example, GaN, InN and AlN, and the mixed alloys of these compounds, e.g., (In, Ga)N, (Al, Ga)N, (In, Ga, Al)N. Methods and apparatuses include a multistage deposition process and system which enables rapid repetition of sub-monolayer deposition of thin films.

Abstract: A method of growing non-polar m-plane III-nitride film, such as GaN, AlN, AlGaN or InGaN, wherein the non-polar m-plane III-nitride film is grown on a suitable substrate, such as an m-SiC, m-GaN, LiGaO2 or LiAlO2 substrate, using metalorganic chemical vapor deposition (MOCVD). The method includes performing a solvent clean and acid dip of the substrate to remove oxide from the surface, annealing the substrate, growing a nucleation layer, such as aluminum nitride (AlN), on the annealed substrate, and growing the non-polar m-plane III-nitride film on the nucleation layer using MOCVD.

Abstract: A manufacturing method for a silicon carbide semiconductor device is disclosed. It includes an etching method in which an Al film and Ni film are laid on an SiC wafer in this order and wet-etched, whereby a two-layer etching mask is formed in which Ni film portions overhang Al film portions. Mesa grooves are formed by dry etching by using this etching mask.

Abstract: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer.

Abstract: A channel layer (40) for forming a portion of a carrier path between a source electrode (100) and a drain electrode (110) is formed on a drift layer (30). The channel layer (40) includes Ge granular crystals formed on the drift layer (30), and a cap layer covering the Ge granular crystals.

Abstract: A plasma oxidation method includes the steps of: generating oxygen-containing plasma with a process gas containing oxygen; applying a bias voltage to a substrate placed on a stage; and radiating positive ions and negative ions in the oxygen-containing plasma onto the substrate so as to perform plasma oxidation of the substrate while controlling a bias potential of the substrate in such a manner that a maximum value Vmax and a minimum value Vmin of the bias potential and a plasma potential Vp satisfy a following relationship: Vmin<Vp<Vmax.

Abstract: A silicon carbide semiconductor device having a MOS structure includes: a substrate; a channel area in the substrate; a first impurity area; a second impurity area; a gate insulating film on the channel area; and a gate on the gate insulating film. The channel area provides an electric current path. The channel area and the gate insulating film have an interface therebetween. The interface includes a dangling bond, which is terminated by a hydrogen atom or a hydroxyl. The interface has a hydrogen concentration equal to or larger than 2.6×1020 cm?3.

Abstract: A method of fabricating templated semiconductor nanowires on a surface of a semiconductor substrate for use in semiconductor device applications is provided. The method includes controlling the spatial placement of the semiconductor nanowires by using an oxygen reactive seed material. The present invention also provides semiconductor structures including semiconductor nanowires. In yet another embodiment, patterning of a compound semiconductor substrate or other like substrate which is capable of forming a compound semiconductor alloy with an oxygen reactive element during a subsequent annealing step is provided. This embodiment provides a patterned substrate that can be used in various applications including, for example, in semiconductor device manufacturing, optoelectronic device manufacturing and solar cell device manufacturing.