Abstract: A method for treatment of the surface of a CdZnTe (CZT) crystal that provides a native dielectric coating to reduce surface leakage currents and thereby, improve the resolution of instruments incorporating detectors using CZT crystals. A two step process is disclosed, etching the surface of a CZT crystal with a solution of the conventional bromine/methanol etch treatment, and after attachment of electrical contacts, passivating the CZT crystal surface with a solution of 10 w/o NH4F and 10 w/o H2O2 in water.

Abstract: A deposition method includes forming a nucleation layer over a substrate, forming a layer of a first substance at least one monolayer thick chemisorbed on the nucleation layer, and forming a layer of a second substance at least one monolayer thick chemisorbed on the first substance. The chemisorption product of the first and second substance may include silicon and nitrogen. The nucleation layer may comprise silicon nitride. Further, a deposition method may include forming a first part of a nucleation layer on a first surface of a substrate and forming a second part of a nucleation layer on a second surface of the substrate. A deposition layer may be formed on the first and second parts of the nucleation layer substantially non-selectively on the first part of the nucleation layer compared to the second part. The first surface may be a surface of a borophosphosilicate glass layer. The second surface may be a surface of a rugged polysilicon layer.

Abstract: A method passivates a surface of a semiconductor structure. The method provides III-V semiconductor material having a surface to be passivated. Upon the surface of the III-V semiconductor material to be passivated an oxide layer is formed. Thereafter, the surface of the III-V semiconductor material having the oxide layer is passivated, without desorption of the oxide layer and in a vacuum of 2×10?6 Torr, with a material having the ability to intermix with the oxide layer so as to exchange oxygen, passivation layer material, and III-V semiconductor material therebetween to form graded layers of oxidized III-V and passivation material.

Abstract: A method includes epitaxially growing a semiconductor layer with a free surface and performing an anneal that reduces atomic roughness on the free surface. The free surface has an orientation with respect to lattice axes of the layer for which atoms in flat regions of the free surface have more chemical bonds to the layer than do, at least, some of the atoms at edges of monolayer steps on the free surface.

Abstract: In a CMOS semiconductor device using a silicon germanium gate and a method of fabricating the same, a gate insulating layer, a conductive electrode layer that is a seed layer, a silicon germanium electrode layer, and an amorphous conductive electrode layer are sequentially formed on a semiconductor substrate. A photolithographic process is then carried out to remove the silicon germanium electrode layer in the NMOS region, so that the silicon germanium layer is formed only in the PMOS region and is not formed in the NMOS region.

Abstract: In a method of fabricating a SiC semiconductor device, a surface of a SiC layer (5, 48, 102) is processed into a cleaned surface terminated at Si. An oxide film (7, 49, 105) is formed on the cleaned surface of the SiC layer. The SiC layer with the oxide film is subjected to thermal oxidation at a temperature in a range of 700° C. to 900° C. so that only terminal Si at the cleaned surface of the SiC layer is oxidated and an interface between the oxide film and the SiC layer becomes an SiO2/SiC cleaned interface.

Abstract: A method for selectively removing one or more coatings from the surface of a substrate is described. The coating is treated with an aqueous composition which includes an acid of the formula HxAF6, or precursors to such an acid. In that formula, A is Si, Ge, Ti, Zr, Al, and Ga; and x is 1-6. The acid is often H2SiF6. The composition may sometimes include at least one additional acid, such as phosphoric acid. The coating being removed is often an aluminide coating or an MCrAl(X)-type material. The substrate is usually a polymer or a metal, such as a superalloy.

Abstract: A method of manufacturing a semiconductor device including a gallium nitride related semiconductor. The method include preparing a substrate having surface of a gallium nitride related semiconductor; contacting the surface with atomic nitrogen, which is obtained by decomposing a nitrogen-containing gas in a catalytic reaction, to nitride the surface; and forming, on the surface, a gate electrode and source and drain electrodes opposing each other across the gate electrode.

Abstract: Ohmic contact formation inclusive of Carbon films on 4H and 6H n-type Silicon Carbide is disclosed. Contact formation includes an initial RF sputtering to produce an amorphous Carbon film with the sp2/sp3 Carbon ratio of about 1.0 measured by X-ray photoelectron spectroscopy. This Carbon film gradually evolves from sp3 to sp2 structures of high sp2 content during an annealing at temperatures ranging from 600° C. to 1350° C. depending on the substrate doping levels, between 1016 and 1019, employed. Formation of sp2 Carbon is accelerated by the presence of metal and gaseous catalytic agents including for example nickel and argon. The sp2 Carbon structures consist especially of nano-size graphitic flakes and also of amorphous aromatic-like Carbon structures, and polyene-like Carbon structures, as are revealed by Raman spectroscopy. Ohmic contact is achieved when a sufficient amount of nano-graphitic flakes are formed at the selected annealing temperature.

Abstract: A method of depositing a low dielectric constant film on a substrate. In one embodiment, the method includes the steps of positioning the substrate in a deposition chamber, providing a gas mixture to the deposition chamber, in which the gas mixture is comprised of one or more cyclic organosilicon compounds, one or more aliphatic compounds and one or more oxidizing gases. The method further includes reacting the gas mixture in the presence of an electric field to form the low dielectric constant film on the semiconductor substrate. The electric field is generated using a very high frequency power having a frequency in a range of about 20 MHz to about 100 MHz.

Abstract: The present invention relates to a multi-layer dopant barrier and its method of fabrication for use in semiconductor structures. In an illustrative embodiment, the multi-layer dopant barrier is disposed between a first doped layer and a second doped layer. The multi-layer dopant barrier further includes a first dopant blocking layer adjacent the first doped layer and a second dopant blocking layer adjacent the second doped layer. A technique for fabricating the multi layer dopant barrier is disclosed. A first dopant blocking layer is formed at a first temperature, and a second dopant blocking layer is formed at a second temperature over the first barrier layer.

Abstract: A method of fabricating a Si1−XGeX film on a silicon substrate includes preparing a silicon substrate; epitaxially depositing a Si1−XGeX layer on the silicon substrate forming a Si1−XGeX/Si interface there between; amorphizing the Si1−XGeX layer at a temperature greater than Tc to form an amorphous, graded SiGe layer; and annealing the structure at a temperature of between about 650° C. to 1100° C. for between about ten seconds and sixty minutes to recrystallize the SiGe layer.

Abstract: A method passivates a surface of a semiconductor structure. The method provides III-V semiconductor material having a surface to be passivated. Upon the surface of the III-V semiconductor material to be passivated an oxide layer is formed. Thereafter, the surface of the III-V semiconductor material having the oxide layer is passivated, without desorption of the oxide layer and in a vacuum of 2×10−6 Torr, with a material having the ability to intermix with the oxide layer so as to exchange oxygen, passivation layer material, and III-V semiconductor material therebetween to form graded layers of oxidized III-V and passivation material.

Abstract: A method for using a monitor substrate to determine effectiveness of a cleaning operation is provided. The method includes selecting a substrate from a lot of substrates and inspecting a surface of the substrate to determine a roughness profile of the substrate. The monitor substrate is then processed through a cleaning operation, and the monitor substrate is patterned with die regions throughout. Each of the die regions has a plurality of areas defining distinct roughness simulations. The method the proceeds to inspecting the monitor substrate at one die region and at one of the plurality of areas in the one die region that most closely resembles the roughness profile of the substrate. The inspecting of the monitor substrate is configured to yield data regarding cleaning performance of the cleaning operation.

Abstract: A process control is performed for fabricating both a wafer for a device including a Ge-containing semiconductor film and a wafer for a device, for example, including no Ge-containing semiconductor film on a common fabrication line. When the wafer including the Ge-containing semiconductor film is to be subjected to high-temperature treatment at 700° C. or more in the state of the Ge-containing semiconductor film being substantially exposed, the Ge-containing semiconductor film is covered with a cap layer made of Si or the like before the high-temperature treatment. The cap layer may be formed on the common fabrication line. However, if the formation of the cap layer itself involves high temperature of 700° C. or more, it is performed on a fabrication line separate from the common fabrication line. Alternatively, the cap layer may be formed on a fabrication line separate from the common fabrication line and the high-temperature treatment at 700° C.

Abstract: Methods are provided herein for treating substrate surfaces in preparation for subsequent nucleation-sensitive depositions (e.g., polysilicon or poly-SiGe) and adsorption-driven deposition (e.g. atomic layer deposition or ALD). Prior to depositing, the surface is treated with non-depositing plasma products. The treated surface more readily nucleates polysilicon and poly-SiGe (such as for a gate electrode), or more readily adsorbs ALD reactants (such as for a gate dielectric). The surface treatment provides surface moieties more readily susceptible to a subsequent deposition reaction, or more readily susceptible to further surface treatment prior to deposition. By changing the surface termination of the substrate with a low temperature radical treatment, subsequent deposition is advantageously facilitated without depositing a layer of any appreciable thickness and without significantly affecting the bulk properties of the underlying material.

Abstract: A method for utilizing a rough insulator to enhance metal-insulator-semiconductor reliability is provided. The method includes steps of: (a) providing a semiconductor substrate; (b) prebaking the semiconductor substrate under a relatively high vacuum to form a rough surface on the semiconductor substrate; and (c) growing an insulator on the semiconductor substrate to form a rough insulator and increase the metal-insulator-semiconductor reliability when the insulator is applied.

Abstract: A method of selectively oxidizing III-V semiconductor material is provided. There is provided a III-V semiconductor system comprising a short-period super lattice (SSL) of N periods of alternating layers of an aluminum-bearing III-V compound semiconductor material and a second III-V semiconductor material where N≧2, at least one phosphorous-rich III-V semiconductor layer, and at least one substantially phosphorous-free III-V semiconductor layer between each of the at least one phosphorous-rich layers and the SSL. The III-V semiconductor system is exposed to oxidizing atmosphere to selectively oxidize at least a portion of the SSL.

Abstract: A sample stand is set in a chamber provided with an observation window on its upper surface and a heater for heating a sample is provided in the vicinity of the sample stand. Then, a microscope, a camera and a television monitor are connected and mounted outside the observation window of the chamber. The microscope is mounted such that a specific layer of the sample is focused on and can be observed. According to a manufacturing method of the preset invention, oxidation treatment is performed in such equipment while an oxidation process of the specific layer (semiconductor layer for selective oxidation) of the sample is observed.

Abstract: An insulating-gate semiconductor device has a first nitride semiconductor layer formed over a substrate and an insulating oxidation layer obtained by oxidizing a second nitride semiconductor layer formed on the first nitride semiconductor layer. A gate electrode is formed on the insulating oxidation layer.

Abstract: The present invention provides a method for producing a semiconductor substrate which comprises the steps of growing a first semiconductor layer on a substrate in liquid phase at a properly controlled temperature for eliminating defects and growing a second semiconductor layer on the first semiconductor layer in liquid phase at a higher temperature; a solar cell produced by a method comprising a step of anodizing the surface of the first and second layer side of the semiconductor substrate produced by the liquid-phase growth method; a liquid-phase growth apparatus comprising means for storing a melt, means for changing the temperature of the stored melt, and means for bringing an oxygen-containing substrate into contact with the melt, wherein a substrate is brought into contact with the melt at a temperature so as to suppress the stacking faults contained in the semiconductor layer grown on the surface of the substrate.

Abstract: A method of producing a semiconductor film of Cu(MIII)(MVI)2 wherein MIII represents In1-xGax where x is between 0 and 1 and MVI represents SeyS1-y where y is between 0.5 and 1, including the steps of: (a) depositing on a substrate a precursor Cu(MIII)(MVI)2 film having a molar ratio of Cu:MIII of less than 1.0:1.0 but not less than 1.0:1.4 and (b) annealing the precursor film at a temperature of 400-500° C. in an oxygen-containing atmosphere to form a buffer layer of indium oxide and/or gallium oxide and a Cu(In1-xGax)(SeyS1-y)2 film interposed between the substrate and the buffer layer. The buffer layer may be removed by etching with an acid.

Abstract: A memory device includes a first memory cell and a second memory cell both controlled by a common control gate. The device includes: a substrate; first and second stacks each including an insulating layer formed over the substrate, a first conductive layer formed over the insulating layer and providing a select gate, and a first dielectric layer formed over the first conductive layer, each of the stacks also including an inner sidewall and an outer sidewall, the. stacks being separated by a common area of the substrate, the inner and outer sidewalls of the stacks being coated with a second dielectric layer; first and second spacers formed adjacent the inner sidewalls of the first and second stacks respectively, the first and second spacers being separated by a medial portion of the common source area of the substrate, each of the spacers.

Abstract: A novel growth procedure to grow epitaxial Group III metal nitride thin films on lattice-mismatched substrates is proposed. Demonstrated are the quality improvement of epitaxial GaN layers using a pure metallic Ga buffer layer on c-plane sapphire substrate. X-ray rocking curve results indicate that the layers had excellent structural properties. The electron Hall mobility increases to an outstandingly high value of &mgr;>400 cm2/Vs for an electron background concentration of 4×1017 cm−3.

Abstract: A method of fabricating a nitride semiconductor includes the steps of forming a nitride semiconductor doped with a p-type impurity, treating the surface of the nitride semiconductor in an atmosphere containing active oxygen to remove carbon remaining the surface and form an oxide film thereon, and activating the p-type impurity to turn the conductive type of the nitride semiconductor into a p-type. Since carbon remaining on the surface of the nitride semiconductor is removed and the oxide film is formed thereon, the surface of the nitride semiconductor is prevented from being deteriorated by the activating treatment and the rate of activating the p-type impurity is enhanced. As a result, it is possible to reduce the contact resistance of the nitride semiconductor with an electrode and hence to variation in characteristics of the nitride semiconductor.

Abstract: A method of forming a native oxide from at least one strain-compensated superlattice of Group III-V semiconductor material, where each at least one superlattice includes two monolayers of a Group III-V semiconductor material and at least two monolayers of an aluminum-bearing Group III-V semiconductor material. The method entails exposing each at least one superlattice to a water-containing environment and a temperature of at least about 425 degrees Celsius to convert at least a portion of said superlattice to a native oxide. The native oxide thus formed is useful in electrical and optoelectrical devices, such as lasers.

Abstract: Method for processing gallium arsenide (GaAs) wafers is provided. One embodiment of the invention provides a method for processing a substrate comprising disposing the substrate on a substrate support member in a high density plasma chemical vapor deposition chamber, depositing a film onto a surface of the substrate, and after deposition of the film, flowing a heat transfer gas in one or more channels on a substrate support surface of the substrate support member.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers (22) by forming a compliant substrate for growing the monocrystalline layers. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer (24) on a silicon wafer (22). The accommodating buffer layer (24) is a layer of monocrystalline oxide spaced apart from the silicon wafer (22) by an amorphous interface layer (28) of silicon oxide. The amorphous interface layer (28) dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer.

Abstract: In a GaAs type semiconductor device, InpGa1−pN (0<p≦1) is used to thereby form heterojunction having a large difference in energy gap, thereby providing a high performance semiconductor device.

Abstract: The present invention generally provides a method and apparatus for forming a doped layer on a substrate to improve uniformity of subsequent deposition thereover. Preferably, the layer is deposited by a sputtering process, such as physical vapor deposition (PVD) or Ionized Metal Plasma (IMP) PVD, using a doped target of conductive material. Preferably, the conductive material, such as copper, is alloyed with a dopant, such as phosphorus, boron, indium, tin, beryllium, or combinations thereof, to improve deposition uniformity of the doped layer over the substrate surface and to reduce oxidation of the conductive material. It is believed that the addition of a dopant, such as phosphorus, stabilizes the conductive material surface, such as a copper surface, and lessens the surface diffusivity of the conductive material.

Abstract: Nitride semiconductor devices and methods of producing same are provided. The present invention includes forming an active layer on a substrate by vapor phase growth at a first temperature and forming thereon one or more nitride semiconductor layers at a temperature which is greater from the first temperature, such as by about 250° C. or less. The nitride semiconductor devices of the present invention can be used in a variety of different applications.

Abstract: Chemical vapor deposition methods are used to deposit silicon-containing films over mixed substrates. Such methods are useful in semiconductor manufacturing to provide a variety of advantages, including uniform deposition over heterogeneous surfaces, high deposition rates, and higher manufacturing productivity. An example is in forming the base region of a heterojunction bipolar transistor, including simultaneous deposition over both single crystal semiconductor surfaces and amorphous insulating regions.

Abstract: By providing a nitrogen-doped low carrier concentration layer 13 having both of a donor concentration and an acceptor concentration controlled below 1×1016/cm3 at a p-n junction portion between an n-type GaP layer 12 and a p-type GaP layer 14, the luminance of the GaP light emitting device can be improved by as much as 20 to 30% over the conventional one. Suppressing the donor concentration and the acceptor concentration in the low carrier concentration layer 13 below 1×1016/cm3 inevitably gives a carrier concentration, which is expressed as a difference between both concentrations, lower than 1×1016/cm3 accordingly. The emission efficiency upon injection of electrons or holes can be improved by suppressing the concentration of the donor which serves as non-emissive center below 1×1016/cm3 to thereby extend the carrier lifetime; and by concomitantly suppressing the carrier concentration at a level significantly lower than that in the adjacent layers 12 and 14.

Abstract: The invention relates to a method for the production of a monocrystalline layer on a substrate with a non-adapted lattice. To this end, a monocrystalline substrate with a buried amply defective layer and a monocrystalline layer produce thereon are used. The buried amply defective layer can be produced by hydrogen implantation.

Abstract: A system for coating the surface of compound semiconductor wafers includes providing a single-wafer epitaxial production system in a cluster-tool architecture with a loading, storage, and transfer modules, a III-V deposition chamber, and an insulator deposition chamber. The compound semiconductor wafer is placed in the loading and transfer module and the pressure is reduced to less than 5×10−10 Torr, after which the wafer is moved to the III-V growth chamber and layers of compound semiconductor material are epitaxially grown on the surface of the wafer. The single wafer is then moved through the transfer module to the insulator chamber and an insulating cap layer is formed by thermally evaporating molecules, consisting essentially of gallium and oxygen, from an effusion cell using a thermal evaporation source that utilizes a metallic iridium crucible that is manufactured using the electroforming process.

Abstract: A method of selectively oxidizing III-V semiconductor material is provided. There is provided a III-V semiconductor system comprising a short-period super lattice (SSL) of N periods of alternating layers of an aluminum-bearing III-V compound semiconductor material and a second III-V semiconductor material where N≧2, at least one phosphorous-rich III-V semiconductor layer, and at least one substantially phosphorous-free III-V semiconductor layer between each of the at least one phosphorous-rich layers and the SSL. The III-V semiconductor system is exposed to oxidizing atmosphere to selectively oxidize at least a portion of the SSL.

Abstract: A semiconductor device has a strongly bonding structure for improving bond strength between the semiconductor and the insulating layer even if the insulating layer is formed by a traditional method which causes slight damage to the semiconductor. The strongly bonding structure includes an oxide layer 12 (containing a constituent element of the semiconductor), an oxide bonding layer, a bond-creating layer (which may disappear from the finished product), and an insulating layer, which are sequentially formed one over the other. The oxide layer may be either one which occurs naturally or one which is formed artificially. The oxide bonding layer is formed by reaction between oxygen in the oxide layer and a constituent element in the bond-creating layer. The bond-creating layer contains an element that oxidizes and an element that reacts with a constituent element of the insulating layer.

Abstract: Method for processing gallium arsenide (GaAs) wafers is provided. One embodiment of the invention provides a method for processing a substrate comprising disposing the substrate on a substrate support member in a high density plasma chemical vapor deposition chamber, depositing a film onto a surface of the substrate, and after deposition of the film, flowing a heat transfer gas in one or more channels on a substrate support surface of the substrate support member.

Abstract: Methods for fabricating a layer of oxide on a silicon carbide layer are provided by forming the oxide layer on the silicon carbide layer by oxidizing the silicon carbide layer in an N2O environment. A predetermined temperature profile and/or a predetermined flow rate profile of N2O are provided during the oxidation. The predetermined temperature profile and/or predetermined flow rate profile may be constant or variable and may include ramps to steady state conditions. The predetermined temperature profile and/or the predetermined flow rate profile are selected so as to reduce interface states of the oxide/silicon carbide interface with energies near the conduction band of SiC.

Abstract: A method for manufacturing a SiC device embraces (a) depositing a polysilicon film above a SiC substrate; (b) delineating the polysilicon film into required pattern; and (c) annealing the SiC substrate in a water rich ambient to selectively grow a thick localized thermal oxide film above the SiC substrate. At the surface of SiC substrate, source/drain regions and substrate contact region are formed. In the water rich ambient, the H2O partial pressure is so maintained that it is more than 0.95.

Abstract: Microcontact printing to pattern a self-assembled monolayer (SAM) of an alkanephosphonic acid on a film of indium zinc oxide (IZO). The SAM is robust enough to protect the undelying IZO from wet chemical etching, and thus defines a pattern of IZO on the substrate. In the microcontact printing process, a patterned, elastomeric stamp is inked with a solution of octadecylphosphonic acid and brought into conformal contact with the IZO surface. A SAM of alkanesulfonic acid forms where the stamp and the surface make contact; the rest remains underivatized. The stamp is then removed from the surface. Etching the sample in aqueous oxalic acid removes the unprotected areas, while the areas protected by the SAM remain in place.

Abstract: A method for forming a nitride compound semiconductor film of the present invention includes the steps of: providing a substrate having a portion which acts as a growth suppressing film on a outermost surface thereof; forming a growth promoting film partially on the substrate; and forming a nitride compound semiconductor on the growth promoting film.

Abstract: Provided herein is a method of depositing a film on a substrate in a high temperature chemical vapor deposition (CVD) reactor, comprising the steps of polishing sharp corner(s) of the surface of a heater, wherein the heater provides heat to the substrate for deposition; coating the polished heater surface with a coating material; and depositing a film on the substrate in the CVD reactor, wherein the substrate is heated through the coated polished heater. Such method of polishing may also be used for reducing pitting of a coated heater and protecting the heater from corrosive environment in a CVD reactor.

Abstract: A method for mask-free molecular or atomic patterning of surfaces of reactive solids is disclosed. A molecular-scale pattern of adsorbate molecules is used in place of the conventional macroscopic “mask”. Molecules adsorb at surfaces in patterns, governed by the structure of the surface, the chemical nature of the adsorbate, and the adsorbate coverage at the surface. The surface is patterned and then marked or imprinted with the pattern by inducing localised chemical reaction between adsorbate molecules and the surface of the solid, resulting in an imprint being formed in the vicinity of the adsorbate molecules. In one aspect of the invention, photoinduced or electron-induced reaction of the patterned adsorbate leads to patterned reaction with the surface.

Abstract: A Rat IgG antibody film, formed on a p-type Si substrate, is selectively irradiated with ultraviolet rays, thereby leaving part of the Rat IgG antibody film, except for a region deactivated with the ultraviolet rays. Next, when the p-type Si substrate is immersed in a solution containing Au fine particles that have been combined with a Rat IgG antigen, the Rat IgG antigen is selectively combined with the Rat IgG antibody film. As a result, Au fine particles, combined with the Rat IgG antigen, are fixed on the Rat IgG antibody film. Thereafter, the p-type Si substrate is placed within oxygen plasma for 20 minutes, thereby removing the Rat IgG antibody film, the deactivated Rat IgG antibody film and the Rat IgG antigen. Consequently, dot elements can be formed at desired positions on the p-type Si substrate. If these dot elements are used for the floating gate of a semiconductor memory device, then the device has a structure suitable for miniaturization.

Abstract: A method of growing a Group III or Group III-V nitride layer on a semiconductor substrate includes the steps of: locating, within a chamber, the semiconductor substrate having on its surface a Group III-V semiconductor layer incorporating a substance which is strongly reactive with nitrogen; and subsequently effecting nitridation of the Group III-V semiconductor layer by introducing a species containing nitrogen into the chamber to cause a reaction between the nitrogen and the substance.

Abstract: Disclosed are a method of making GaAs-based enhancement-type MOS-FETs, and articles (e.g., GaAs-based ICs) that comprise such a MOS-FET. The MOS-FETs are planar devices, without etched recess or epitaxial re-growth, with gate oxide that is primarily Ga2O3, and with low midgap interface state density (e.g., at most 1×1011 cm−2 eV−1 at 20° C.). The method involves ion implantation, implant activation in an As-containing atmosphere, surface reconstruction, and in situ deposition of the gate oxide. In preferred embodiments, no processing step subsequent to gate oxide formation is carried out above 300° C. in air, or above about 700° C. in UHV. The method makes possible fabrication of planar enhancement-type MOS-FETs having excellent characteristics, and also makes possible fabrication of complementary MOS-FETs, as well as ICs comprising MOS-FETs and MES-FETs.

Abstract: To increase the rate or speed of formation of a thermal oxide film of a silicon carbide semiconductor device, the partial pressure of water vapor is controlled to within the range of 0.1 to 0.95 when a surface of silicon carbide is oxidized under a mixed atmosphere of water vapor and oxygen. In a pyrogenic oxidation method in which hydrogen and oxygen are introduced to perform thermal oxidation, the ratio of the flow rate of hydrogen to that of oxygen is controlled to within the range of 1:0.55 to 1:9.5. In another pyrogenic oxidation method in which hydrogen and oxygen are introduced to perform thermal oxidation, a large portion of an oxide film is formed while the ratio of the flow rate of hydrogen to that of oxygen is controlled to about 1:4.5, and a remaining portion of the oxide film is then formed while the ratio of the flow rate of hydrogen to that of oxygen is controlled to about 1:0.55.

Abstract: A method for growing high-quality gallium nitride over a substrate is disclosed. The method comprises growing first layer with a high dislocation density over the substrate, a second layer having a high number of point defects and a reduced dislocation density as compared to the dislocation density of the first layer over the first layer, and a third layer having a reduced number of point defects as compared to the second layer over the second layer. The resulting gallium nitride is semi-insulating, which inhibits parasitic current flow and parasitic capacitive effects, yet it not so insulating that electron flow in adjacent transistor channels is inhibited.

Abstract: A method for forming a titanium dioxide layer is disclosed. The method includes the steps of providing a titanium-containing material, adding an acid substance to the titanium-containing material to form a mixture, and exposing the device to the mixture to form the titanium dioxide layer thereon. Such a method can be applied for forming a titanium dioxide layer on a semiconductor device, a silicon substrate, an integrated circuit, a photoelectric device, etc.