Having Structure To Improve Output Signal (e.g., Exposure Control Structure, Etc.) Patents (Class 438/78)
  • Patent number: 8956908
    Abstract: In image sensors and methods of manufacturing the same, a substrate has a photoelectric conversion area, a floating diffusion area and a recess between the photoelectric conversion area and the floating diffusion area. A plurality of photodiodes is vertically arranged inside the substrate in the photoelectric conversion area. A transfer transistor is arranged along a surface profile of the substrate having the recess and configured to transfer electric charges generated from the plurality of photodiodes to the floating diffusion area. The transfer transistor includes a gate insulation pattern on a sidewall and a bottom of the recess and on a surface of the substrate around the recess, and a gate conductive pattern including polysilicon doped with impurities and positioned on the gate insulation pattern along the surface profile of the substrate having the recess, wherein a cavity is in an upper surface of the gate conductive pattern.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: February 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ihara Hisanori
  • Patent number: 8895349
    Abstract: An approach is provided for forming a backside illuminated image sensor that includes a semiconductor substrate having a front side and backside, a sensor element formed overlying the frontside of the semiconductor substrate, and a capacitor formed overlying the sensor element.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: November 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Jeng-Shyan Lin, Wen-De Wang
  • Patent number: 8835981
    Abstract: According to embodiments of the present invention, a solid-state image sensor has a semiconductor element substrate having a plurality of photo electric conversion elements, an interlaminar insulating film having wires, formed at a first surface of the semiconductor element substrate, a color filter having a plurality of dye films of a plurality of colors, formed at a second surface of the semiconductor element substrate, a micro lens array having a plurality of micro lenses, formed above the color filter, a plurality of inner lenses formed between the photoelectric conversion elements and the dye films, and a shroud that surrounds each of the inner lenses, formed above the second surface of the semiconductor element substrate.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: September 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Amane Oishi
  • Patent number: 8815637
    Abstract: A conductive paste for a photovoltaic cell and a method for producing the photovoltaic cell are disclosed. The conductive paste includes a silver powder, glass frit and a sintering inhibitor that suppresses sintering of the silver powder. The sintering inhibitor contains at least one substance selected from aluminum oxide, silicon oxide and silicon carbide. The method includes forming a first anti-reflective layer on a first region of a main surface of a semiconductor substrate; forming a second anti-reflection layer on a second region of the main surface which is different from the first region; coating the electrically conductive paste onto the second anti-reflective layer on the second anti-reflection layer; and forming a surface electrode in the second region by reacting the second anti-reflection layer with the electrically conductive paste at an elevated temperature.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: August 26, 2014
    Assignee: KYOCERA Corporation
    Inventors: Kotaro Umeda, Tomoko Yoshimi, Shuhei Katayama, Yoshio Miura, Toshihiro Iwaida, Takeshi Nakatani
  • Patent number: 8779484
    Abstract: An image sensor includes a plurality of color filters and an anti-reflective layer. The color filters are located on a substrate. The anti-reflective layer is located between the substrate and the color filters, and parts of the anti-reflective layer corresponding to at least two of the color filters have different thicknesses. Moreover, an image sensing process including the following steps is also provided. An anti-reflective layer is formed on a substrate. A plurality of color filters is formed on the anti-reflective layer, wherein parts of the anti-reflective layer right below at least two of the color filters have different thicknesses.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: July 15, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Xu Yang Shen, Seng Wah Liau, Yuheng Liu, Qin Li, Kiet Houng Chow
  • Patent number: 8766339
    Abstract: The present disclosure relates to photodetectors with high efficiency of light detection, and may be used in a wide field of applications, which employ the detection of very weak and fast optical signals, such as industrial and medical tomography, life science, nuclear, particle, and/or astroparticle physics etc. A highly efficient CMOS-technology compatible Silicon Photoelectric Multiplier may comprise a substrate and a buried layer applied within the substrate. The multiplier may comprise cells with silicon strip-like quenching resistors, made by CMOS-technology, located on top of the substrate and under an insulating layer for respective cells, and separating elements may be disposed between the cells.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: July 1, 2014
    Assignee: Max-Planck-Gesellschaft zur Foerderung der Wissenschaften e.V. Hofgartenstr. 8
    Inventors: Masahiro Teshima, Razmik Mirzoyan, Anatoly Pleshko, Ljudmila Aseeva
  • Patent number: 8735946
    Abstract: Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to processes for making such substrates.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: May 27, 2014
    Assignee: Soitec
    Inventors: Mohamad A Shaheen, Frederic Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru, Karine Landry, Carlos Mazure
  • Patent number: 8629484
    Abstract: Disclosed herein is a solid-state imaging device including: a semiconductor region of a second conductivity type which is formed on a face side of a semiconductor substrate; a photoelectric conversion element which has an impurity region of a first conductivity type and which is operable to generate electric charge according to the amount of incident light and to accumulate the electric charge in the inside thereof; an electric-charge holding region which has an impurity region of the first conductivity type and in which the electric charge generated through photoelectric conversion by the photoelectric conversion element is held until read out; an intermediate transfer path through which only the electric charge generated by the photoelectric conversion element during an exposure period and being in excess of a predetermined electric charge amount is transferred into the electric-charge holding region; and an impurity layer.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: January 14, 2014
    Assignee: Sony Corporation
    Inventors: Hiroyuki Ohri, Takashi Machida, Takahiro Kawamura, Yasunori Sogoh
  • Patent number: 8558234
    Abstract: Highly efficient, low energy, low light level imagers and photodetectors are provided. In particular, a novel class of Della-Doped Electron Bombarded Array (DDEBA) photodetectors that will reduce the size, mass, power, complexity, and cost of conventional imaging systems while improving performance by using a thinned imager that is capable of detecting low-energy electrons, has high gain, and is of low noise.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: October 15, 2013
    Assignee: California Institute of Technology
    Inventors: Shouleh Nikzad, Chris Martin, Michael E. Hoenk
  • Patent number: 8546174
    Abstract: In a method for manufacturing a semiconductor device according to an embodiment, an epitaxial semiconductor layer is epitaxially grown on a semiconductor substrate, a photoelectric converting portion is formed on the epitaxial semiconductor layer, a wiring layer is formed on the epitaxial semiconductor layer after forming the photoelectric converting portion, a support substrate is bonded onto the wiring layer, and the semiconductor substrate is etched from an opposite surface side to a side for the bonding after the bonding. In the method for manufacturing a semiconductor device, an amorphous Si layer is formed on the opposite surface side of the epitaxial semiconductor layer after the etching and an antireflection film and a color filter are formed on the amorphous Si layer in sequence.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: October 1, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tadashi Iijima
  • Patent number: 8546899
    Abstract: A light receiving element includes a waveguide that includes a waveguide core, a multi-mode interference waveguide that has a width larger than a width of the waveguide, the multi-mode interference waveguide receiving a first light from the waveguide core at a first end, and a photodetection portion that includes a first semiconductor layer and an absorption layer disposed on the first semiconductor layer, the first semiconductor layer including at least one layer and receiving a second light from the multi-mode interference waveguide at a second end, the absorption layer being disposed above the first semiconductor layer and absorbing the second light. A distance from the first end of the multi-mode interference waveguide to the second end of the photodetection portion is longer than 70% of a first length and shorter than 100% of the first length, the first length being a length where self-imaging occurs in the multi-mode interference waveguide.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: October 1, 2013
    Assignee: Fujitsu Limited
    Inventor: Kazumasa Takabayashi
  • Patent number: 8481358
    Abstract: A pixel array in an image sensor includes multiple pixels. The pixel array includes vertical shift registers for shifting charge out of the pixel array. The vertical shift registers can be interspersed between the pixels, such as in an interline image sensor, or the photosensitive areas in the pixels can operate as vertical shift registers. The pixels are divided into blocks of pixels. One or more electrodes are disposed over each pixel. Conductive strips are disposed over the electrodes. Contacts are used to connect selected electrodes to respective conductive strips. The contacts in at least one block of pixels are positioned according to one contact pattern while the contacts in one or more other blocks are positioned according to a different contact pattern. The different contact patterns reduce or eliminate visible patterns in the contact locations.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: July 9, 2013
    Assignee: Truesense Imaging, Inc.
    Inventor: Shen Wang
  • Patent number: 8476102
    Abstract: A method for manufacturing a solid state image pickup device including a first active region provided with a first conversion unit, a second active region provided with a second conversion unit, and a third active region adjoining the first and the second active regions with a field region therebetween and being provided with a pixel transistor, the method including the steps of ion-implanting first conductivity type impurity ions to form a semiconductor region serving as a potential barrier against the signal carriers at a predetermined depth in the third active region and ion-implanting second conductivity type impurity ions into the third active region with energy lower than the above-described ion-implantation energy.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: July 2, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hideaki Takada, Toru Koizumi, Yasuo Yamazaki, Tatsuya Ryoki
  • Patent number: 8455294
    Abstract: A method for making the image sensor structure, for avoiding or mitigating lens shading effect. The image sensor structure includes a substrate, a sensor array disposed at the surface of the substrate, a dielectric layer covering the sensor array, wherein the dielectric layer includes a top surface having a dishing structure, an under layer filled into the dishing structure and having a refraction index greater than that of the dielectric layer, a filter array disposed on the under layer corresponding to the sensor array, and a microlens array disposed above the filter array. A top layer may be additionally disposed to cover the filter array and the microlens array is disposed on the top layer.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: June 4, 2013
    Assignee: United Microelectronics Corp.
    Inventor: Cheng-Hung Yu
  • Patent number: 8445311
    Abstract: A method of fabricating a differential doped solar cell is provided. The method comprises the steps of (a) providing a light doped semiconductor substrate; (b) forming a heavy doped layer having the same type of dopant used in step (a) on a front surface of the semiconductor substrate; and (c) forming an emitter layer having a different type of dopant used in step (a) on a surface of the heavy doped layer to constitute a p-n junction with the heavy doped layer.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: May 21, 2013
    Assignee: Big Sun Energy Technology Incorporation
    Inventors: Chi-Hsiung Chang, Kuan-Lun Chang, Hung-Yi Chang, Yi-Min Pan, Jun-Min Wu, Ying-Yen Chiu
  • Patent number: 8435823
    Abstract: According to one embodiment, a method of manufacturing a back-illuminated solid-state imaging device including forming a mask with apertures corresponding to a pixel pattern on the surface of a semiconductor layer, implanting second-conductivity-type impurity ions into the semiconductor layer from the front side of the layer to form second-conductivity-type photoelectric conversion parts and forming a part where no ion has been implanted into a pixel separation region, forming at the surface of the semiconductor layer a signal scanning circuit for reading light signals obtained at the photoelectric conversion parts after removing the mask, and removing the semiconductor substrate and a buried insulating layer from the semiconductor layer after causing a support substrate to adhere to the front side of the semiconductor layer.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: May 7, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hirofumi Yamashita
  • Patent number: 8420437
    Abstract: Disclosed is a method for forming an EMI shielding layer on all surfaces of a semiconductor package in order to enhance EMI shielding effect on all surfaces and to prevent electrical short to external terminals of the semiconductor package. According to the method, a temporary protective layer is formed on the external terminals where the temporary protective layer is further in contact with a plurality of annular surface regions of the semiconductor package surrounding and adjacent to the external terminals. Then, the EMI shielding layer is formed on the top surface, the bottom surface and the side surfaces of the semiconductor package without forming on the external terminals.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: April 16, 2013
    Assignee: Powertech Technology Inc.
    Inventor: Wen-Jeng Fan
  • Patent number: 8415195
    Abstract: In manufacturing of a solar cell module in which a solar cell having a surface electrode to which a tab lead is connected is sealed with a resin, the step of connecting the tab lead and the step of sealing the solar cell with the resin are performed simultaneously at a relatively low temperature that is used for the resin sealing step. To perform these steps simultaneously, the solar cell having the surface electrode to which the tab lead is connected with an adhesive is resin-sealed using a vacuum laminator to manufacture the solar cell module. The vacuum laminator used includes a first chamber and a second chamber partitioned by a flexible sheet. The internal pressures of these chambers can be controlled independently, and a heating stage for heating is provided in the second chamber.
    Type: Grant
    Filed: May 14, 2010
    Date of Patent: April 9, 2013
    Assignee: Sony Chemical & Information Device Corporation
    Inventors: Hideaki Okumiya, Satoshi Yamamoto, Masao Saito
  • Patent number: 8390007
    Abstract: A semiconductor light emitting device has a light emitting element, and first and second electrodes. The light emitting element has a nitride-based III-V compound semiconductor on a substrate. The first and second electrodes are disposed on both sides of the light emitting element, respectively. The light emitting element has a light emitting layer, a first conductive type semiconductor layer, and a second conductive type semiconductor layer. The first conductive type semiconductor layer is disposed between the light emitting layer and the first electrode. The second conductive type semiconductor layer is disposed between the light emitting layer and the second electrode. One surface of the first conductive type semiconductor layer contacts the first electrode and is a light extraction surface which is roughly processed so as to have two or more kinds of oblique angles.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: March 5, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toru Gotoda, Takahiro Sato, Toshiyuki Oka, Shinya Nunoue, Kotaro Zaima
  • Patent number: 8389322
    Abstract: A theme is to prevent the generation of noise due to damage in a photodetecting portion in a mounting process in a photodiode array, a method of manufacturing the same, and a radiation detector. In a photodiode array, wherein a plurality of photodiodes (4) are formed in array form on a surface at a side of an n-type silicon substrate (3) onto which light to be detected is made incident and penetrating wirings (8), which pass through from the incidence surface side to the back surface side, are formed for the photodiodes (4), the photodiode array (1) is arranged with a transparent resin film (6), which covers the formed regions of the photodiodes (4) and transmits the light to be detected, provided at the incidence surface side.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: March 5, 2013
    Assignee: Hamamatsu Photonics K.K.
    Inventor: Katsumi Shibayama
  • Patent number: 8361836
    Abstract: A method for manufacturing a photoelectric conversion element and a photoelectric conversion element manufactured by the manufacturing method. The method includes the steps of forming a p-type impurity diffusion layer by diffusing boron into a silicon substrate, forming an oxidation control mask on a surface of the p-type impurity diffusion layer in an area corresponding to an area where an electrode for p-type is to be formed, forming a thermal silicon oxide film on the surface of the p-type impurity diffusion layer, exposing part of the surface of the p-type impurity diffusion layer by removing the oxidation control mask formed on the surface of the p-type impurity diffusion layer in the area corresponding to the area where the electrode for p-type is to be formed, and forming the electrode for p-type on the part of the surface of the p-type impurity diffusion layer exposed by the removal of the oxidation control mask.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: January 29, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Tsutomu Yamazaki
  • Patent number: 8313975
    Abstract: The purpose is manufacturing a photoelectric conversion device with excellent photoelectric conversion characteristics typified by a solar cell with effective use of a silicon material. A single crystal silicon layer is irradiated with a laser beam through an optical modulator to form an uneven structure on a surface thereof. The single crystal silicon layer is obtained in the following manner; an embrittlement layer is formed in a single crystal silicon substrate; one surface of a supporting substrate and one surface of an insulating layer formed over the single crystal silicon substrate are disposed to be in contact and bonded; heat treatment is performed; and the single crystal silicon layer is formed over the supporting substrate by separating part of the single crystal silicon substrate fixed to the supporting substrate along the embrittlement layer or a periphery of the embrittlement layer.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: November 20, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Fumito Isaka, Sho Kato, Junpei Momo
  • Patent number: 8298880
    Abstract: Method for manufacturing a semiconductor device, which may include (a) forming a coating film on a substrate by applying a coating liquid including a polymer conductive material dissolved in an insulating solvent on the substrate after the step (a); (b) heat-treating the coating film; and (c) forming, before or after the steps (a) and (b), a gate electrode on the substrate. Herein, a surface layer portion is an insulating layer, and an inner layer portion is an organic semiconductor layer, and the surface layer portion and the inner layer portion are formed separate from each other to allow the surface layer portion and the inner layer portion to be used as a gate insulating film and a channel of a field-effect transistor, respectively.
    Type: Grant
    Filed: September 3, 2008
    Date of Patent: October 30, 2012
    Assignee: Tokyo Electron Limited
    Inventor: Hiroshi Sato
  • Patent number: 8263857
    Abstract: A solar cell includes a substrate of a first conductive type having at least one via hole; an emitter layer of a second conductive type opposite to the first conductive type; and at least one first electrode positioned from a first surface of the substrate to the at least one via hole, and at least one first electrode current collector positioned from the at least one via hole to a second surface of the substrate, wherein the at least one via hole has a radius of about 10 ?m to about 40 ?m, and at least one of a portion of the at least one first electrode and a portion of the at least one electrode current collector, in the at least one via hole, includes at least one cavity.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: September 11, 2012
    Assignee: LG Electronics Inc.
    Inventors: Daehee Jang, Jihoon Ko, Juwan Kang, Jonghwan Kim
  • Patent number: 8236664
    Abstract: A phase change memory device includes a silicon substrate including a plurality of active regions which extend in a first direction and are arranged at regular intervals in a second direction perpendicular to the first direction. Switching elements are formed in each active region of the silicon substrate and are spaced apart from one another. Phase change patterns are formed in the second direction and have the shape of lines in such that the phase change patterns connect side surfaces of pairs of switching elements which are placed adjacent to each other in a direction diagonal to the first direction.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: August 7, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Heon Yong Chang
  • Patent number: 8232133
    Abstract: An image sensor includes a semiconductor layer that filters light of different wavelengths. For example, the semiconductor layer absorbs photons of shorter wavelengths and passes more photons of longer wavelengths such that the longer wavelength photons often pass through without being absorbed. An imaging pixel having a photodiode is formed near a front side of the semiconductor layer. A dopant layer is formed below the photodiode near a back side of the semiconductor layer. A mirror that primarily reflects photons of longer visible wavelengths is disposed on the back side of the semiconductor layer.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: July 31, 2012
    Assignee: OmniVision Technologies, Inc.
    Inventors: Howard E. Rhodes, Hidetoshi Nozaki
  • Publication number: 20120028403
    Abstract: A pixel array in an image sensor includes multiple pixels. The pixel array includes vertical shift registers for shifting charge out of the pixel array. The vertical shift registers can be interspersed between the pixels, such as in an interline image sensor, or the photosensitive areas in the pixels can operate as vertical shift registers. The pixels are divided into blocks of pixels. One or more electrodes are disposed over each pixel. Conductive strips are disposed over the electrodes. Contacts are used to connect selected electrodes to respective conductive strips. The contacts in at least one block of pixels are positioned according to one contact pattern while the contacts in one or more other blocks are positioned according to a different contact pattern. The different contact patterns reduce or eliminate visible patterns in the contact locations.
    Type: Application
    Filed: July 29, 2010
    Publication date: February 2, 2012
    Inventor: Shen Wang
  • Publication number: 20120028400
    Abstract: A pixel array in an image sensor includes multiple pixels. The pixel array includes vertical shift registers for shifting charge out of the pixel array. The vertical shift registers can be interspersed between the pixels, such as in an interline image sensor, or the photosensitive areas in the pixels can operate as vertical shift registers. The pixels are divided into blocks of pixels. One or more electrodes are disposed over each pixel. Conductive strips are disposed over the electrodes. Contacts are used to connect selected electrodes to respective conductive strips. The contacts in at least one block of pixels are positioned according to one contact pattern while the contacts in one or more other blocks are positioned according to a different contact pattern. The different contact patterns reduce or eliminate visible patterns in the contact locations.
    Type: Application
    Filed: July 29, 2010
    Publication date: February 2, 2012
    Inventor: Shen Wang
  • Patent number: 8003506
    Abstract: More complete charge transfer is achieved in a CMOS or CCD imager by reducing the spacing in the gaps between gates in each pixel cell, and/or by providing a lightly doped region between adjacent gates in each pixel cell, and particularly at least between the charge collecting gate and the gate downstream to the charge collecting gate. To reduce the gaps between gates, an insulator cap with spacers on its sidewalls is formed for each gate over a conductive layer. The gates are then etched from the conductive layer using the insulator caps and spacers as hard masks, enabling the gates to be formed significantly closer together than previously possible, which, in turn increases charge transfer efficiency. By providing a lightly doped region on between adjacent gates, a more complete charge transfer is effected from the charge collecting gate.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: August 23, 2011
    Assignee: Round Rock Research, LLC
    Inventor: Howard E. Rhodes
  • Patent number: 7964434
    Abstract: A method of processing a plurality of photovoltaic materials in a batch process includes providing at least one transparent substrate having an overlying first electrode layer and an overlying copper species based absorber precursor layer within an internal region of a furnace. The overlying copper species based absorber precursor layer has an exposed face. The method further includes disposing at least one soda lime glass comprising a soda lime glass face within the internal region of the furnace such that the soda lime glass face is adjacent by a spacing to the exposed face of the at least one transparent substrate. Furthermore, the method includes subjecting the at least one transparent substrate and the one soda lime glass to thermal energy to transfer one or more sodium bearing species from the soda lime glass face across the spacing into the copper species based absorber precursor layer via the exposed face.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: June 21, 2011
    Assignee: Stion Corporation
    Inventor: Robert D. Wieting
  • Patent number: 7964451
    Abstract: A first oxide film (102) is formed on a semiconductor substrate (101). A first nitride film (103) is formed on first gate electrode formation regions of the first oxide film (102). A plurality of first gate electrodes (104) are provided on the first nitride film (103) so as to be spaced apart from one another with a predetermined distance therebetween. A second oxide film (105) covers upper part and side walls of each of the first gate electrodes (104). A sidewall spacer (106) of a third oxide film is buried in an overhang portion generated on each side wall of each of the first gate electrodes (104) covered by the second oxide film (105). A second nitride film (107) covers the second oxide film (105), the sidewall spacer (106) and part of the first oxide film (102) located between the first gate electrodes (104). A plurality of second gate electrodes (108) are formed on at least part of the second nitride film (107) located between adjacent two of the first gate electrodes (104).
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: June 21, 2011
    Assignee: Panasonic Corporation
    Inventors: Naoto Niisoe, Kazuhisa Hirata, Tohru Yamada
  • Patent number: 7956389
    Abstract: A solid-state imaging device includes: a semiconductor substrate; photoelectric conversion elements; vertical charge transfer paths that transfer charges generated in photoelectric conversion elements, in a vertical direction; a horizontal charge transfer path that transfers the charges transferred in vertical charge transfer paths, in a horizontal direction orthogonal to the vertical direction; a plurality of charge accumulating sections between the vertical charge transfer paths and the horizontal charge transfer path; a plurality of electrodes disposed above the respective charge accumulating sections, the plurality of electrodes being classified into a plurality of kinds of electrodes; wirings corresponding to the respective kinds of electrodes and extending in the horizontal direction above the plurality of electrodes; and a planarizing layer disposed between the wirings and an uneven surface caused by the plurality of electrodes that are present in areas overlapping the wirings, so as to planarize the u
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: June 7, 2011
    Assignee: Fujifilm Corporation
    Inventors: Hirokazu Shiraki, Katsumi Ikeda
  • Patent number: 7829368
    Abstract: A pinned photodiode, which is a double pinned photodiode having increased electron capacitance, and a method for forming the same are disclosed. The invention provides a pinned photodiode structure comprising a substrate base over which is a first layer of semiconductor material. There is a base layer of a first conductivity type, wherein the base layer of a first conductivity type is the substrate base or is a doped layer over the substrate base. At least one doped region of a second conductivity type is below the surface of said first layer, and extends to form a first junction with the base layer. A doped surface layer of a first conductivity type is over the at least one region of a second conductivity type and forms a second junction with said at least one region of a second conductivity type.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: November 9, 2010
    Assignee: Aptina Imaging Corporation
    Inventor: Inna Patrick
  • Patent number: 7790496
    Abstract: An imaging apparatus includes (a) a full-frame, charge-coupled device having (i) a conductive layer of a first dopant type; (ii) a plurality of pixels arranged as a charge-coupled device in the conductive layer that collects charge in response to incident light and transfers the collected charge; (iii) an overflow drain of a dopant type opposite the first type disposed in the conductive layer and laterally adjacent to each pixel; and the apparatus having (b) a voltage supply connected to the lateral overflow drain that is at a first voltage during readout and at a second voltage that is lower than the first voltage during integration.
    Type: Grant
    Filed: September 23, 2008
    Date of Patent: September 7, 2010
    Assignee: Eastman Kodak Company
    Inventor: Eric J. Meisenzahl
  • Patent number: 7768046
    Abstract: An image sensor has a semiconductor substrate of a first conductivity type having a photo-detecting surface and a semiconductor region of a second conductivity type disposed under the photo-detecting surface and forming a junction with the semiconductor substrate. A dielectric body is provided in the semiconductor substrate beneath the junction so that a width of the dielectric body in a direction parallel to the photo-detecting surface does not extend beyond a width of the semiconductor region in the direction parallel to the photo-detecting surface. The dielectric body is polarized due to charges forming a depletion region generated by the semiconductor substrate and the semiconductor region. A width of the dielectric body is approximately equal to a width of an inner surface of the depletion in the direction parallel to the photo-detecting surface of the semiconductor substrate.
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: August 3, 2010
    Assignee: Seiko Instruments Inc.
    Inventor: Sumitaka Goto
  • Patent number: 7737044
    Abstract: A method of manufacturing a solid state imaging device having photoelectric conversion devices, the method including: 1) forming a plurality of color filters differing in color from each other, 2) forming a transparent resin layer on the color filters, 3) forming an etching control layer on the transparent resin layer, the etching control layer being enabled to be etched at a different etching rate from the etching rate of the transparent resin layer, 4) forming a lens master on the etching control layer by using a heat-flowable resin material, 5) transferring a pattern of the lens master to the etching control layer by dry etching to form an intermediate micro lens, and 6) transferring a pattern of the intermediate micro lens to the transparent resin layer by dry etching to form the transfer lenses.
    Type: Grant
    Filed: November 15, 2006
    Date of Patent: June 15, 2010
    Assignee: Toppan Printing Co., Ltd.
    Inventors: Kenzo Fukuyoshi, Tadashi Ishimatsu, Keisuke Ogata, Mitsuhiro Nakao, Akiko Uchibori
  • Patent number: 7732247
    Abstract: Isolation methods and devices for isolating regions of a semiconductor device. The isolation method and structure include forming an isolating trench in an active area and filling the trench with a doped conductive material containing silicon. Suitable conductive materials containing silicon include polysilicon and silicon-germanium. There is also provided a method and structure for isolating the regions by providing a trench in an active area of a substrate, growing an epitaxial layer in the trench to fill the trench or to partially fill the trench and depositing an insulating material over the epitaxial layer and within the trench to completely fill the trench.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: June 8, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Chandra Mouli, Howard Rhodes
  • Patent number: 7727794
    Abstract: A theme is to prevent the generation of noise due to damage in a photodetecting portion in a mounting process in a photodiode array, a method of manufacturing the same, and a radiation detector. In a photodiode array, wherein a plurality of photodiodes (4) are formed in array form on a surface at a side of an n-type silicon substrate (3) onto which light to be detected is made incident and penetrating wirings (8), which pass through from the incidence surface side to the back surface side, are formed for the photodiodes (4), the photodiode array (1) is arranged with a transparent resin film (6), which covers the formed regions of the photodiodes (4) and transmits the light to be detected, provided at the incidence surface side.
    Type: Grant
    Filed: March 10, 2004
    Date of Patent: June 1, 2010
    Assignee: Hamamatsu Photonics K.K.
    Inventor: Katsumi Shibayama
  • Patent number: 7585695
    Abstract: An interline transfer type image sensing device that can be operated at high speed and with low image smear is described. The device incorporates a refractory metal layer which is used for both a light shield over the vertical charge transfer region and as a wiring layer for low resistance strapping of poly crystalline silicon (polysilicon) gate electrodes for the vertical charge transfer region. Plugs provided by a separate metallization layer connect the refractory light shield to the polysilicon gate electrode. These plugs allow high temperature processing after refractory light shield patterning for improved sensor performance without degradation of the polysilicon gate electrode or the refractory lightshield layer.
    Type: Grant
    Filed: July 21, 2006
    Date of Patent: September 8, 2009
    Assignee: Eastman Kodak Company
    Inventors: David N. Nichols, David L. Losee, Christopher Parks
  • Patent number: 7557024
    Abstract: More complete charge transfer is achieved in a CMOS or CCD imager by reducing the spacing in the gaps between gates in each pixel cell, and/or by providing a lightly doped region between adjacent gates in each pixel cell, and particularly at least between the charge collecting gate and the gate downstream to the charge collecting gate. To reduce the gaps between gates, an insulator cap with spacers on its sidewalls is formed for each gate over a conductive layer. The gates are then etched from the conductive layer using the insulator caps and spacers as hard masks, enabling the gates to be formed significantly closer together than previously possible, which, in turn increases charge transfer efficiency. By providing a lightly doped region between adjacent gates, a more complete charge transfer is effected from the charge collecting gate.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: July 7, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Howard E. Rhodes
  • Patent number: 7537939
    Abstract: In the manufacture of semiconductors, it is often necessary to characterize the effect of line width and line width shape on yield. In an example embodiment, there is a method (200) for randomizing exposure conditions across a substrate. The method comprises generating a list of random numbers (210). A random number is mapped (220) to an exposure field, forming a list of random numbers and corresponding exposure fields. The list or random numbers and corresponding exposure fields is sorted (230) by random number. To each exposure field in the list sorted by random number, an exposure dose is assigned (240). The list is sorted is sorted by exposure field (250).
    Type: Grant
    Filed: April 27, 2004
    Date of Patent: May 26, 2009
    Assignee: NXP B.V.
    Inventors: David Ziger, Steven Qian
  • Patent number: 7504278
    Abstract: An image sensor is disclosed where individual photo diodes of the respective unit cells separated by an element isolating layer are physically integrated into a single large scale pixel formed widely on a semiconductor substrate so as to hold the pixels in common. A pixel separation pattern is additionally formed on a portion of the large scale photo diode formed so as to electrically separate them. An optimization of the light receiving area of the photo diode, a minimization of the intrusion area of an element isolating layer, and so on are achieved, so that the photo diode recovers an area occupied by an intrusion of the element isolating layer, thus maximizing the light receiving area in an optimal scale and easily preventing electrical impacts between the respective unit cells.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: March 17, 2009
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: James Jang
  • Publication number: 20090011533
    Abstract: Isolation methods and devices for isolating regions of a semiconductor device. The isolation method and structure include forming an isolating trench in an active area and filling the trench with a doped conductive material containing silicon. Suitable conductive materials containing silicon include polysilicon and silicon-germanium. There is also provided a method and structure for isolating the regions by providing a trench in an active area of a substrate, growing an epitaxial layer in the trench to fill the trench or to partially fill the trench and depositing an insulating material over the epitaxial layer and within the trench to completely fill the trench.
    Type: Application
    Filed: September 11, 2008
    Publication date: January 8, 2009
    Inventors: Chandra Mouli, Howard Rhodes
  • Patent number: 7470560
    Abstract: A deep implanted region of a first conductivity type located below a transistor array of a pixel sensor cell and adjacent a doped region of a second conductivity type of a photodiode of the pixel sensor cell is disclosed. The deep implanted region reduces surface leakage and dark current and increases the capacitance of the photodiode by acting as a reflective barrier to photo-generated charge in the doped region of the second conductivity type of the photodiode. The deep implanted region also provides improved charge transfer from the charge collection region of the photodiode to a floating diffusion region adjacent the gate of the transfer transistor.
    Type: Grant
    Filed: May 17, 2006
    Date of Patent: December 30, 2008
    Assignee: Aptina Imaging Corporation
    Inventors: Howard Rhodes, Chandra Mouli
  • Patent number: 7470965
    Abstract: In a solid-state imaging device of the present invention, light-sensitive elements 54, each of which includes a light receiving section capable of receiving light, are arranged in a matrix form at regular spacings in a photoreceiving region provided on a semiconductor substrate 51. A plurality of detecting electrodes 53 are provided on the semiconductor substrate 51 corresponding to the light-sensitive elements 54 for detecting an electrical charge generated by each light-sensitive element 54. A plurality of interconnections 57 coat the detecting electrodes 53, and apply a voltage thereto. A plurality of reflecting walls 62 are formed in a grid pattern over the interconnection 57 so as to partition the light-sensitive elements 54 individually for reflecting a portion of light entering the semiconductor substrate 51 from above onto the light receiving section of each light-sensitive element 54. The plurality of reflecting walls 62 are electrically insulated from the interconnections 57.
    Type: Grant
    Filed: July 20, 2004
    Date of Patent: December 30, 2008
    Assignee: Panasonic Corporation
    Inventor: Toshihiro Kuriyama
  • Publication number: 20080283726
    Abstract: A backside illuminated imaging device performs imaging by illuminating light from a back side of a p substrate to generate electric charges in the substrate based on the light and reading out the electric charges from a front side of the substrate. The device includes n layers located in the substrate and on an identical plane near a front side surface of the substrate and accumulating the electric charges; n+ layers between the respective n layers and the front side of the substrate, the n+ layers having an exposed surface exposed on the front side surface of the substrate and functioning as overflow drains for discharging unnecessary electric charges accumulated in the n layers; p+ layers between the respective n+ layers and the n layers and functioning as overflow barriers of the overflow drains; and an electrode connected to the exposed surface of each of the n+ layers.
    Type: Application
    Filed: September 17, 2007
    Publication date: November 20, 2008
    Inventors: Shinji UYA, Masanori Nagase, Yosuke Nakahashi, Toru Hachiya
  • Patent number: 7449732
    Abstract: The substrate with electrodes is formed of a transparent material onto which is deposited a film (1) of a transparent conductive material of thickness e1 and of refractive index n1, said film being structured to form a set of electrodes (1a) whose contours (8) delimit insulating spaces (3), wherein the insulating spaces (3) are filled with a transparent dielectric material of thickness e2 and of refractive index n2 so that the respective thicknesses of the conductive material and the dielectric material are inversely proportional to the values of the refractive indices of said materials and said dielectric material forms neither depressions nor beads at the contour (8) of the electrodes. A hardcoating layer (7) may be disposed between the substrate (5) and the electrodes and a protective film (9) added. The substrate with electrodes is obtained by UV irradiation through a single mask.
    Type: Grant
    Filed: March 5, 2004
    Date of Patent: November 11, 2008
    Assignee: Asulab S.A.
    Inventors: Joachim Grupp, Gian-Carlo Poli, Pierre-Yves Baroni, Estelle Wagner, Patrik Hoffmann
  • Patent number: RE41340
    Abstract: A lock in pinned photodiode photodetector includes a plurality of output ports which are sequentially enabled. Each time when the output port is enabled is considered to be a different bin of time. A specified pattern is sent, and the output bins are investigated to look for that pattern. The time when the pattern is received indicates the time of flight. A CMOS active pixel image sensor includes a plurality of pinned photodiode photodetectors that share buffer transistors. In one configuration, the charge from two or more pinned photodiodes may be binned together and applied to the gate of a shared buffer transistor.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: May 18, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Vladimir Berezin, Alexander Krymski, Eric R. Fossum
  • Patent number: RE42292
    Abstract: A lock in pinned photodiode photodetector includes a plurality of output ports which are sequentially enabled. Each time when the output port is enabled is considered to be a different bin of time. A specified pattern is sent, and the output bins are investigated to look for that pattern. The time when the pattern is received indicates the time of flight. A CMOS active pixel image sensor includes a plurality of pinned photodiode photodetectors that use a common output transistor. In one configuration, the charge from two or more pinned photodiodes may be binned together and applied to the gate of an output transistor.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: April 12, 2011
    Assignee: Round Rock Research, LLC
    Inventors: Vladimir Berezin, Alexander I. Krymski, Eric R. Fossum
  • Patent number: RE44482
    Abstract: A lock in pinned photodiode photodetector includes a plurality of output ports which are sequentially enabled. Each time when the output port is enabled is considered to be a different bin of time. A specified pattern is sent, and the output bins are investigated to look for that pattern. The time when the pattern is received indicates the time of flight A CMOS active pixel image sensor includes a plurality of pinned photodiode photodetectors that use a common output transistor. In one configuration, the charge from two or more pinned photodiodes may be binned together and applied to the gate of an output transistor.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: September 10, 2013
    Assignee: Round Rock Research, LLC
    Inventors: Vladimir Berezin, Alexander I. Krymski, Eric R. Fossum