Charge Transfer Device (e.g., Ccd, Etc.) Patents (Class 438/75)
  • Patent number: 10290671
    Abstract: An image sensor device includes a first substrate, an interconnect structure, a conductive layer, a conductive via and a second substrate. The first substrate includes a first region including a pixel array and a second region including a circuit. The interconnect structure is over the pixel array or the circuit. The interconnect structure electrically connecting the circuit to the pixel array. The conductive layer is on the interconnect structure. The conductive via passes through the second substrate and at least partially embedded in the conductive layer. The second substrate is over the conductive layer.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-De Wang, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Jeng-Shyan Lin
  • Patent number: 9553122
    Abstract: A backside illuminated image sensor includes a substrate, a backside passivation layer disposed on backside of the substrate, and a transparent conductive layer disposed on the backside passivation layer.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: January 24, 2017
    Assignee: INTELLECTUAL VENTURES II LLC
    Inventors: Jaroslav Hynecek, Leonard Forbes, Homayoon Haddad, Thomas Joy
  • Patent number: 9450004
    Abstract: An encapsulated semiconductor device includes a device die with a semiconductor device fabricated thereon. A carrier layer opposite the device die covers the semiconductor device. A dam supports the carrier layer above the device die, the dam being located therebetween. The semiconductor device further includes a first sealant portion for attaching the dam to the device die, and a means for attaching the dam to the carrier layer. The device die, the dam, and the carrier layer form a sealed cavity enclosing the semiconductor device. A method of encapsulating semiconductor devices formed on a device wafer includes forming an assembly including a carrier wafer and a plurality of dams thereon. After the step of forming, the method attaches the plurality of dams to the device wafer to form a respective plurality of encapsulated semiconductor devices.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: September 20, 2016
    Assignee: OmniVision Technologies, Inc.
    Inventors: Chih-Hung Tu, Wei-Feng Lin
  • Patent number: 9379159
    Abstract: A method of fabricating an image sensor includes forming a pixel array in an imaging region of a semiconductor substrate and forming a trench in a peripheral region of the semiconductor substrate after forming the pixel array. The peripheral region is on a perimeter of the imaging region. The trench is filled with an insulating material. An interconnect layer is formed after filling the trench with insulating material. A first wafer is bonded to a second wafer. The first wafer includes the interconnect layer and the semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the insulating material. A via cavity is formed through the insulating material. The via cavity extends down to a second interconnect layer of the second wafer. The via cavity is filled with a conductive material to form a via. The insulating material insulates the conductive material from the semiconductor substrate.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: June 28, 2016
    Assignee: OmniVision Technologies, Inc.
    Inventors: Yin Qian, Dyson H. Tai, Jin Li, Chen-Wei Lu, Howard E. Rhodes
  • Patent number: 9357145
    Abstract: The present description describes a method and apparatus for using a single exposure area scan interline transfer CCD imaging devices in TDI scanning mode. The user is enabled to obtain a high resolution area-scan image with very high sensitivity from a conventional interline transfer CCD imager. The user may select the number of TDI stages, and in some cases of multi-tap CCD structures, obtain a two dimensional area-scan image. Utilizing a conventional interline CCD imager for TDI scanning allows a normal image to be produced by switching the mode back and forth between TDI and conventional area scan imaging.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: May 31, 2016
    Assignee: Imperx, Inc.
    Inventor: Petko Dimitrov Dinev
  • Patent number: 9219100
    Abstract: A solid-state image pickup unit including a pixel section having a plurality of unit pixels two-dimensionally arranged in a matrix formation, wherein a unit pixel includes a conductive region of a first conductivity type having a surface adjacent to a multilayer wiring layer, a charge accumulation region of a second conductivity type formed within the first conductive region, wherein the charge accumulation region is separated from the surface of the conductive region adjacent to the multilayer wiring layer by a separation section, and a contact disposed in the conductive region, the contact electrically connecting the charge accumulation region and an external wire of the multilayer wiring layer.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: December 22, 2015
    Assignee: Sony Corporation
    Inventors: Tetsuji Yamaguchi, Kazunori Nagahata, Toshihiro Miura, Kaori Takimoto
  • Patent number: 9153621
    Abstract: A process of forming a back side illumination (BSI) image sensor is disclosed. An n-type implant is formed in a semiconductor substrate, and a p-type implant region, surrounding n-type in each pixel, is formed in the n-type implant such that in cross sectional view an n-type implant region is sandwiched between the two p-type implant regions. A transfer gate is formed on the semiconductor substrate such that the transfer gate entirely covers the n-type implant region and at least partially covers each of the p-type implant regions. A floating diffusion is formed in one of the p-type implant regions.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: October 6, 2015
    Assignee: Himax Imaging, Inc.
    Inventors: Yang Wu, Inna Patrick
  • Patent number: 9035311
    Abstract: An organic light emitting diode (OLED) display device and a method of fabricating the same are provided. The OLED display device includes a substrate having a thin film transistor region and a capacitor region, a buffer layer disposed on the substrate, a gate insulating layer disposed on the substrate, a lower capacitor electrode disposed on the gate insulating layer in the capacitor region, an interlayer insulating layer disposed on the substrate, and an upper capacitor electrode disposed on the interlayer insulating layer and facing the lower capacitor electrode, wherein regions of each of the buffer layer, the gate insulating layer, the interlayer insulating layer, the lower capacitor electrode, and the upper capacitor electrode have surfaces in which protrusions having the same shape as grain boundaries of the semiconductor layer are formed. The resultant capacitor has an increased surface area, and therefore, an increased capacitance.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 19, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byoung-Keon Park, Tae-Hoon Yang, Jin-Wook Seo, Soo-Beom Jo, Dong-Hyun Lee, Kil-Won Lee, Maxim Lisachenko, Yun-Mo Chung, Bo-Kyung Choi, Jong-Ryuk Park, Ki-Yong Lee
  • Patent number: 9029969
    Abstract: There is provided an imaging element including a transmission channel region provided in an optical black pixel region shielded from light from an outside of a semiconductor substrate by a light shielding film, for transmitting a charge existing inside the semiconductor substrate of the optical black pixel region to an outside of the optical black pixel region.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: May 12, 2015
    Assignee: Sony Corporation
    Inventor: Suzunori Endo
  • Patent number: 8994139
    Abstract: A lateral overflow drain and a channel stop are fabricated using a double mask process. Each lateral overflow drain is formed within a respective channel stop. Due to the use of two mask layers, one edge of each lateral overflow drain is aligned, or substantially aligned, with an edge of a respective channel stop.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: March 31, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Edmund K. Banghart, Eric G. Stevens, Hung Q. Doan
  • Patent number: 8993369
    Abstract: A method for manufacturing a solid-state imaging device in which: photo sensor portions are formed in a silicon layer over a substrate, a first conductivity type region being included in the photo sensor portions and a second conductivity type region being formed in the silicon layer implanted from a rear-surface of the solid-state imaging device by ion implantation; a wiring portion is formed above the silicon layer; and a supporting substrate is bonded to the wiring portion, wherein, the solid-state imaging device is configured for receiving incident light via the rear-surface of the solid-state imaging device.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: March 31, 2015
    Assignee: Sony Corporation
    Inventors: Yasushi Maruyama, Hideshi Abe, Hiroyuki Mori
  • Patent number: 8987041
    Abstract: Certain embodiments provide method for manufacturing a solid-state imaging device, including forming an electrode and forming a second impurity layer. The electrode is formed on a semiconductor substrate including a first impurity layer of a first conductivity type on a surface. The second impurity layer is a second conductivity type and is formed by implanting an impurity of a second conductivity type into the first impurity layer in an oblique direction with respect to the surface of the semiconductor substrate on the condition that the impurity penetrates an end portion of the electrode, based on a position of the electrode. The second impurity layer is bonded to the first impurity layer to constitute a photodiode, and a portion of the second impurity layer is disposed under the electrode.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ken Tomita, Atsushi Sasaki
  • Patent number: 8969875
    Abstract: The present invention relates to a thin film transistor substrate and method for fabricating the same which can secure an alignment margin and reduce the number of mask steps. A thin transistor substrate according to the present invention includes a gate line and a data line crossing each other to define a pixel, a gate metal pattern under the data line, a thin film transistor having a gate electrode, a source electrode and a drain electrode in the pixel, and a pixel electrode connected to the drain electrode of the thin film transistor by a connection electrode, wherein the data line has a plurality of first slits to disconnect the gate metal pattern from the gate line.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: March 3, 2015
    Assignee: LG Display Co., Ltd.
    Inventor: Seung Hee Nam
  • Publication number: 20150042854
    Abstract: According to one embodiment of the present invention, a solid-state imaging device is provided. The solid-state imaging device includes a first-conductivity-type semiconductor region and a second-conductivity-type semiconductor region. The first-conductivity-type semiconductor region is disposed for each pixel of a captured image. The second-conductivity-type semiconductor region constitutes a photoelectric conversion element by a PN junction with the first-conductivity-type semiconductor region, and has second-conductivity-type impurity concentration that decreases from the center of the photoelectric conversion element toward a transfer gate side for transferring signal charge.
    Type: Application
    Filed: January 22, 2014
    Publication date: February 12, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Motohiro MAEDA, Nagataka Tanaka
  • Patent number: 8947593
    Abstract: A solid-state image sensing apparatus includes a solid-state image sensing device, signal processing circuit device, and a multi-layer wiring package. The solid-state image sensing device has a pixel in an image sensing area thereof. The pixel receives incident light and generate a signal electric charge. The signal processing circuit device is arranged to face the image sensing area and applies signal processing to a signal output from the solid-state image sensing device. The multi-layer wiring package has wiring layers, the solid-state image sensing device, and the signal processing circuit device. Each of the wiring layers is laminated via an insulator. The multi-layer wiring package is formed such that a first wiring layer provided between the solid-state image sensing device and the signal processing circuit device has a greater thickness than second wiring layers and has heat conductivity higher than or equal to heat conductivity of the second wiring layers.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: February 3, 2015
    Assignee: Sony Corporation
    Inventors: Hiroki Hagiwara, Keiji Sasano, Hiroaki Tanaka, Yuki Tuji, Tsuyoshi Watanabe, Koji Tsuchiya, Kenzo Tanaka, Takaya Wada, Noboru Kawabata, Hirokazu Yoshida, Hironori Yokoyama
  • Patent number: 8946795
    Abstract: Embodiments of a pixel including a photosensitive region formed in a surface of a substrate and an overflow drain formed in the surface of the substrate at a distance from the photosensitive area, an electrical bias of the overflow drain being variable and controllable. Embodiments of a pixel including a photosensitive region formed in a surface of a substrate, a source-follower transistor coupled to the photosensitive region, the source-follower transistor including a drain, and a doped bridge coupling the photosensitive region to the drain of the source-follower transistor.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: February 3, 2015
    Assignee: OmniVision Technologies, Inc.
    Inventors: Gang Chen, Sing-Chung Hu, Duli Mao, Hsin-Chih Tai, Yin Qian, Vincent Venezia, Rongsheng Yang, Howard E. Rhodes
  • Patent number: 8946845
    Abstract: The invention describes in detail a solid-state CMOS image sensor, specifically a CMOS image sensor pixel that has stacked photo-sites, high sensitivity, and low dark current. The pixels have incorporated therein special potential barriers under the standard pinned photodiode region that diverts the photo-generated electrons from a deep region within the silicon bulk to separate storage structures located at the surface of the silicon substrate next to the pinned photodiode. The storage structures are p channel BCMD transistors that are biased to a low dark current generation mode during a charge integration period. The signal readout from the BCMD is nondestructive, therefore, without kTC noise generation. Thus a single pixel is capable of detecting several color-coded signals while using fewer or without using any light absorbing color filters on top of the pixel.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: February 3, 2015
    Assignee: Aptina Imaging Corporation
    Inventors: Jaroslav Hynecek, Hirofumi Komori, Xia Zhao
  • Patent number: 8945967
    Abstract: A photosensitive imaging device and a method for forming a semiconductor device are provided. The method includes: providing a first device layer formed on a first substrate, wherein a conductive top bonding pad layer is formed on the first device layer; providing a continuous second device layer formed on a second substrate, wherein a continuous conductive adhesion layer is formed on the continuous second device layer; bonding the first device layer with the second device layer, where the top bonding pad layer on the first device layer is directly connected with the conductive continuous adhesion layer on the continuous second device layer; removing the second substrate; selectively etching the continuous second device and the continuous conductive adhesion layer to form a groove array; and filling up the groove array with an insulation material to form a plurality of second devices. Alignment accuracy may be improved.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 3, 2015
    Assignee: Lexvu Opto Microelectronics Technology (Shanghai) Ltd
    Inventors: Zhiwei Wang, Jianhong Mao, Fengqin Han, Lei Zhang, Deming Tang
  • Publication number: 20150014750
    Abstract: A solid-state imaging apparatus includes a semiconductor substrate in which a charge transfer section configured to transfer a charge generated in a photoelectric conversion section is formed. The semiconductor substrate includes a surface that is formed in a convex shape in an area in which the charge transfer section is formed.
    Type: Application
    Filed: July 3, 2014
    Publication date: January 15, 2015
    Inventor: Tomokazu Ohchi
  • Publication number: 20150002719
    Abstract: A solid-state imaging device according to the present disclosure includes: a pixel region which includes: pixel plugs formed above and electrically connected to a charge accumulation and diffusion layer, the pixel plugs respectively corresponding to pixels; lower pixel electrodes formed on and electrically connected to the pixel plugs, respectively, the lower pixel electrodes respectively corresponding to the pixels; an organic photoelectric conversion film formed on and electrically connected to the lower pixel electrodes; and an upper pixel electrode formed on and electrically connected to the organic photoelectric conversion film, and in which top surfaces of a global interconnect, a light shielding film, and a first AI pad formed in an uppermost layer of a multilayer interconnect structure disposed in a peripheral region is above a bottom surface of the organic photoelectric conversion film, the peripheral region being peripheral to the pixel region.
    Type: Application
    Filed: September 16, 2014
    Publication date: January 1, 2015
    Inventors: Shunsuke ISONO, Tetsuya UEDA, Tetsuo SATAKE, Takashi HYAKUSHIMA, Kenji TAKI
  • Publication number: 20150001376
    Abstract: An image pickup device includes: a photodiode provided in a silicon substrate, and configured to generate electric charge corresponding to an amount of received light, by performing photoelectric conversion; and a transfer transistor provided at an epitaxial layer on the silicon substrate, and configured to transfer the electric charge generated in the photodiode, wherein the transfer transistor includes a gate electrode and a channel region, the gate electrode being embedded in the epitaxial layer, and the channel region surrounding the gate electrode, and the channel region has, in a thickness direction, a concentration gradient in which a curvature of a potential gradient is free from a mixture of plus and minus signs.
    Type: Application
    Filed: June 24, 2014
    Publication date: January 1, 2015
    Inventor: Yuki Miyanami
  • Publication number: 20140370645
    Abstract: An improvement is achieved in the performance of a semiconductor device. In a method of manufacturing the semiconductor device, in an n-type semiconductor substrate, a p-type well as a p-type semiconductor region forming a part of a photodiode is formed and a gate electrode of a transfer transistor is formed. Then, after an n-type well as an n-type semiconductor region forming the other part of the photodiode is formed, a microwave is applied to the semiconductor substrate to heat the semiconductor substrate. Thereafter, a drain region of the transfer transistor is formed.
    Type: Application
    Filed: May 25, 2014
    Publication date: December 18, 2014
    Applicant: Renesas Electronics Corporation
    Inventor: Tadashi Yamaguchi
  • Patent number: 8883542
    Abstract: A solid-state imaging device capable of reducing an eclipse (blocking) of an incident light at a circumferential portion of a light receiving portion and realizing a larger angle of view and high-speed driving. A single-layer transfer electrode configuration of forming first transfer electrodes and second transfer electrodes by one polysilicon layer is adopted. Two shunt wirings extending in a horizontal direction are formed on the first transfer electrodes connected in a horizontal direction and, for example, four-phase transfer pulses are supplied to first transfer electrodes and second transfer electrodes on transfer channels through low-resistance shunt wirings extending in the horizontal direction.
    Type: Grant
    Filed: July 7, 2009
    Date of Patent: November 11, 2014
    Assignee: Sony Corporation
    Inventor: Hideo Kanbe
  • Patent number: 8852988
    Abstract: A semiconductor package and a method for manufacturing the same are provided. The semiconductor package includes a semiconductor chip having a first surface, a second surface and a pixel area, first adhesion patterns disposed on the first surface, second adhesion patterns disposed between the first adhesion patterns and the pixel area and disposed on the first surface, and external connection terminals disposed on the second surface, wherein the second adhesion patterns and the external connection terminals are disposed to overlap each other.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: October 7, 2014
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Hyung-Sun Jang, Woon-Seong Kwon, Tae-Je Cho, Un-Byoung Kang, Jung-Hwan Kim
  • Patent number: 8816462
    Abstract: An image sensor pixel includes a photodiode region having a first polarity doping type disposed in a semiconductor layer. A pinning surface layer having a second polarity doping type is disposed over the photodiode region in the semiconductor layer. The second polarity is opposite from the first polarity. A first polarity charge layer is disposed proximate to the pinning surface layer over the photodiode region. An contact etch stop layer is disposed over the photodiode region proximate to the first polarity charge layer. The first polarity charge layer is disposed between the pinning surface layer and the contact etch stop layer such that first polarity charge layer cancels out charge having a second polarity that is induced in the contact etch stop layer. A passivation layer is also disposed over the photodiode region between the pinning surface layer and the contact etch stop layer.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: August 26, 2014
    Assignee: OmniVision Technologies, Inc.
    Inventors: Howard E. Rhodes, Dajiang Yang, Gang Chen, Duli Mao, Vincent Venezia
  • Patent number: 8815630
    Abstract: Back side illumination (BSI) sensors, manufacturing methods thereof, and semiconductor device manufacturing methods are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes providing a workpiece having a front side and a back side opposite the front side. An integrated circuit is formed on the workpiece, and a first insulating material is formed on the back side of the workpiece. A second insulating material is formed over the first insulating material. The second insulating material is patterned to form a grid on the back side of the workpiece.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: August 26, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Chin-Nan Wu, Chun Che Lin, Yu-Ku Lin
  • Patent number: 8778778
    Abstract: According to an embodiment, an active layer is formed on a first surface of a semiconductor substrate, a wiring layer is formed on the active layer, and an insulating layer is formed covering the wiring layer. The first surface of the semiconductor substrate is bonded to a support substrate via the insulating layer, and the semiconductor substrate bonded to the support substrate is thinned leaving the semiconductor substrate having a predetermined thickness which covers the active layer from a second surface. At least a part of area of the thinned semiconductor substrate is removed to expose the active layer.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: July 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumasa Tanida, Masahiro Sekiguchi, Masayuki Dohi, Tsuyoshi Matsumura, Hideo Numata, Mari Otsuka, Naoko Yamaguchi, Takashi Shirono, Satoshi Hongo
  • Patent number: 8772844
    Abstract: Capacitance between a detection capacitor and a reset transistor is the largest among the capacitances between the detection capacitor and transistors placed around the detection capacitor. In order to reduce this capacitance, it is effective to reduce the channel width of the reset transistor. It is possible to reduce the effective channel width by distributing, in the vicinity of the channel of the reset transistor and the boundary line between an active region and an element isolation region, ions which enhance the generation of carriers of an opposite polarity to the channel.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: July 8, 2014
    Assignee: Wi Lan, Inc.
    Inventors: Motonari Katsuno, Ryouhei Miyagawa, Masayuki Matsunaga
  • Patent number: 8759141
    Abstract: A backside illuminated image sensor is provided which includes a substrate having a front side and a backside, a sensor formed in the substrate at the front side, the sensor including at least a photodiode, and a depletion region formed in the substrate at the backside, a depth of the depletion region is less than 20% of a thickness of the substrate.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: June 24, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Hsuan Hsu, Han-Chi Liu, Ching-Chun Wang
  • Patent number: 8754458
    Abstract: A solid-state imaging device includes an element forming region on the surface of a substrate, element isolating parts that isolate pixels, each of which is formed with a trench and a buried film, an opto-electric conversion element, and a buried-channel MOS transistor. The buried-channel MOS transistor includes a source region and a drain region, formed in the element forming region, that have a conductivity type opposite to that of the element forming region, a channel region having first and second impurity diffusion regions, which have a conductivity type opposite to that of the element forming region, and a gate electrode. Each first impurity diffusion region is formed between the source region and drain region on a side adjacent to one element isolating part. The second impurity diffusion region is formed across the region between the source region and drain region.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: June 17, 2014
    Assignee: Sony Corporation
    Inventor: Naoki Saka
  • Patent number: 8748957
    Abstract: A coherent spin field effect transistor is provided by depositing a ferromagnetic base like cobalt on a substrate. A magnetic oxide layer is formed on the cobalt by annealing at temperatures on the order of 1000° K to provide a few monolayer thick layer. Where the gate is cobalt, the resulting magnetic oxide is Co3O4(111). Other magnetic materials and oxides may be employed. A few ML field of graphene is deposited on the cobalt (III) oxide by molecular beam epitaxy, and a source and drain are deposited of base material. The resulting device is scalable, provides high on/off rates, is stable and operable at room temperature and easily fabricated with existing technology.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: June 10, 2014
    Assignee: Quantum Devices, LLC
    Inventors: Jeffry Kelber, Peter Dowben
  • Patent number: 8716719
    Abstract: Provided is a solid-state imaging device including: a first-conductivity-type substrate; a second-conductivity-type well formed in a surface side of the first-conductivity-type substrate; a photoelectric conversion area configured with a first-conductivity-type-impurity area formed in the second-conductivity-type well to convert incident light to charges; a first-conductivity-type-charge retaining area configured with the first-conductivity-type-impurity area formed in the second-conductivity-type well to retain the charges converted by the photoelectric conversion area until the charges are read out; a charge voltage conversion area configured with the first-conductivity-type-impurity area formed in the second-conductivity-type well to convert the charges retained in the charge retaining area to a voltage; and a first-conductivity-type-layer area configured by forming a first-conductivity-type-in a convex shape from a boundary between the first-conductivity-type substrate and the second-conductivity-type wel
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: May 6, 2014
    Assignee: Sony Corporation
    Inventors: Yusuke Matsumura, Takashi Machida
  • Patent number: 8711280
    Abstract: A solid-state image sensing apparatus includes a solid-state image sensing device, signal processing circuit device, and a multi-layer wiring package. The solid-state image sensing device has a pixel in an image sensing area thereof. The pixel receives incident light and generate a signal electric charge. The signal processing circuit device is arranged to face the image sensing area and applies signal processing to a signal output from the solid-state image sensing device. The multi-layer wiring package has wiring layers, the solid-state image sensing device, and the signal processing circuit device. Each of the wiring layers is laminated via an insulator. The multi-layer wiring package is formed such that a first wiring layer provided between the solid-state image sensing device and the signal processing circuit device has a greater thickness than second wiring layers and has heat conductivity higher than or equal to heat conductivity of the second wiring layers.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: April 29, 2014
    Assignee: Sony Corporation
    Inventors: Hiroki Hagiwara, Keiji Sasano, Hiroaki Tanaka, Yuki Tuji, Tsuyoshi Watanabe, Koji Tsuchiya, Kenzo Tanaka, Takaya Wada, Noboru Kawabata, Hirokazu Yoshida, Hironori Yokoyama
  • Patent number: 8709855
    Abstract: A conductive light shield is formed over a first dielectric layer of a via level in a metal interconnect structure. The conductive light shield is covers a floating drain of an image sensor pixel cell. A second dielectric layer is formed over the conductive light shield and at least one via extending from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive image sensor pixel cell is less prone to noise due to the blockage of light over the floating drain by the conductive light shield.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: April 29, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Zhong-Xiang He, Kevin N. Ogg, Richard J. Rassel, Robert M. Rassel
  • Patent number: 8691637
    Abstract: Disclosed herein is a solid-state image pickup device including: a photoelectric conversion section configured to convert incident light into a signal charge; a transfer transistor configured to read the signal charge from the photoelectric conversion section and transfer the signal charge; and an amplifying transistor configured to amplify the signal charge read by the transfer transistor, wherein a compressive stress film having a compressive stress is formed on the amplifying transistor.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: April 8, 2014
    Assignee: Sony Corporation
    Inventor: Shinichi Arakawa
  • Patent number: 8686483
    Abstract: A photosite may include, in a semi-conductor substrate, a photodiode pinched in the direction of the depth of the substrate including a charge storage zone, and a charge transfer transistor to transfer the stored charge. The charge storage zone may include a pinching in a first direction passing through the charge transfer transistor defining a constriction zone adjacent to the charge transfer transistor.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: April 1, 2014
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Julien Michelot, Francois Roy, Frederic Lalanne
  • Patent number: 8679870
    Abstract: Provided is a method of manufacturing a semiconductor element having at a cut portion with excellent quality, which minimizes a region on a silicon substrate necessary for cutting, and which prevents cutting water used when cutting by dicing is carried out from entering the semiconductor element. The method of manufacturing a semiconductor element includes: arranging, on the silicon substrate, multiple semiconductor element portions so as to be adjacent to one another; bonding the silicon substrate and a glass substrate together using the resin; and cutting the silicon substrate and the glass substrate, respectively, in a region in which the resin is provided, the cutting the silicon substrate and the glass substrate including: half-cutting the silicon substrate by dicing; cutting the glass substrate by scribing; and dividing the silicon substrate, the glass substrate, and the resin.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: March 25, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Ichiro Kataoka, Kazuya Igarashi
  • Patent number: 8664032
    Abstract: It is an object to provide a CCD solid-state image sensor, in which an area of a read channel is reduced and a rate of a surface area of a light receiving portion (photodiode) to an area of one pixel is increased.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: March 4, 2014
    Assignee: Unisantis Electronics Singapore Pte Ltd.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 8659060
    Abstract: According to one embodiment, a solid-state imaging device includes a semiconductor layer including first and second regions, a pixel portion provided in the first region, electrodes provided in the second region and configured to penetrate the semiconductor layer, and a guard ring provided in the second region and configured to penetrate the semiconductor layer and electrically isolate the pixel portion from the electrodes. An upper surface of the semiconductor layer in the second region is lower than an upper surface of the semiconductor layer in the first region.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: February 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hidetoshi Koike
  • Patent number: 8658477
    Abstract: An exposure mask according to an embodiment of the invention includes a first transmission region where a plurality of dots through which light is shielded or transmitted are arrayed into a matrix form having rows and columns and a second transmission region where a plurality of dots through which the light is shielded or transmitted are arrayed into a matrix form having rows and columns and is disposed adjacent to the first transmission region. The dots arrayed in a row or a column of the first transmission region, which is adjacent to the second transmission region, have an area intermediate between areas of dots arrayed on both sides of the row or the column.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: February 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ken Tomita
  • Patent number: 8653529
    Abstract: In a semiconductor device in which a glass substrate is attached to a surface of a semiconductor die with an adhesive layer being interposed therebetween, it is an object to fill a recess portion of an insulation film formed on a photodiode with the adhesive layer without bubbles therein. In a semiconductor die in which an optical semiconductor integrated circuit including a photodiode having a recess portion of an interlayer insulation film in the upper portion, an NPN bipolar transistor, and so on are formed, generally, a light shield film covers a portion except the recess portion region on the photodiode and except a dicing region. In the invention, an opening slit is further formed in the light shield film, extending from the recess portion to the outside of the recess portion, so as to attain the object.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: February 18, 2014
    Assignee: ON Semiconductor Trading, Ltd.
    Inventors: Shinzo Ishibe, Katsuhiko Kitagawa
  • Patent number: 8642374
    Abstract: An image sensor is described in which the imaging pixels have reduced noise by blocking nitridation in selected areas. In one example, a method includes forming a first and second gate oxide layer over a substrate, forming a layer of photoresist over the first gate oxide layer, applying nitridation to the photoresist and the second gate oxide layer such that the first gate oxide layer is protected from the nitridation by the photoresist, and forming a polysilicon gate over the first and second gate oxide layers.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: February 4, 2014
    Assignee: OmniVision Technologies, Inc.
    Inventors: Jeong-Ho Lyu, Sohei Manabe, Howard Rhodes
  • Patent number: 8629482
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes implanting impurity ions to a semiconductor layer in which an electrode is embedded; forming a light absorption film which absorbs laser light at a side of the electrode to which the laser light is irradiated; and activating the impurity ions by irradiating laser light to the semiconductor layer at which the light absorption film is formed in the forming.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: January 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoyasu Kudo, Kenichi Yoshino, Masaki Kamimura
  • Patent number: 8574941
    Abstract: A method for manufacturing a solid-state imaging device in which a charge generator that detects an electromagnetic wave and generates signal charges is formed on a semiconductor substrate and a negative-charge accumulated layer having negative fixed charges is formed above a detection plane of the charge generator. The method includes the steps of: forming an oxygen-feed film capable of feeding oxygen on the detection plane of the charge generator; forming a metal film that covers the oxygen-feed film on the detection plane of the charge generator; and performing heat treatment for the metal film in an inactive atmosphere to thereby form an oxide of the metal film between the metal film and the oxygen-feed film on the detection plane of the charge generator, the oxide being to serve as the negative-charge accumulated layer.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: November 5, 2013
    Assignee: Sony Corporation
    Inventors: Susumu Hiyama, Tomoyuki Hirano
  • Patent number: 8558335
    Abstract: A solid-state imaging device includes a photoelectric conversion unit that is formed on a semiconductor substrate, a reading unit that reads signal charges of the photoelectric conversion unit, a gate insulating film and an electrode disposed thereon that constitute the reading unit, a light shielding film that covers the electrode, and an antireflection film that is formed on the photoelectric conversion unit and is constituted by films of four or more layers. The film of the lower layer of the antireflection film is also used as a stopper film during patterning, and a gap between the end of the light shielding film and the semiconductor substrate which is defined by interposing a plurality of films of the lower layer of the antireflection film is set so as to be smaller than the thickness of the gate insulating film.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: October 15, 2013
    Assignee: Sony Corporation
    Inventor: Mitsuhiro Nagano
  • Patent number: 8558234
    Abstract: Highly efficient, low energy, low light level imagers and photodetectors are provided. In particular, a novel class of Della-Doped Electron Bombarded Array (DDEBA) photodetectors that will reduce the size, mass, power, complexity, and cost of conventional imaging systems while improving performance by using a thinned imager that is capable of detecting low-energy electrons, has high gain, and is of low noise.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: October 15, 2013
    Assignee: California Institute of Technology
    Inventors: Shouleh Nikzad, Chris Martin, Michael E. Hoenk
  • Patent number: 8541255
    Abstract: A solid-state imaging device includes a semiconductor substrate; a first conductive region of the semiconductor substrate; a first conductive region on an upper surface side of the first conductive region of the semiconductor substrate; a second conductive region below the first conductive region on the upper surface side of the first conductive region of the semiconductor substrate. The solid-state imaging device further includes a photoelectric conversion region including the first conductive region located on the upper surface side of the first conductive region of the semiconductor substrate and the second conductive region and a transfer transistor transferring charges accumulated in the photoelectric conversion region to a readout region; and a pixel including the photoelectric conversion region and the transfer transistor. The first conductive region, which is included in the photoelectric conversion region, extends to the lower side of a sidewall of a gate electrode of the transfer transistor.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: September 24, 2013
    Assignee: Sony Corporation
    Inventor: Keiji Mabuchi
  • Patent number: 8530267
    Abstract: A method for manufacturing a silicon-based thin film solar cell including a crystalline silicon photoelectric conversion unit which contains a p-type layer (4p), a crystalline i-type silicon photoelectric conversion layer (4ic), and an n-type layer (4nc) stacked in this order from a transparent substrate side is provided. In one example, an n-type silicon-based thin film layer (4na) is formed on the crystalline i-type silicon photoelectric conversion layer (4ic), the n-type silicon-based thin film layer (4na) having an n-type silicon alloy layer having a film thickness of 1-12 nm and being in contact with the crystalline i-type silicon photoelectric conversion layer.
    Type: Grant
    Filed: October 9, 2009
    Date of Patent: September 10, 2013
    Assignee: Kaneka Corporation
    Inventors: Kunta Yoshikawa, Mitsuru Ichikawa, Kenji Yamamoto
  • Patent number: 8519456
    Abstract: A solid-state image pickup device in which electric charges accumulated in a photodiode conversion element are transferred to a second diffusion layer through a first diffusion layer.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: August 27, 2013
    Assignee: Sony Corporation
    Inventors: Atsushi Masagaki, Ikuhiro Yamamura
  • Publication number: 20130217174
    Abstract: An exposure mask according to an embodiment of the invention includes a first transmission region where a plurality of dots through which light is shielded or transmitted are arrayed into a matrix form having rows and columns and a second transmission region where a plurality of dots through which the light is shielded or transmitted are arrayed into a matrix form having rows and columns and is disposed adjacent to the first transmission region. The dots arrayed in a row or a column of the first transmission region, which is adjacent to the second transmission region, have an area intermediate between areas of dots arrayed on both sides of the row or the column.
    Type: Application
    Filed: April 5, 2013
    Publication date: August 22, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: KABUSHIKI KAISHA TOSHIBA