Making Electromagnetic Responsive Array Patents (Class 438/73)
  • Patent number: 12261233
    Abstract: A dynamic photodiode detector or detector array having a light absorbing region of doped semiconductor material for absorbing photons. Electrons or holes generated by photon absorption are detected with a construction of oppositely heavily doped anode and cathode regions and a heavily doped ground region of the same doping type as the anode region. Photon detection involves switching the device from reverse bias to forward bias to create a depletion region enclosing the anode region. When a photon is then absorbed the electron or hole thereby generated drifts under the electric field induced by the biasing to the depletion region where it causes the anode-to-ground current to increase. Furthermore, the detector is configured such that anode-to-cathode current starts to flow once a threshold number of electrons or holes reaches the depletion region, where the threshold may be one to provide single photon detection.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: March 25, 2025
    Assignee: ActLight SA
    Inventors: Maxim Gureev, Denis Sallin, Serguei Okhonin
  • Patent number: 12261182
    Abstract: An image sensing device includes an image pixel region including active pixels, each active pixel configured to generate an imaging pixel signal through a photoelectric conversion of incident light received by the active pixel, and an optical black pixel region disposed separately from the image pixel region and including a plurality of black pixels and a light blocking layer that blocks incident light from entering the black pixels, each black pixel configured to generate a black pixel signal for correcting dark current. The image pixel region includes a condensing lens layer configured to condense the incident light, and the optical black pixel region includes a dispersion lens layer configured to disperse the incident light.
    Type: Grant
    Filed: December 7, 2022
    Date of Patent: March 25, 2025
    Assignee: SK HYNIX INC.
    Inventor: Eun Khwang Lee
  • Patent number: 12224297
    Abstract: A method of making a semiconductor structure includes forming a pixel array region on a substrate. The method further includes forming a first seal ring region on the substrate, wherein the first seal ring region surrounds the pixel array region, and the first seal ring region includes a first seal ring. The method further includes forming a first isolation feature in the first seal ring region, wherein forming the first isolation feature includes filling a first opening with a dielectric material, wherein the first isolation feature is a continuous structure surrounding the pixel array region. The method further includes forming a second isolation feature between the first isolation feature and the pixel array region, wherein forming the second isolation feature includes filling a second opening with the dielectric material.
    Type: Grant
    Filed: January 19, 2023
    Date of Patent: February 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yun-Wei Cheng, Chun-Wei Chia, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
  • Patent number: 12210936
    Abstract: Methods, systems and apparatus for correcting a result of a quantum computation.
    Type: Grant
    Filed: September 22, 2023
    Date of Patent: January 28, 2025
    Assignee: Google LLC
    Inventors: Jarrod Ryan McClean, Ryan Babbush, Zhang Jiang
  • Patent number: 12206034
    Abstract: A solar cell module comprises: two base plates each including a conductive layer on at least one side; and a plurality of submodules interposed between respective conductive layers of the two base plates. The plurality of submodules each include a plurality of cells connected to each other as a result of a conductive material electrically connecting the respective conductive layers of the two base plates. The two base plates each have a plurality of insulating grooves in a gap between the plurality of submodules. The plurality of insulating grooves of one of the two base plates and the plurality of insulating grooves of an other one of the two base plates define at least one insulating space that prevents short circuiting between adjacent submodules.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: January 21, 2025
    Assignee: ZEON CORPORATION
    Inventor: Yuki Hirose
  • Patent number: 12191335
    Abstract: An image sensor includes a substrate including a first surface and a second surface which is opposite to the first portion, and a pixel isolation portion provided in the substrate and configured to isolate unit pixels from each other. The pixel isolation portion includes a first filling insulation pattern extending from the first surface toward the second surface and having an air gap region, the first filling insulation pattern including a first sidewall and a second sidewall which is opposite to the first sidewall, a conductive structure including a first portion on the first sidewall, a second portion on the second sidewall, and a connection portion connecting the first portion and the second portion, and an insulating liner provided between the first portion and the substrate and between the second portion and the substrate.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: January 7, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Su Park, Kwansik Kim, Changhwa Kim, Taemin Kim, Gyuhyun Lim
  • Patent number: 12113079
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a gate structure on a substrate. A doped region is within the substrate. One or more dielectric materials are within a recess formed by one or more surfaces of the substrate. The doped region is laterally between the gate structure and the recess. A doped epitaxial material is within the recess and between the one or more dielectric materials and the doped region. The doped epitaxial material is asymmetric about a vertical line that extends through a lateral center of the doped epitaxial material.
    Type: Grant
    Filed: June 28, 2023
    Date of Patent: October 8, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yueh-Chuan Lee, Chia-Chan Chen
  • Patent number: 12107112
    Abstract: Groove portions are provided between adjacent photoelectric conversion portions, and sidewall surfaces and bottom surfaces of the groove portions are covered with a first fixed charge film, and open ends of the groove portions are closed by a second fixed charge film with voids inside of the groove portions.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: October 1, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Itaru Oshiyama, Shinichiro Noudo, Yasufumi Miyoshi
  • Patent number: 12092777
    Abstract: According to an embodiment, a radiation detector includes scintillator elements, dielectric multilayer films, and a metal reflective layer. The scintillator elements are arranged in a two-dimensional grid pattern. The dielectric multilayer films are provided between adjacent scintillator elements such that a dielectric multilayer film is adjacent to one of said scintillator elements. The metal reflective layer is provided between adjacent dielectric multilayer films.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: September 17, 2024
    Assignee: CANON MEDICAL SYSTEMS CORPORATION
    Inventors: Yusuke Terao, Tatsuo Osaka, Akihiko Taniguchi
  • Patent number: 12094904
    Abstract: An image sensor includes: on a substrate that includes a first surface and a second surface opposite to the first surface, photoelectric conversion regions located in the substrate, the photoelectric conversion regions being separated from each other; partition layers spaced apart from the first surface and between the photoelectric conversion regions; and pixel separation layers on the partition layers that separate the photoelectric conversion regions from each other.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: September 17, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyoungmok Son, Hyejung Kim
  • Patent number: 12094905
    Abstract: Provided are an image sensor and a manufacturing method thereof. In the image sensor, an insulating layer and a first silicon layer are sequentially on a silicon base. A first isolation structure is in the first silicon layer to define an active area (AA). A doped region is in a part of the first silicon layer in the AA and in a part of the silicon base thereunder. A second silicon layer is in a part of the first silicon layer in the AA and extends into the silicon base. An interconnection structure is on the first silicon layer and electrically connected with a transistor. A second isolation structure is in the silicon base under the first isolation structure and connected to the insulating layer. A passivation layer surrounds the silicon base and is connected to the doped region. A microlens is on the silicon base.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: September 17, 2024
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chih-Ping Chung, Ming-Yu Ho, Saysamone Pittikoun
  • Patent number: 12094992
    Abstract: The present inventive concept relates to a solar cell, a unit cell included in the solar cell, and a method for manufacturing the solar cell, the solar cell comprising: a first unit cell manufactured using any one piece from among a plurality of pieces formed by separating a mother substrate; and a second unit cell coupled to the first unit cell, wherein the first unit cell comprises a first cell electrode provided on a first unit substrate and having conductivity, the second unit cell comprises a second cell electrode provided on a second unit substrate and having conductivity, and the second cell electrode and the first cell electrode are bonded to each other without a bonding material to couple the second unit cell to the first unit cell.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: September 17, 2024
    Assignee: JUSUNG ENGINEERING CO., LTD
    Inventors: JungBae Kim, JunYoung Kang, HyangJu Mun, SeonKi Min, JeongHo Seo, WonSuk Shin, HyunKyo Shin, YoungTae Yoon, KyoungJin Lim
  • Patent number: 12068340
    Abstract: An image sensor includes a substrate having a sensing area, a floating diffusion region arranged in the sensing area, a plurality of photodiodes arranged around the floating diffusion region in the sensing area, and an inter-pixel overflow (IPO) barrier in contact with each of the plurality of photodiodes, the IPO barrier overlapping the floating diffusion region in a vertical direction at a position vertically spaced apart from the floating diffusion region within the sensing area.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: August 20, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sanghyuck Moon, Kyungho Lee, Seungjoon Lee, Minji Jung, Masato Fujita
  • Patent number: 12062548
    Abstract: In an etching method for an oxide semiconductor film according to an embodiment of the present disclosure, a modified layer is formed in the oxide semiconductor film by using a first rare gas and the modified layer is sputtered by using a second rare gas different from the first rare gas.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: August 13, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Akiko Hirata, Tetsuya Tatsumi, Masanaga Fukasawa, Satoshi Hamaguchi, Kazuhiro Karahashi
  • Patent number: 12062679
    Abstract: The present disclosure relates to an image sensor having an image sensing element surrounded by a BDTI structure, and an associated method of formation. In some embodiments, a first image sensing element and a second image sensing element are arranged next to one another within an image sensing die. A pixel dielectric stack is disposed along a back of the image sensing die overlying the image sensing elements. The pixel dielectric stack includes a first high-k dielectric layer and a second high-k dielectric layer. The BDTI structure is disposed between the first image sensing element and the second image sensing element and extends from the back of the image sensor die to a position within the image sensor die. The BDTI structure includes a trench filling layer surrounded by an isolation dielectric stack. The pixel dielectric stack has a composition different from that of the isolation dielectric stack.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: August 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Wen-Chang Kuo, Shih-Han Huang
  • Patent number: 12027538
    Abstract: The present technology relates to an imaging element and an electronic apparatus capable of expanding a saturation signal electric charge amount. A first P-type impurity region, a capacitance expanding portion that forms a PN junction surface with a second P-type impurity region and a first N-type impurity region, and the first N-type impurity region are sequentially provided in a depth direction from a surface side where a wiring layer of a semiconductor substrate is laminated. The second P-type impurity region is formed in a stripe on a plane of the capacitance expanding portion that perpendicularly intersects with the depth direction. The stripe is formed, on the plane of the capacitance expanding portion that perpendicularly intersects with the depth direction, in a direction perpendicular to a side where an electrode that reads accumulated electric charge is formed. The present technology can be applied to an imaging element.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: July 2, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hiroaki Murakami, Bo Ma, Yusuke Kikuchi, Yutaka Tsukano
  • Patent number: 12021104
    Abstract: A semiconductor substrate includes a first main surface and a second main surface opposing each other. The semiconductor substrate includes a first semiconductor region of a first conductivity type, and a plurality of second semiconductor regions constituting pn junctions with the first semiconductor region. The semiconductor substrate includes the plurality of second semiconductor in a side of the second main surface. Each of the plurality of second semiconductor regions includes a first region including a textured surface, and a second region including no textured surface. A thickness of the first region at a deepest position of recesses of the textured surface is smaller than a distance between a surface of the second region and the deepest position in a thickness direction of the semiconductor substrate. The first main surface is a light incident surface of the semiconductor substrate.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: June 25, 2024
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Tomoya Taguchi, Yuki Yoshida, Katsumi Shibayama
  • Patent number: 12003879
    Abstract: The present application discloses a pixel unit and a signal processing method for a pixel unit. The pixel unit includes at least one pixel, and the pixel includes: an N-type main pixel, a P-type main pixel, and a sub-pixel; and the sub-pixel is located between the N-type main pixel and the P-type main pixel; or the pixel includes at least a first pixel and a second pixel that are adjacent to each other; the first pixel includes an N-type main pixel, and the second pixel includes a P-type main pixel; the first pixel and the second pixel share one sub-pixel; the sub-pixel is configured to generate and output a signal difference between the N-type main pixel and the P-type main pixel according to the current.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: June 4, 2024
    Assignee: PEKING UNIVERSITY
    Inventors: Xiaoyan Liu, Liqiao Liu, Gang Du
  • Patent number: 11990493
    Abstract: An image sensor device is provided. The image sensor device includes a semiconductor substrate having a front surface, a back surface opposite to the front surface, and a light-sensing region close to the front surface. The image sensor device includes an insulating layer covering the back surface and extending into the semiconductor substrate. The protection layer has a first refractive index, and the first refractive index is less than a second refractive index of the semiconductor substrate and greater than a third refractive index of the insulating layer, and the protection layer conformally and continuously covers the back surface and extends into the semiconductor substrate. The image sensor device includes a reflective structure surrounded by insulating layer in the semiconductor substrate.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Chieh Fang, Ming-Chi Wu, Ji-Heng Jiang, Chi-Yuan Wen, Chien-Nan Tu, Yu-Lung Yeh, Shih-Shiung Chen, Kun-Yu Lin
  • Patent number: 11963426
    Abstract: A display device includes a sensor having a detection electrode. An optical pattern layer is disposed directly on the sensor and includes a plurality of transmission portions and a light blocking portion. A display panel is disposed on the optical pattern layer. A minimum distance between the detection electrode and the light blocking portion is in a range of 1 micrometer-5 micrometers.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: April 16, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Dae-Young Lee, Gee-Bum Kim, Byung Han Yoo, Sangwoo Kim, Jungha Son, Taekyung Ahn, Yunjong Yeo, Kijune Lee, Jaeik Lim, Min Oh Choi, Chaungi Choi
  • Patent number: 11956416
    Abstract: An image sensing device may include a plurality of test pixel blocks and a signal processing unit. The test pixel blocks may be simultaneously heated to different temperatures. The signal processing unit may be in communication with the test blocks and configured to obtain pixel signals for different colors, respectively, based on dark current information associated with the temperatures of the test pixel blocks.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: April 9, 2024
    Assignee: SK HYNIX INC.
    Inventor: Yun Hui Yang
  • Patent number: 11908878
    Abstract: An image sensor includes a pixel and an isolation structure. The pixel includes a photosensitive region and a circuitry region next to the photosensitive region. The isolation structure is located over the pixel, where the isolation structure includes a conductive grid and a dielectric structure covering a sidewall of the conductive grid, and the isolation structure includes an opening or recess overlapping the photosensitive region. The isolation structure surrounds a peripheral region of the photosensitive region.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Wen-Chang Kuo, Sheng-Chau Chen, Feng-Chi Hung, Sheng-Chan Li
  • Patent number: 11895380
    Abstract: A device includes a substantially planar platform. The device also includes a detector connected to the platform. The device further includes multiple cold fingers including a first cold finger and a second cold finger. Each cold finger has an end portion connected to the platform. Each cold finger is configured to be fluidly coupled to a corresponding cryocooler. Each cold finger is configured to absorb thermal energy generated by the detector. The second cold finger has a flexure region at the end portion.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: February 6, 2024
    Assignee: Raytheon Company
    Inventors: Thomas P. Sprafke, Stephen Marinsek
  • Patent number: 11884044
    Abstract: The present invention relates to a lamination process for producing a multilayer laminate, preferably to a lamination process for producing a photovoltaic (PV) module, and to a PV module laminate.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: January 30, 2024
    Assignee: BOREALIS AG
    Inventors: Stefan Hellstrom, Francis Costa, Jeroen Oderkerk, Bert Broeders
  • Patent number: 11855118
    Abstract: An image sensor device includes a semiconductor substrate, a radiation sensing member, a device layer, and a color filter layer. The semiconductor substrate has a photosensitive region and an isolation region surrounding the photosensitive region. The radiation sensing member is embedded in the photosensitive region of the semiconductor substrate. The radiation sensing member has a material different from a material of the semiconductor substrate, and an interface between the radiation sensing member and the isolation region of the semiconductor substrate includes a direct band gap material. The device layer is under the semiconductor substrate and the radiation sensing member. The color filter layer is over the radiation sensing member and the semiconductor substrate.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Yu Wei, Yen-Liang Lin, Kuo-Cheng Lee, Hsun-Ying Huang, Hsin-Chi Chen
  • Patent number: 11824480
    Abstract: A solar power plant is constructed using a reverse workflow whereby the grid connection that will ultimately feed electricity to the grid is constructed before the array so that one or more transformers and portable charging stations may be deployed onsite to transform grid power so that it can recharge electrically powered heavy equipment including solar pile drivers, truss drivers, and telehandlers as well as electrically powered hand tools such as cordless impact drivers while the plant is constructed. Once complete, the fixed electrical infrastructure and grid connection are used to supply power from the solar power plant to the grid.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: November 21, 2023
    Assignee: Ojjo, Inc.
    Inventor: Jack West
  • Patent number: 11804506
    Abstract: An image sensor includes a two-dimensional array of image sensor pixels, which are formed in a semiconductor layer. Each image sensor pixel is formed in a substrate having a corresponding semiconductor region therein. Each semiconductor region contains at least first and second photoelectric conversion elements, which are disposed at side-by-side locations therein. An electrically insulating isolation region is also provided, which extends at least partially through the semiconductor region and at least partially between the first and second photoelectric conversion elements, which may be configured respectively as first and second semiconductor regions of first conductivity type (e.g., N-type). At least one optically reflective region is also provided, which extends at least partially through the semiconductor region and surrounds at least a portion of at least one of the first and second photoelectric conversion elements. A semiconductor floating diffusion (FD) region (e.g.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: October 31, 2023
    Inventors: Kyungho Lee, Hyuk An, Hyuk Soon Choi
  • Patent number: 11798969
    Abstract: Apparatus and methods for sensing long wavelength light are described herein. A semiconductor device includes: a carrier; a device layer on the carrier; a semiconductor layer on the device layer, and an insulation layer on the semiconductor layer. The semiconductor layer includes isolation regions and pixel regions. The isolation regions are or include a first semiconductor material. The pixel regions are or include a second semiconductor material that is different from the first semiconductor material.
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: October 24, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
  • Patent number: 11735609
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a photodetector region provided in a substrate. A dielectric material is disposed within a trench defined by one or more interior surfaces of the substrate. The trench has a depth that extends from an upper surface of the substrate to within the substrate. A doped silicon material is disposed within the trench and has a sidewall facing away from the doped silicon material. The sidewall contacts a sidewall of the dielectric material along an interface extending along the depth of the trench.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: August 22, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yueh-Chuan Lee, Chia-Chan Chen
  • Patent number: 11721794
    Abstract: A method for manufacturing reflective structure is provided. The method includes the operations as follows. A metallization structure is received. A plurality of conductive pads are formed over the metallization structure. A plurality of dielectric stacks are formed over the conductive pads, respectively, wherein the thicknesses of the dielectric stacks are different. The dielectric stacks are isolated by forming a plurality of trenches over a plurality of intervals between each two adjacent dielectric stacks.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: August 8, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia-Hua Lin, Yao-Wen Chang, Chii-Ming Wu, Cheng-Yuan Tsai, Eugene I-Chun Chen, Tzu-Chung Tsai
  • Patent number: 11711932
    Abstract: A method for manufacturing a photoelectric conversion element includes providing a base structure including a semiconductor substrate having a principal surface, a first electrode located on or above the principal surface, second electrodes which are located on or above the principal surface and which are one- or two-dimensionally arranged, and a photoelectric conversion film covering at least the second electrodes; forming a mask layer on the photoelectric conversion film, the mask layer being conductive and including a covering section covering a portion of the photoelectric conversion film that overlaps the second electrodes in plan view; and partially removing the photoelectric conversion film by immersing the base structure and the mask layer in an etchant.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: July 25, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masaya Hirade, Manabu Nakata, Katsuya Nozawa, Yasunori Inoue
  • Patent number: 11696513
    Abstract: This magnetoresistance effect element includes a first ferromagnetic layer, a second ferromagnetic layer, and a tunnel barrier layer which is interposed between the first and second ferromagnetic layers, wherein the tunnel barrier layer has a spinel structure represented by a compositional formula X1-?Y?O?, and the tunnel barrier layer contains one or more additional elements selected from the group consisting of He, Ne, Ar, Kr, Xe, P, C, B, and Si, and in the compositional formula, X represents one or more elements selected from the group consisting of Mg, Zn, Cd, Ag, Pt, and Pb, Y represents one or more elements selected from the group consisting of Al, Ga, and In, a range of ? is 0<??1, and a range of ? is 0.35???1.7.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: July 4, 2023
    Assignee: TDK CORPORATION
    Inventors: Katsuyuki Nakada, Shinto Ichikawa
  • Patent number: 11688610
    Abstract: A method for forming a semiconductor structure includes forming a pattern having first and second line features extending in a first direction on a substrate. After depositing a photoresist layer on the substrate to cover the pattern, the photoresist layer is patterned to form a cut pattern including first and second cut features exposing portions of the respective first and second line features. In a top view, at least one of the first and second cut features is asymmetrically arranged with respect to a central axis of a corresponding first or second line feature. At least one angled ion implantation is performed to enlarge the first and second cut features in at least one direction perpendicular to the first direction. The portions of the first and second line features exposed by the respective first and second cut features are then removed.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: June 27, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzung-Hua Lin, Yi-Ko Chen, Chia-Chu Liu, Hua-Tai Lin
  • Patent number: 11670660
    Abstract: A pixel array included in an auto-focus image sensor includes a substrate, a plurality of pixels, a deep device isolation region and a plurality of first ground regions. The substrate includes a first surface on which a gate electrode is disposed and a second surface opposite to the first surface. The plurality of pixels are disposed in the substrate, and include a plurality of first pixels configured to detect a phase difference and a plurality of second pixels configured to detect an image. The deep device isolation region is disposed in the substrate, extends substantially vertically from the second surface of the substrate to isolate the plurality of pixels from each other. The plurality of first ground regions are disposed adjacent to the first surface in the substrate and adjacent to only at least some of the plurality of first pixels.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: June 6, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Masato Fujita, Kyungho Lee
  • Patent number: 11665895
    Abstract: A method for manufacturing a semiconductor structure includes forming a first oxide layer on a wafer; forming a silicon nitride layer on the first oxide layer; forming a plurality of trenches; filling an oxide material in the trenches to form a plurality of shallow trench isolation regions; removing the silicon nitride layer without removing the first oxide layer; using a photomask to apply a photoresist for covering a first part of the first oxide layer on a first area and exposing a second part of the first oxide layer on a second area; and removing the second part of the first oxide layer while remaining the first part of the first oxide layer.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: May 30, 2023
    Assignee: eMemory Technology Inc.
    Inventors: Wein-Town Sun, Chun-Hsiao Li
  • Patent number: 11599229
    Abstract: Provided is a display device including a display panel having a plurality of pixel regions, a first insulating layer on the display panel, having a first refractive index, and having a plurality of first openings defined in regions which overlap the plurality of pixel regions, a second insulating layer directly on the first insulating layer and having a plurality of second openings defined in regions which correspond to the plurality of first openings, and a third insulating layer covering the display panel, the first insulating layer, and the second insulating layer and having a second refractive index higher than the first refractive index, wherein the third insulating layer may overlap the plurality of pixel regions on a plane.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: March 7, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jungha Son, Gee-Bum Kim, Sangwoo Kim, Kijune Lee, Taekyung Ahn, Byung Han Yoo, Jaeik Lim, Chaungi Choi
  • Patent number: 11598672
    Abstract: The present invention features a novel design for a bolometric infrared detector focused on LWIR range for human body high-resolution temperature sensing. The present invention incorporates an efficient plasmonic absorber and VO2 nanobeam to facilitate improvement in both aspects—thermal resolution and spatial resolution. The present invention significantly improves the detectivity, NETD, and responsivity for a smaller form-factor detector active area.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: March 7, 2023
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Mohammad Wahiduzzaman Khan, Ozdal Boyraz, Jonathan Sullivan, Jaeho Lee, Ziqi Yu
  • Patent number: 11587968
    Abstract: The present technology relates to a solid-state imaging device capable of suppressing deterioration in dark characteristics, and an electronic apparatus. The device includes a photoelectric conversion section; a trench between the photoelectric conversion sections in adjacent pixels; and a PN junction region on a sidewall of the trench and including a P-type region and an N-type region, the P-type region having a protruding region. The device can include an inorganic photoelectric conversion section having a pn junction and an organic photoelectric conversion section having an organic photoelectric conversion film that are stacked in a depth direction within a same pixel; and a PN junction region on a sidewall of the inorganic photoelectric conversion section. The PN junction region can further include a first P-type region and an N-type region; and a second P-type region. The present technology can be applied to, for example, a back-illuminated CMOS image sensor.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: February 21, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Masashi Ohura, Shin Iwabuchi, Atsushi Okuyama
  • Patent number: 11551904
    Abstract: A system and method that allows higher energy implants to be performed, wherein the peak concentration depth is shallower than would otherwise occur is disclosed. The system comprises an ion source, an accelerator, a platen and a platen orientation motor that allows large tilt angles. The system may be capable of performing implants of hydrogen ions at an implant energy of up to 5 MeV. By tilting the workpiece during an implant, the system can be used to perform implants that are typically performed at implant energies that are less than the minimum implant energy allowed by the system. Additionally, the resistivity profile of the workpiece after thermal treatment is similar to that achieved using a lower energy implant. In certain embodiments, the peak concentration depth may be reduced by 3 ?m or more using larger tilt angles.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: January 10, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Venkataramana R. Chavva, KyuHa Shim, Hans Gossmann, Edwin Arevalo, Scott Falk, Rajesh Prasad
  • Patent number: 11538840
    Abstract: A semiconductor device includes a conductive substrate and an encapsulation structure. The conductive substrate has a plurality of pixels. The encapsulation structure is disposed on the conductive substrate and includes at least one light-collimating unit. The light-collimating unit includes a transparent substrate and a patterned light-shielding layer. The patterned light-shielding layer is disposed on the transparent substrate. The patterned light-shielding layer has a plurality of holes disposed to correspond to the pixels.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: December 27, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Wu-Hsi Lu, Chung-Ren Lao, Chih-Cherng Liao, Shih-Hao Liu, Ming-Cheng Lo, Wei-Lun Chung
  • Patent number: 11538709
    Abstract: A transfer printing method is described that can be used for a wide variety of materials, such as to allow for circuits formed of different materials to be integrated together on a single integrated circuit. A tether (18) is formed on dice regions (16) of a first wafer (30), followed by attachment of a second wafer (32) to the tethers. The dice regions (16) are processed so as to be separated, followed by transfer printing of the dice regions to a third wafer (34).
    Type: Grant
    Filed: February 17, 2018
    Date of Patent: December 27, 2022
    Assignee: Analog Devices International Unlimited Company
    Inventors: James G. Fiorenza, Susan L. Feindt, Michael D. Delaus, Matthew Duffy, Ryan Iutzi, Kenneth Flanders, Rama Krishna Kotlanka
  • Patent number: 11461529
    Abstract: Routing a circuit path includes selecting pixels on the circuit path based at least on penalty values associated with the pixels. Pixels on a rejected circuit path are penalized by increasing their penalty values. Re-routing a rejected circuit path allows for pixels on previously rejected paths to be considered when rerouting the rejected circuit path, rather than being eliminated outright.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: October 4, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Matus Lipka, Kenneth Reneris
  • Patent number: 11424346
    Abstract: The present application discloses a semiconductor device with a programmable feature such as anti-fuse and a method for fabricating the semiconductor device. The semiconductor device includes a first insulating layer including a peak portion and an upper portion positioned on the peak portion, and first conductive blocks positioned on two sides of the peak portion. A width of the peak portion is gradually decreased toward a direction opposite to the upper portion, and the first conductive blocks are spaced apart by the peak portion.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: August 23, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chin-Ling Huang
  • Patent number: 11367616
    Abstract: A method of patterning a material layer includes the following steps. A first material layer is formed over a substrate, and the first material layer includes a first metal compound. Through a first photomask, portions of the first material layer is exposed with a gamma ray, wherein a first metal ion of the first metal compound in the portions of the first material layer is chemically reduced to a first metal grain. Other portions of the first material layer are removed to form a plurality of first hard mask patterns including the first metal grain.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: June 21, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: You-Hua Chou, Kuo-Sheng Chuang
  • Patent number: 11211423
    Abstract: A method of producing a semiconductor epitaxial wafer is provided. The method includes irradiating a surface of a semiconductor wafer with cluster ions to form a modified layer in a surface portion of the semiconductor wafer, in which the modified layer includes a constituent element of the cluster ions in solid solution. The method further includes forming an epitaxial layer on the modified layer of the semiconductor wafer. The irradiating is performed such that a portion of the modified layer in a thickness direction becomes an amorphous layer, and an average depth of an amorphous layer surface from a semiconductor wafer surface-side of the amorphous layer is at least 20 nm from the surface of the semiconductor wafer.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: December 28, 2021
    Assignee: SUMCO CORPORATION
    Inventor: Ryosuke Okuyama
  • Patent number: 11183612
    Abstract: The invention relates to a method for producing at least one optoelectronic component (100) comprising the steps A) providing an auxiliary carrier (1), B) epitaxially applying a sacrificial layer (2) on the auxiliary carrier (1), wherein the sacrificial layer (2) comprises germanium, C) epitaxially applying a semiconductor layer sequence (3) on the sacrificial layer (2), D) removing the sacrificial layer (2) by means of dry etching (9), such that the auxiliary carrier (1) is removed from the semiconductor layer sequence (3).
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: November 23, 2021
    Assignee: OSRAM OLED GMBH
    Inventors: Petrus Sundgren, Christoph Klemp
  • Patent number: 11164854
    Abstract: A pair of smart glasses including a headset, a frame, and an optical photoelectric conversion unit that can gather and utilize solar energy to supplement the electrical energy of a built-in battery. The smart glasses also include a display module comprising a plurality of display units arranged in a matrix. Each display unit comprises at least one micro LED unit and at least one first optical photoelectric conversion unit. A number of the micro LED units functions as a display, and also being controllable as an infrared light source for retinal scanning of the user.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: November 2, 2021
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Chi-An Chen, Ming-Ta Hsieh
  • Patent number: 11056517
    Abstract: Methods and devices that monolithically integrate thin film elements/devices, e.g., environmental sensors, batteries and biosensors, with high performance integrated circuits, i.e., integrated circuits formed in a high quality device layer. Preferred embodiments further monolithically integrate a solar cell array. Preferred embodiments provide pin-size and integrated solar powered wearable electronic, ionic, molecular, radiation, etc. sensors and circuits.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: July 6, 2021
    Assignee: The Regents of the University of California
    Inventors: Shadi A. Dayeh, Yun Goo Ro, Namseok Park, Atsunori Tanaka, Siarhei Vishniakou, Ahmed Youssef, James Buckwalter, Cooper Levy
  • Patent number: 10854493
    Abstract: A method for manufacturing a handling device includes depositing a single layer of an adhesive on a first surface of a first wafer; depositing an antiadhesive layer on a first surface of a second wafer different from the first wafer; bringing into contact the first wafer and the second wafer, the bringing into contact taking place at the level of the single adhesive layer of the first wafer and the antiadhesive layer of the second wafer; separating the first wafer and the second wafer; the first wafer including the single adhesive layer forming a handling device. The bringing into contact of the first wafer and the second wafer is carried out at a temperature TC such that TC>Tg+100° C. where Tg is the glass transition temperature of the material composing the single adhesive layer of the first wafer.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: December 1, 2020
    Assignee: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
    Inventors: Pierre Montmeat, Frank Fournel
  • Patent number: RE48755
    Abstract: An image sensor is provided. The image sensor includes a substrate, a first interlayer insulating layer, a first metal line, and a shielding structure. The substrate includes a pixel array, a peripheral circuit area, and an interface area disposed between the pixel array and the peripheral circuit area. The first interlayer insulating layer is formed on a first surface of the substrate. The first metal line is disposed on the first interlayer insulating layer of the pixel array. The second interlayer insulating layer is disposed on the first interlayer insulating layer wherein the second interlayer insulating layer covers the first metal line. The shielding structure passes through the substrate in the interface area wherein the shielding structure electrically insulates the pixel array of the substrate and the peripheral circuit area.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: September 28, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yun-Ki Lee, Chang-Rok Moon, Min-Wook Jung