Abstract: The present application relates to a silicon precursor compound, a method for preparing the silicon precursor compound, a precursor composition for depositing a silicon-containing oxide thin film or nitride thin film, the precursor composition comprising the silicon precursor compound, and a method for depositing a silicon-containing oxide thin film or nitride thin film using the precursor composition.

Abstract: Process flows and methods are provided for recessing a fill material within openings formed within a patterned substrate. The openings are formed within a multilayer stack comprising a target material layer and one or more additional material layers, which overly and differ from the target material layer. After the openings are formed within the multilayer stack, a grafting material comprising a solubility-shifting agent is selectively deposited within the openings, such that the grafting material adheres to the target material layer without adhering to the additional material layer(s) overlying the target material layer. Next, a fill material is deposited within the openings and the solubility-shifting agent is activated to change the solubility of a portion of the fill material adjacent to and surrounding the grafting material. Then, a wet development process is used to remove the soluble/insoluble portions of fill material to the recess the fill material within the openings.

Abstract: A method of fabricating a dielectric film includes depositing a first precursor on a substrate. The first precursor includes a cyclic carbosiloxane group comprising a six-membered ring. The method also includes depositing a second precursor on the substrate. The first precursor and the second precursor form a preliminary film on the substrate, and the second precursor includes silicon, carbon, and hydrogen. The method further includes exposing the preliminary film to energy from an energy source to form a porous dielectric film.

Abstract: A method includes forming a bottom layer over a semiconductor substrate, where the bottom layer includes a polymer bonded to a first cross-linker and a second cross-linker, the first cross-linker being configured to be activated by ultraviolet (UV) radiation and the second cross-linker being configured to be activated by heat at a first temperature. The method then proceeds to exposing the bottom layer to a UV source to activate the first cross-linker, resulting in an exposed bottom layer, where the exposing activates the first cross-linker. The method further includes baking the exposed bottom layer, where the baking activates the second cross-linker.

Abstract: Zeolites are industrially important materials possessing high Bronsted acidity and shape-selectivity. However, their inherently small pores restrict application for catalytic conversion of bulky molecules. A method of synthesis of ‘artificial’ zeolites. The artificial zeolites have well-tailored Bronsted and Lewis acid sites prepared on mesostructured silica to circumvent this limitation. This novel approach utilizes atomic layer deposition to tailor both porosity and acid speciation, providing exquisite control over catalytic behavior and enabling systematic studies.

Abstract: Methods of selectively depositing films on substrates are described. A passivation film is deposited on a metal surface before deposition of a dielectric material. Also described is exposing a substrate surface comprising a metal surface and a dielectric surface to a docking precursor to form a passivation film.

Abstract: A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.

Abstract: Provided is a method for forming an organic planarization layer. The method includes forming lithographically-patterned arrays atop a substrate; disposing a thiol-based photocurable resin on to the lithographically-patterned arrays to form a photocurable planarization layer; and curing the photocurable planarization layer to form a flat surface above the lithographically-patterned array.

Abstract: Examples of the present technology include semiconductor processing methods that provide a substrate in a substrate processing region of a substrate processing chamber, where the substrate is maintained at a temperature less than or about 50° C. An inert precursor and a hydrocarbon-containing precursor may be flowed into the substrate processing region of the substrate processing chamber, where a flow rate ratio of the inert precursor to the hydrocarbon-containing precursor may be greater than or about 10:1. A plasma may be generated from the inert precursor and the hydrocarbon-containing precursor, and a carbon-containing material may be deposited from the plasma on the substrate. The carbon-containing material may include diamond-like-carbon, and may have greater than or about 60% of the carbon atoms with sp3 hybridized bonds.

Abstract: A method for forming airgaps within an integrated electronic circuit implements a conformal layer and a nanosheet both of boron nitride. The method has advantages for the circuit due to special properties of boron nitride material. In particular, mechanical strength and heat dissipation are increased whereas electro-migration is limited. The method may be applied to the first interconnect layer of the integrated circuit, for reducing additionally capacitive interactions existing between gate electrode structures and source or drain contact structures.

Abstract: Described herein are functionalized cyclosilazane precursor compounds and compositions and methods comprising same to deposit a silicon-containing film such as, without limitation, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, or carbon-doped silicon oxide via a thermal atomic layer deposition (ALD) or plasma enhanced atomic layer deposition (PEALD) process, or a combination thereof.

Abstract: A substrate processing apparatus according to an embodiment includes a transport block and a plurality of processing blocks. In the transport block, a transport device for transporting a substrate is disposed. The plurality of processing blocks are disposed adjacent to the transport block and process the substrate transported by the transport device. Each processing block includes one liquid processing unit and one drying unit. The liquid processing unit performs a liquid film forming processing so as to form a liquid film on the top surface of the substrate. The drying unit performs a supercritical drying processing in which the substrate is dried by bringing the substrate into contact with the processing fluid in a supercritical state. The liquid processing unit and the drying unit included in the same processing block are disposed on the same side with respect to the movement direction of the transport device of the transport block.

Abstract: An interconnect structure includes a metal interconnect layer, a dielectric layer on the metal interconnect layer, a fluorocarbon layer on the dielectric layer, a metal interconnect extending through the fluorocarbon layer and the dielectric layer to the metal interconnect layer. The metal interconnect includes a first portion extending through the fluorocarbon layer and into an upper portion of the dielectric layer and a second portion below the first portion and extending through a lower portion of the dielectric layer to the metal interconnect layer.

Abstract: A method of manufacturing a semiconductor device comprising: providing a semiconductor device substrate having a relief image on a surface of the substrate, the relief image having a plurality of gaps to be filled; applying a coating composition to the relief image to provide a coating layer, wherein the coating composition comprises (i) a polyarylene oligomer comprising as polymerized units one or more first monomers having two or more cyclopentadienone moieties and one or more second monomers having an aromatic moiety and two or more alkynyl moieties; wherein the polyarylene oligomer has a Mw of 1000 to 6000 Da, a PDI of 1 to 2, and a molar ratio of total first monomers to total second monomers of 1:>1; and (ii) one or more organic solvents; curing the coating layer to form a polyarylene film; patterning the polyarylene film; and transferring the pattern to the semiconductor device substrate.

Abstract: A semiconductor die is provided. The semiconductor die includes a semiconductor substrate, an interconnection structure, conductive pads, a first passivation layer, and a second passivation layer. The interconnection structure is disposed on the semiconductor substrate. The conductive pads are disposed over and electrically connected to the interconnection structure. The first passivation layer and the second passivation layer are sequentially stacked on the conductive pads. The first passivation layer and the second passivation layer fill a gap between two adjacent conductive pads. The first passivation layer includes a first section and a second section. The first section extends substantially parallel to a top surface of the interconnection structure. The second section faces a side surface of one of the conductive pads. Thicknesses of the first section and the second section are different.

Abstract: A method for depositing a silicon-containing film, the method comprising: placing a substrate comprising at least one surface feature into a flowable CVD reactor which is at a temperature of from about ?20° C. to about 100° C.; increasing pressure in the reactor to at least 10 torr; and introducing into the reactor at least one silicon-containing compound having at least one acetoxy group to at least partially react the at least one silicon-containing compound to form a flowable liquid oligomer wherein the flowable liquid oligomer forms a silicon oxide coating on the substrate and at least partially fills at least a portion of the at least one surface feature. Once cured, the silicon oxide coating has a low k and excellent mechanical properties.

Abstract: A pixel defining layer is disclosed including a display area and a non-display area located at a periphery of the display area, wherein the display area includes pixel units, and the non-display area includes dummy pixel units arranged outside one or more corners of the display area. A display panel, a display device, a method of fabricating a pixel defining layer, and a method of fabricating the display panel are also disclosed.

Abstract: A gate oxide forming process includes the following steps. A substrate including a first area and a second area is provided. A first oxide layer, a silicon containing cap layer and a second oxide layer on the substrate of the first area and the second area are sequentially and blanketly formed. The silicon containing cap layer and the second oxide layer in the first area are removed. An oxidation process is performed to oxidize the silicon containing cap layer and a gate oxide layer is formed in the second area.

Abstract: A substrate processing apparatus for processing a substrate to manufacture a semiconductor device, includes: a mounting table on which a substrate is mounted; a first liquid supply part that supplies a first liquid to form a polymer film having a urea bond on the substrate mounted on the mounting table; a second liquid supply part that supplies a second liquid reacting with the first liquid; and a nozzle part provided at an end portion of a liquid flow path where the first liquid supplied from the first liquid supply part and the second liquid supplied from the second liquid supply part are joined with each other to obtain a mixed solution, and configured to supply the mixed solution to the substrate to form the polymer film on a surface of the substrate, wherein the polymer film is temporarily used for manufacturing the semiconductor device and is subsequently removed by depolymerization.

Abstract: A first material layer, a second material layer, and a photoresist layer may be formed over a substrate. The second material layer may be patterned by transfer of a lithographic pattern therethrough. A conformal spacer layer may be formed over the patterned second material layer in a chamber enclosure of an in-situ deposition-etch apparatus. Spacer films may be formed by anisotropically etching the conformal spacer layer in the chamber enclosure of the in-situ deposition-etch apparatus. The first material layer may be anisotropically etched using a combination of the patterned second material layer and the spacer films as an etch mask in the in-situ deposition-etch apparatus. A high fidelity pattern may be transferred into the first material layer with reduced line edge roughness, reduced line width roughness, and without enlargement of lateral dimensions of openings in the first material layer.

Abstract: Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.

Abstract: A method includes performing an implantation on a portion of a first layer to form an implanted region, and removing un-implanted portions of the first layer. The implanted region remains after the un-implanted portions of the first layer are removed. An etching is then performed on a second layer underlying the first layer, wherein the implanted region is used as a portion of a first etching mask in the etching. The implanted region is removed. A metal mask is etched using the second layer to form a patterned mask. An inter-layer dielectric is then etched to form a contact opening, wherein the patterned mask is used as a second etching mask.

Abstract: A semiconductor structure includes an Nth metal layer, a diffusion barrier layer over the Nth metal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1)th metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion barrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.

Abstract: A method for depositing a silicon-containing film, the method comprising: placing a substrate comprising at least one surface feature into a flowable CVD reactor which is at a temperature of from about ?20° C. to about 400° C.; introducing into the reactor at least one silicon-containing compound having at least one acetoxy group to at least partially react the at least one silicon-containing compound to form a flowable liquid oligomer wherein the flowable liquid oligomer forms a silicon oxide coating on the substrate and at least partially fills at least a portion of the at least one surface feature. Once cured, the silicon oxide coating has a low k and excellent mechanical properties.

Abstract: Methods are provided for selectively depositing a material on a first surface of a substrate relative to a second, different surface of the substrate. The selectively deposited material can be, for example, a metal, metal oxide, or dielectric material.

Abstract: A component in a CMP tool disclosed herein having a surface and a hydrophobic layer deposited on the surface. In one example, the component is a component for delivering a fluid in a CMP tool. The component for delivering a fluid in a CMP tool includes an elongated member having a first end and a second end, and an elongated upper surface extending between the two ends. A hydrophobic layer is deposited on the elongated upper surface. In another example, the component is a ring shaped body having an upper side and a lower side. A hydrophobic layer is deposited on the inner surfaces of both the upper and lower sides. In another example, the component is a disk shaped body having a top surface, bottom surface, and ledge defined by the top and bottom surfaces. A hydrophobic layer is deposited on the surfaces and the ledge.

Abstract: A method for manufacturing a flexible substrate, a flexible substrate manufactured using the method and a display device including the flexible substrate are disclosed. The method includes steps of: coating a glass carrier with a plurality of film layers, wherein each of at least one pair of adjacent film layers of the plurality of film layers is formed through steps of: S1: coating the glass carrier with a first film layer; and S2: coating the glass carrier with a second film layer over the first film layer so that the second film layer covers the first film layer, wherein the second film layer has an area greater than an area of the first film layer; and peeling off the plurality of formed film layers from the glass carrier to form a flexible substrate.

Abstract: A method includes forming a first insulating layer over a substrate, the first insulating layer having a non-planar top surface, the first insulating layer having a first etch rate. A second insulating layer is formed over the first insulating layer, the second insulating layer having a non-planar top surface, the second insulating layer having a second etch rate, the second etch rate being greater than the first etch rate. The second insulating layer is polished, the polishing partially removing the second insulating layer. The first insulating layer and the second insulating layer are non-selectively recessed.

Abstract: Embodiments of the present invention provides methods to etching a mask layer, e.g., an absorber layer, disposed in a film stack for manufacturing a photomask in EUV applications and phase shift and binary photomask applications. In one embodiment, a method of etching an absorber layer disposed on a photomask includes transferring a film stack into an etching chamber, the film stack having a chromium containing layer partially exposed through a patterned photoresist layer, providing an etching gas mixture including Cl2, O2 and at least one hydrocarbon gas in to a processing chamber, wherein the Cl2 and O2 is supplied at a Cl2:O2 ratio greater than about 9, supplying a RF source power to form a plasma from the etching gas mixture, and etching the chromium containing layer through the patterned photoresist layer in the presence of the plasma.

Abstract: A method for planarizing a polysilicon layer of a low-temperature polysilicon device is provided. The method includes: Step S1: Crystallizing the low-temperature polysilicon device. Step S2: Forming a flat coating layer on an uneven surface of the polysilicon layer of the crystallized low-temperature polysilicon device through a coating process. Step S3: Curing the flat coating layer. Step S4: Removing the cured flat coating layer and the polysilicon protrusion through a removing process to form a flat surface of the polysilicon layer. By the foregoing method, the surface of the rough and uneven polysilicon layer can be well-planarized. As a result, the problems of a broken film, unclean etching, or tip discharge, which would be induced by a rough polysilicon layer, are mitigated. Therefore, the production yield of the low-temperature polysilicon device is improved.

Abstract: Disclosed is a method for purifying an organic compound, comprising the steps of (i) providing a crystalline sample of organic compound having a first impurity level, (ii) adding a catalyst to the sample, (iii) heating a portion of the sample to a temperature at or above melting point of the organic compound so as to create a molten zone of the sample, (iv) moving application of heat down the length of the sample, such that the molten zone is moved along the length of the sample, (v) collecting molten material at an end of the sample, (vi) optionally grinding the sample back to a powder, (vii) repeating steps (i)-(iv) at least two more times, and (viii) obtaining a purified sample having a second impurity level, which is lower than the first impurity level, wherein the organic compound is a nutraceutical selected from the group consisting of vinpocetine, huperzine, astragalosides, HEPPS buffer, curcumin, piperine, uridine, capsaicin and kinetin.

Abstract: A method for depositing a barrier layer includes a) arranging a substrate including a nitride layer in a processing chamber; b) setting a process temperature in the processing chamber to a predetermined process temperature range; c) setting a process pressure in the processing chamber to a predetermined process pressure range; d) supplying at least one of a gas and a vapor including an organosilane precursor species; and e) depositing a barrier layer on the nitride layer. The barrier layer reduces diffusion of nitrogen-containing groups in the nitride layer into a photoresist layer that is subsequently deposited on the nitride layer.

Abstract: A method for forming patterns is provided. The method includes forming a resist layer on a substrate, imprinting a convex pattern and a concave pattern on the resist layer using a template, forming a silicon diffusion layer containing silicon containing diffusion species in an upper portion of the convex pattern, and selectively removing a recessed portion of the resist layer under the concave pattern using the silicon diffusion layer as an etch mask.

Abstract: Methods of discouraging poreseal deposition on metal (e.g. copper) at the bottom of a via during a poresealing process are described. A self-assembled monolayer (SAM) is selectively formed on the exposed metal surface and prevents or discourages formation of poreseal on the metal. The SAM is selectively formed by exposing a patterned substrate to a SAM molecule which preferentially binds to exposed metal surfaces rather than exposed dielectric surfaces. The selected SAM molecules tend to not bind to low-k films. The SAM and SAM molecule are also chosen so the SAM tolerates subsequent processing at relatively high processing temperatures above 140° C. or 160° C. Aliphatic or aromatic SAM molecules with thiol head moieties may be used to form the SAM.

Abstract: Arrangement information regarding shot areas is obtained in an imprinting method. When a pattern is sequentially formed in the shot areas, the attraction force of a first attraction area is reduced to less than that of the second attraction area. After the pattern is formed in the shot area corresponding to the first attraction area, the attraction forces of the first and second attraction areas are changed. The position information regarding the shot area corresponding to the second attraction area is obtained, which is compared with the position information regarding the shot area corresponding to the second attraction area based on the arrangement information. If the difference between the compared position information is a threshold value or less, positioning of a substrate and a mold is achieved using the arrangement information. If the difference is greater than the threshold value, the arrangement information regarding the shot areas is obtained again.

Abstract: Here we disclose a lithographic pattern development process for amorphous fluoropolymers. Amorphous fluoropolymers are a class of plastic materials with high chemical inertness and favorable optical properties. Exposure of surface-deposited layers of such polymer with high energy radiation leads to a change in the chemical structure of the polymer, which selectively compromises the solubility of the exposed areas in fluorinated organic solvents. Micro- and nanopatterning with a feature size down to <50 nm was achieved by dissolving and removing unexposed amorphous fluoropolymer from exposed, surface deposited films. The amorphous fluoropolymer functions thus as a negative resist.

Abstract: In accordance with an embodiment a bottom anti-reflective layer comprises a surface energy modification group which modifies the surface energy of the polymer resin to more closely match a surface energy of an underlying material in order to help fill gaps between structures. The surface energy of the polymer resin may be modified by either using a surface energy modifying group or else by using an inorganic structure.

Abstract: Methods are devices are provided in which interconnection structures are formed using metal reflow techniques. For example, a method to fabricate a semiconductor device includes forming an opening in an ILD (inter-level dielectric) layer. The opening includes a via hole and a trench. A layer of diffusion barrier material is deposited to cover the ILD layer and to line the opening with the diffusion barrier material. A layer of first metallic material is deposited on the layer of diffusion barrier material to cover the ILD layer and to line the opening with the first metallic material. A reflow process is performed to allow the layer of first metallic material to reflow into the opening and at least partially fill the via hole with the first metallic material. A layer of second metallic material is deposited to at least partially fill a remaining portion of the opening in the ILD layer.

Abstract: A semiconductor structure includes an Nth metal layer, a diffusion barrier layer over the Nth metal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1)th metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion barrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.

Abstract: Disclosed is a substrate processing apparatus. The substrate processing apparatus includes a moving mechanism that moves a wafer in a horizontal direction, coating sections that eject the coating liquid to the wafer, and dry sections that dries the coating liquid, and a controller that controls the drying sections, the coating sections, and the moving mechanism. In each coating section, the wafer is moved in the horizontal direction while causing the coating liquid to be in contact with the wafer so that the coating liquid is coated on the entire surface.

Abstract: A sol composition for producing a porous low-k dielectric material is provided. The composition can include at least one silicate ester, a polar solvent, water, an acid catalyst for silicate ester hydrolysis, an amphiphilic block copolymer surfactant, and a nonmetallic catalyst that reduces dielectric constant in the produced material. The composition can further include a metallic ion at a lower parts-per-million concentration than the nonmetallic catalyst, and/or the composition can further include a cosolvent. A method of preparing a thin film on a substrate using the sol composition is also provided.

Abstract: An apparatus for thermal treatment of dielectric films on substrates comprises: a microwave applicator cavity and microwave power source; a workpiece to be heated in the cavity, comprising a porous coating on a selected substrate; and, a means of introducing a controlled amount of a polar solvent into said porous coating immediately before heating by said microwave power. The interaction of the polar solvent with the microwaves enhances the efficiency of the process, to shorten process time and reduce thermal budget. A related method comprises the steps of: depositing a porous film on a substrate; soft baking the film to a selected state of dryness; introducing a controlled amount of a polar solvent into the soft baked film; and, applying microwave energy to heat the film via interaction with the polar solvent.

Abstract: The method may include forming a plurality of fins on a substrate with first and second regions, forming a photoresist pattern to expose the fins of the first region, forming a material layer to cover the fins of first region and the photoresist pattern, chemically reacting the photoresist pattern the material layer to form a supplemental film on a side surface of the photoresist pattern, performing an ion implantation process using the photoresist pattern and the supplemental film as a ion injection mask to form impurity layers in the fins of the first region.

Abstract: A process for forming an array of irregularities or features that are submicron-size in height and that have a characteristic lateral dimension that is micron- or submicron-size, over a surface of a material by reactive-ion etching, the process including: supplying the material with a thickness at least equal to 100 nm, the material being a solid hybrid material that includes: a simple silicon oxide or a mixed silicon oxide, most of the oxides in the case of a mixed oxide being silicon oxide, an oxide molar percentage in the material being at least 40%; and a species, of a different nature to the silicon of the oxide, a molar percentage of the species in the material ranging from 1 mol % or even up to 50 mol % while remaining below the percentage of the silicon oxide, at least most of the species having a largest characteristic dimension smaller than 50 nm, optionally heating the hybrid material before the etching; structuring the surface of the hybrid material, without masking, with etching that lasts less t

Abstract: A method for manufacturing a micromechanical component includes the following sequential steps: a first material layer including a first joining partner being applied to a first wafer; a second material layer including a second joining partner being applied to a second wafer; a micromechanical structure being created in the first wafer by gas phase etching with the aid of a gaseous etching medium which is applied to the first joining partner; the first and second wafers being joined in such a way that they are in contact at least in some areas; and the first and second joining partners being heated to be integrally joined to form a connecting layer, a eutectic joining material being formed in the connecting layer from the first joining partner and the second joining partner.

Abstract: One or more techniques or systems for forming a pattern during semiconductor fabrication are provided herein. In some embodiments, a photo resist (PR) region is patterned and a spacer region is formed above or surrounding at least a portion of the patterned PR region. Additionally, at least some of the spacer region and the patterned PR region are removed to form one or more spacers. Additionally, a block co-polymer (BCP) is filled between the spacers. In some embodiments, the BCP comprises a first polymer and a second polymer. In some embodiments, the second polymer is removed, thus forming a pattern comprising the first polymer and the spacers. In this manner, a method for forming a pattern during semiconductor fabrication is provided, such that a width of the spacer or the first polymer is controlled.

Abstract: Techniques are disclosed for sub-second annealing a lithographic feature to, for example, tailor or otherwise selectively alter its profile in one, two, or three dimensions. Alternatively, or in addition to, the techniques can be used, for example, to smooth or otherwise reduce photoresist line width/edge roughness and/or to reduce defect density. In some cases, the sub-second annealing process has a time-temperature profile that can effectively change the magnitude of resist shrinkage in one or more dimensions or otherwise modify the resist in a desired way (e.g., smooth the resist). The techniques may be implemented, for example, with any type of photoresist (e.g., organic, inorganic, hybrid, molecular photoresist materials) and can be used in forming, for instance, processor microarchitectures, memory circuitry, logic arrays, and numerous other digital/analog/hybrid integrated semiconductor devices.

Abstract: The present invention relates to a method for producing encapsulated nanoparticles by dispersing said nanoparticles and an encapsulating medium in a common solvent to form a first solution system and treating said first solution system with a stimulus suitable to induce simultaneous aggregation of the nanoparticles and the encapsulating medium.

Abstract: Curable silicone mixture containing an alkenyl-functional silicone, an Si—H functional silicone, an epoxy-functional silicone, a ferrocene, and a hydrosilylation curing catalyst, provide thermally stable silicones which are also adherent. The compositions are particularly useful for embedding power semiconductor devices.

Abstract: A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances oxidation and copper diffusion barrier properties. The dielectric stack has inorganic or hybrid inorganic-organic random three-dimensional covalent bonding throughout the network, which contain different regions of different chemical compositions such as a cap component adjacent to a low-k component of the same type of material but with higher porosity.