Depositing Organic Material (e.g., Polymer, Etc.) Patents (Class 438/780)
  • Patent number: 10468587
    Abstract: A semiconductor structure includes an Nth metal layer, a diffusion barrier layer over the Nth metal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1)th metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion barrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: November 5, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chung-Yen Chou, Fu-Ting Sung, Yao-Wen Chang, Shih-Chang Liu
  • Patent number: 10468244
    Abstract: A method for depositing a silicon-containing film, the method comprising: placing a substrate comprising at least one surface feature into a flowable CVD reactor which is at a temperature of from about ?20° C. to about 400° C.; introducing into the reactor at least one silicon-containing compound having at least one acetoxy group to at least partially react the at least one silicon-containing compound to form a flowable liquid oligomer wherein the flowable liquid oligomer forms a silicon oxide coating on the substrate and at least partially fills at least a portion of the at least one surface feature. Once cured, the silicon oxide coating has a low k and excellent mechanical properties.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: November 5, 2019
    Assignee: VERSUM MATERIALS US, LLC
    Inventors: Jianheng Li, Raymond Nicholas Vrtis, Robert Gordon Ridgeway, Manchao Xiao, Xinjian Lei
  • Patent number: 10456808
    Abstract: Methods are provided for selectively depositing a material on a first surface of a substrate relative to a second, different surface of the substrate. The selectively deposited material can be, for example, a metal, metal oxide, or dielectric material.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: October 29, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Suvi P. Haukka, Raija H. Matero, Eva Tois, Antti Niskanen, Marko Tuominen, Hannu Huotari, Viljami J. Pore, Ivo Raaijmakers
  • Patent number: 10434627
    Abstract: A component in a CMP tool disclosed herein having a surface and a hydrophobic layer deposited on the surface. In one example, the component is a component for delivering a fluid in a CMP tool. The component for delivering a fluid in a CMP tool includes an elongated member having a first end and a second end, and an elongated upper surface extending between the two ends. A hydrophobic layer is deposited on the elongated upper surface. In another example, the component is a ring shaped body having an upper side and a lower side. A hydrophobic layer is deposited on the inner surfaces of both the upper and lower sides. In another example, the component is a disk shaped body having a top surface, bottom surface, and ledge defined by the top and bottom surfaces. A hydrophobic layer is deposited on the surfaces and the ledge.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: October 8, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Sreenidhi Attur
  • Patent number: 10319924
    Abstract: A method for manufacturing a flexible substrate, a flexible substrate manufactured using the method and a display device including the flexible substrate are disclosed. The method includes steps of: coating a glass carrier with a plurality of film layers, wherein each of at least one pair of adjacent film layers of the plurality of film layers is formed through steps of: S1: coating the glass carrier with a first film layer; and S2: coating the glass carrier with a second film layer over the first film layer so that the second film layer covers the first film layer, wherein the second film layer has an area greater than an area of the first film layer; and peeling off the plurality of formed film layers from the glass carrier to form a flexible substrate.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: June 11, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ming-Che Hsieh, Lu Liu, Chunyan Xie, Hejin Wang
  • Patent number: 10269567
    Abstract: A method includes forming a first insulating layer over a substrate, the first insulating layer having a non-planar top surface, the first insulating layer having a first etch rate. A second insulating layer is formed over the first insulating layer, the second insulating layer having a non-planar top surface, the second insulating layer having a second etch rate, the second etch rate being greater than the first etch rate. The second insulating layer is polished, the polishing partially removing the second insulating layer. The first insulating layer and the second insulating layer are non-selectively recessed.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Teng-Chun Tsai, Yung-Cheng Lu, Ying-Tsung Chen, Tien-I Bao
  • Patent number: 10199224
    Abstract: Embodiments of the present invention provides methods to etching a mask layer, e.g., an absorber layer, disposed in a film stack for manufacturing a photomask in EUV applications and phase shift and binary photomask applications. In one embodiment, a method of etching an absorber layer disposed on a photomask includes transferring a film stack into an etching chamber, the film stack having a chromium containing layer partially exposed through a patterned photoresist layer, providing an etching gas mixture including Cl2, O2 and at least one hydrocarbon gas in to a processing chamber, wherein the Cl2 and O2 is supplied at a Cl2:O2 ratio greater than about 9, supplying a RF source power to form a plasma from the etching gas mixture, and etching the chromium containing layer through the patterned photoresist layer in the presence of the plasma.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: February 5, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Zhigang Mao, Xiaoyi Chen, Amitabh Sabharwal, Ajay Kumar
  • Patent number: 10177007
    Abstract: A method for planarizing a polysilicon layer of a low-temperature polysilicon device is provided. The method includes: Step S1: Crystallizing the low-temperature polysilicon device. Step S2: Forming a flat coating layer on an uneven surface of the polysilicon layer of the crystallized low-temperature polysilicon device through a coating process. Step S3: Curing the flat coating layer. Step S4: Removing the cured flat coating layer and the polysilicon protrusion through a removing process to form a flat surface of the polysilicon layer. By the foregoing method, the surface of the rough and uneven polysilicon layer can be well-planarized. As a result, the problems of a broken film, unclean etching, or tip discharge, which would be induced by a rough polysilicon layer, are mitigated. Therefore, the production yield of the low-temperature polysilicon device is improved.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: January 8, 2019
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Weibin Zhang
  • Patent number: 10138173
    Abstract: Disclosed is a method for purifying an organic compound, comprising the steps of (i) providing a crystalline sample of organic compound having a first impurity level, (ii) adding a catalyst to the sample, (iii) heating a portion of the sample to a temperature at or above melting point of the organic compound so as to create a molten zone of the sample, (iv) moving application of heat down the length of the sample, such that the molten zone is moved along the length of the sample, (v) collecting molten material at an end of the sample, (vi) optionally grinding the sample back to a powder, (vii) repeating steps (i)-(iv) at least two more times, and (viii) obtaining a purified sample having a second impurity level, which is lower than the first impurity level, wherein the organic compound is a nutraceutical selected from the group consisting of vinpocetine, huperzine, astragalosides, HEPPS buffer, curcumin, piperine, uridine, capsaicin and kinetin.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: November 27, 2018
    Assignee: White Flower Associates
    Inventor: Mel Blum
  • Patent number: 10109476
    Abstract: A method for depositing a barrier layer includes a) arranging a substrate including a nitride layer in a processing chamber; b) setting a process temperature in the processing chamber to a predetermined process temperature range; c) setting a process pressure in the processing chamber to a predetermined process pressure range; d) supplying at least one of a gas and a vapor including an organosilane precursor species; and e) depositing a barrier layer on the nitride layer. The barrier layer reduces diffusion of nitrogen-containing groups in the nitride layer into a photoresist layer that is subsequently deposited on the nitride layer.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: October 23, 2018
    Assignee: LAM RESEARCH CORPORATION
    Inventors: David Cheung, Ilia Kalinovski
  • Patent number: 10083837
    Abstract: A method for forming patterns is provided. The method includes forming a resist layer on a substrate, imprinting a convex pattern and a concave pattern on the resist layer using a template, forming a silicon diffusion layer containing silicon containing diffusion species in an upper portion of the convex pattern, and selectively removing a recessed portion of the resist layer under the concave pattern using the silicon diffusion layer as an etch mask.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: September 25, 2018
    Assignee: SK Hynix Inc.
    Inventor: Woo Yung Jung
  • Patent number: 10074559
    Abstract: Methods of discouraging poreseal deposition on metal (e.g. copper) at the bottom of a via during a poresealing process are described. A self-assembled monolayer (SAM) is selectively formed on the exposed metal surface and prevents or discourages formation of poreseal on the metal. The SAM is selectively formed by exposing a patterned substrate to a SAM molecule which preferentially binds to exposed metal surfaces rather than exposed dielectric surfaces. The selected SAM molecules tend to not bind to low-k films. The SAM and SAM molecule are also chosen so the SAM tolerates subsequent processing at relatively high processing temperatures above 140° C. or 160° C. Aliphatic or aromatic SAM molecules with thiol head moieties may be used to form the SAM.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: September 11, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Geetika Bajaj, Tapash Chakraborty, Prerna Sonthalia Goradia, Robert Jan Visser, Bhaskar Kumar, Deenesh Padhi
  • Patent number: 10048581
    Abstract: Arrangement information regarding shot areas is obtained in an imprinting method. When a pattern is sequentially formed in the shot areas, the attraction force of a first attraction area is reduced to less than that of the second attraction area. After the pattern is formed in the shot area corresponding to the first attraction area, the attraction forces of the first and second attraction areas are changed. The position information regarding the shot area corresponding to the second attraction area is obtained, which is compared with the position information regarding the shot area corresponding to the second attraction area based on the arrangement information. If the difference between the compared position information is a threshold value or less, positioning of a substrate and a mold is achieved using the arrangement information. If the difference is greater than the threshold value, the arrangement information regarding the shot areas is obtained again.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: August 14, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Hiroshi Sato
  • Patent number: 9835949
    Abstract: Here we disclose a lithographic pattern development process for amorphous fluoropolymers. Amorphous fluoropolymers are a class of plastic materials with high chemical inertness and favorable optical properties. Exposure of surface-deposited layers of such polymer with high energy radiation leads to a change in the chemical structure of the polymer, which selectively compromises the solubility of the exposed areas in fluorinated organic solvents. Micro- and nanopatterning with a feature size down to <50 nm was achieved by dissolving and removing unexposed amorphous fluoropolymer from exposed, surface deposited films. The amorphous fluoropolymer functions thus as a negative resist.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: December 5, 2017
    Inventors: Aldo Jesorka, Mehrnaz Shaali
  • Patent number: 9761449
    Abstract: In accordance with an embodiment a bottom anti-reflective layer comprises a surface energy modification group which modifies the surface energy of the polymer resin to more closely match a surface energy of an underlying material in order to help fill gaps between structures. The surface energy of the polymer resin may be modified by either using a surface energy modifying group or else by using an inorganic structure.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: September 12, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chung Su, Ching-Yu Chang
  • Patent number: 9735051
    Abstract: Methods are devices are provided in which interconnection structures are formed using metal reflow techniques. For example, a method to fabricate a semiconductor device includes forming an opening in an ILD (inter-level dielectric) layer. The opening includes a via hole and a trench. A layer of diffusion barrier material is deposited to cover the ILD layer and to line the opening with the diffusion barrier material. A layer of first metallic material is deposited on the layer of diffusion barrier material to cover the ILD layer and to line the opening with the first metallic material. A reflow process is performed to allow the layer of first metallic material to reflow into the opening and at least partially fill the via hole with the first metallic material. A layer of second metallic material is deposited to at least partially fill a remaining portion of the opening in the ILD layer.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: August 15, 2017
    Assignee: International Business Machines Corporation
    Inventors: Conal E. Murray, Chih-Chao Yang
  • Patent number: 9711713
    Abstract: A semiconductor structure includes an Nth metal layer, a diffusion barrier layer over the Nth metal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1)th metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion barrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: July 18, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chung-Yen Chou, Fu-Ting Sung, Yao-Wen Chang, Shih-Chang Liu
  • Patent number: 9623435
    Abstract: Disclosed is a substrate processing apparatus. The substrate processing apparatus includes a moving mechanism that moves a wafer in a horizontal direction, coating sections that eject the coating liquid to the wafer, and dry sections that dries the coating liquid, and a controller that controls the drying sections, the coating sections, and the moving mechanism. In each coating section, the wafer is moved in the horizontal direction while causing the coating liquid to be in contact with the wafer so that the coating liquid is coated on the entire surface.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: April 18, 2017
    Assignee: Tokyo Electron Limited
    Inventor: Yukihiro Wakamoto
  • Patent number: 9589789
    Abstract: A sol composition for producing a porous low-k dielectric material is provided. The composition can include at least one silicate ester, a polar solvent, water, an acid catalyst for silicate ester hydrolysis, an amphiphilic block copolymer surfactant, and a nonmetallic catalyst that reduces dielectric constant in the produced material. The composition can further include a metallic ion at a lower parts-per-million concentration than the nonmetallic catalyst, and/or the composition can further include a cosolvent. A method of preparing a thin film on a substrate using the sol composition is also provided.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: March 7, 2017
    Assignee: SBA Materials, Inc.
    Inventors: Mark L. F. Phillips, Travis Savage
  • Patent number: 9538586
    Abstract: An apparatus for thermal treatment of dielectric films on substrates comprises: a microwave applicator cavity and microwave power source; a workpiece to be heated in the cavity, comprising a porous coating on a selected substrate; and, a means of introducing a controlled amount of a polar solvent into said porous coating immediately before heating by said microwave power. The interaction of the polar solvent with the microwaves enhances the efficiency of the process, to shorten process time and reduce thermal budget. A related method comprises the steps of: depositing a porous film on a substrate; soft baking the film to a selected state of dryness; introducing a controlled amount of a polar solvent into the soft baked film; and, applying microwave energy to heat the film via interaction with the polar solvent.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: January 3, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Iftikhar Ahmad
  • Patent number: 9443732
    Abstract: The method may include forming a plurality of fins on a substrate with first and second regions, forming a photoresist pattern to expose the fins of the first region, forming a material layer to cover the fins of first region and the photoresist pattern, chemically reacting the photoresist pattern the material layer to form a supplemental film on a side surface of the photoresist pattern, performing an ion implantation process using the photoresist pattern and the supplemental film as a ion injection mask to form impurity layers in the fins of the first region.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: September 13, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae Sun Kim, Jaekyung Seo, Kwangsub Yoon, Yura Kim, Yeojin Lee
  • Patent number: 9371251
    Abstract: A process for forming an array of irregularities or features that are submicron-size in height and that have a characteristic lateral dimension that is micron- or submicron-size, over a surface of a material by reactive-ion etching, the process including: supplying the material with a thickness at least equal to 100 nm, the material being a solid hybrid material that includes: a simple silicon oxide or a mixed silicon oxide, most of the oxides in the case of a mixed oxide being silicon oxide, an oxide molar percentage in the material being at least 40%; and a species, of a different nature to the silicon of the oxide, a molar percentage of the species in the material ranging from 1 mol % or even up to 50 mol % while remaining below the percentage of the silicon oxide, at least most of the species having a largest characteristic dimension smaller than 50 nm, optionally heating the hybrid material before the etching; structuring the surface of the hybrid material, without masking, with etching that lasts less t
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: June 21, 2016
    Assignee: SAINT-GOBAIN GLASS FRANCE
    Inventors: Elin Sondergard, Sébastien Le Roy, Alban Letailleur, Constance Magne
  • Patent number: 9365417
    Abstract: A method for manufacturing a micromechanical component includes the following sequential steps: a first material layer including a first joining partner being applied to a first wafer; a second material layer including a second joining partner being applied to a second wafer; a micromechanical structure being created in the first wafer by gas phase etching with the aid of a gaseous etching medium which is applied to the first joining partner; the first and second wafers being joined in such a way that they are in contact at least in some areas; and the first and second joining partners being heated to be integrally joined to form a connecting layer, a eutectic joining material being formed in the connecting layer from the first joining partner and the second joining partner.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: June 14, 2016
    Assignee: ROBERT BOSCH GMBH
    Inventors: Thomas Mayer, Heribert Weber, Jens Frey
  • Patent number: 9355865
    Abstract: One or more techniques or systems for forming a pattern during semiconductor fabrication are provided herein. In some embodiments, a photo resist (PR) region is patterned and a spacer region is formed above or surrounding at least a portion of the patterned PR region. Additionally, at least some of the spacer region and the patterned PR region are removed to form one or more spacers. Additionally, a block co-polymer (BCP) is filled between the spacers. In some embodiments, the BCP comprises a first polymer and a second polymer. In some embodiments, the second polymer is removed, thus forming a pattern comprising the first polymer and the spacers. In this manner, a method for forming a pattern during semiconductor fabrication is provided, such that a width of the spacer or the first polymer is controlled.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: May 31, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Cheng-Hsiung Tsai, Chung-Ju Lee, Tsung-Jung Tsai, Yu-Sheng Chang
  • Patent number: 9224602
    Abstract: Techniques are disclosed for sub-second annealing a lithographic feature to, for example, tailor or otherwise selectively alter its profile in one, two, or three dimensions. Alternatively, or in addition to, the techniques can be used, for example, to smooth or otherwise reduce photoresist line width/edge roughness and/or to reduce defect density. In some cases, the sub-second annealing process has a time-temperature profile that can effectively change the magnitude of resist shrinkage in one or more dimensions or otherwise modify the resist in a desired way (e.g., smooth the resist). The techniques may be implemented, for example, with any type of photoresist (e.g., organic, inorganic, hybrid, molecular photoresist materials) and can be used in forming, for instance, processor microarchitectures, memory circuitry, logic arrays, and numerous other digital/analog/hybrid integrated semiconductor devices.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: December 29, 2015
    Assignee: INTEL CORPORATION
    Inventors: Aravind S. Killampalli, Charles H. Wallace, Bernhard Sell
  • Patent number: 9159590
    Abstract: The present invention relates to a method for producing encapsulated nanoparticles by dispersing said nanoparticles and an encapsulating medium in a common solvent to form a first solution system and treating said first solution system with a stimulus suitable to induce simultaneous aggregation of the nanoparticles and the encapsulating medium.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: October 13, 2015
    Assignee: Nanoco Technologies, Ltd.
    Inventors: Imad Naasani, James Gillies, Emma Hogarth, Xiaojuan Wang, Ombretta Masala
  • Patent number: 9150726
    Abstract: Curable silicone mixture containing an alkenyl-functional silicone, an Si—H functional silicone, an epoxy-functional silicone, a ferrocene, and a hydrosilylation curing catalyst, provide thermally stable silicones which are also adherent. The compositions are particularly useful for embedding power semiconductor devices.
    Type: Grant
    Filed: January 2, 2013
    Date of Patent: October 6, 2015
    Assignee: Wacker Chemie AG
    Inventor: Philipp Mueller
  • Patent number: 9105642
    Abstract: A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances oxidation and copper diffusion barrier properties. The dielectric stack has inorganic or hybrid inorganic-organic random three-dimensional covalent bonding throughout the network, which contain different regions of different chemical compositions such as a cap component adjacent to a low-k component of the same type of material but with higher porosity.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: August 11, 2015
    Assignee: International Business Machines Corporation
    Inventors: Griselda Bonilla, Alfred Grill, Thomas J. Haigh, Jr., Satyanarayana V. Nitta, Son Nguyen
  • Patent number: 9034736
    Abstract: The present invention provides a method of patterning an electronic or photonic material on a substrate comprising: forming a film of said electronic or photonic material on said substrate; and using a fluoropolymer to protect regions of said electronic or photonic material during a patterning process.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: May 19, 2015
    Assignee: Cambridge Enterprise Limited
    Inventors: Henning Sirringhaus, Jui-Fen Chang, Michael Gwinner
  • Patent number: 9034740
    Abstract: The deposition rate of a porous insulation film is increased, and the film strength of the porous insulation film is improved. Two or more organic siloxane raw materials each having a cyclic SiO structure as a main skeleton thereof, and having mutually different structures, are vaporized, and transported with a carrier gas to a reactor (chamber), and an oxidant gas including an oxygen atom is added thereto. Thus, a porous insulation film is formed by a plasma CVD (Chemical Vapor Deposition) method or a plasma polymerization method in the reactor (chamber). In the step, the ratio of the flow rate of the added oxidant gas to the flow rate of the carrier gas is more than 0 and 0.08 or less.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: May 19, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hironori Yamamoto, Fuminori Ito, Yoshihiro Hayashi
  • Patent number: 9029270
    Abstract: Provided is a photopolymer composition for a semiconductor element surface protective film or an interlayer insulating film, in which a solution of the photopolymer composition comprises 100 parts by mass of (A) a phenolic resin having a biphenyldiyl structure in a main chain of the resin; 1 to 30 parts by mass of (B) a photo acid-generating agent; and 1 to 60 parts by mass of (C) a compound that can be reacted with ingredient (A) by means of an acid generated from the photo acid-generating agent or heat.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: May 12, 2015
    Assignee: Asahi Kasei E-Materials Corporation
    Inventors: Takahiro Sasaki, Jun Li
  • Patent number: 9029228
    Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate. The layer of graphene may be formed in direct contact with the surface of the substrate, or an intervening layer of a material may be formed between the substrate surface and the graphene layer.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: May 12, 2015
    Assignees: SunEdision Semiconductor Limited (UEN201334164H), Kansas State University Research Foundation
    Inventors: Michael R. Seacrist, Vikas Berry, Phong Tuan Nguyen
  • Patent number: 9028915
    Abstract: A method for forming a photoresist layer on a semiconductor device is disclosed. An exemplary includes providing a wafer. The method further includes spinning the wafer during a first cycle at a first speed, while a pre-wet material is dispensed over the wafer and spinning the wafer during the first cycle at a second speed, while the pre-wet material continues to be dispensed over the wafer. The method further includes spinning the wafer during a second cycle at the first speed, while the pre-wet material continues to be dispensed over the wafer and spinning the wafer during the second cycle at the second speed, while the pre-wet material continues to be dispensed over the wafer. The method further includes spinning the wafer at a third speed, while a photoresist material is dispensed over the wafer including the pre-wet material.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wei Chang, Chih-Chien Wang, Wang-Pen Mo, Hung-Chang Hsieh
  • Patent number: 9029171
    Abstract: The present disclosure relates to a structure and method to create a self-repairing dielectric material for semiconductor device applications. A porous dielectric material is deposited on a substrate, and exposed with treating agent particles such that the treating agent particles diffuse into the dielectric material. A dense non-porous cap is formed above the dielectric material which encapsulates the treating agent particles within the dielectric material. The dielectric material is then subjected to a process which creates damage to the dielectric material. A chemical reaction is initiated between the treating agent particles and the damage, repairing the damage. A gradient concentration resulting from the consumption of treating agent particles by the chemical reaction promotes continuous diffusion the treating agent particles towards the damaged region of the dielectric material, continuously repairing the damage.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Min Huang, Chung-Ju Lee, Tien-I Bao
  • Patent number: 9029271
    Abstract: A method of patterning a block copolymer layer includes: providing a guide pattern on a surface of a substrate, the guide pattern including sidewalls each elongated in a longitudinal direction and spaced apart from each other, a trench defined by a bottom surface and facing surfaces of the sidewalls, and having a uniform width over an entire length thereof in the longitudinal direction, and a latitudinal wall perpendicular to the longitudinal direction of the trench; providing a block copolymer layer on the surface of the substrate; and annealing the block copolymer to cause self-assembly of the block copolymer and to direct the same in the trench. The block copolymer has a microphase-separation into anisotropic discrete domains aligned with a period ?o in the trench by the annealing.
    Type: Grant
    Filed: December 24, 2013
    Date of Patent: May 12, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youn Jung Park, Haeng Deog Koh, Mi-Jeong Kim, Seong-Jun Jeong
  • Publication number: 20150125593
    Abstract: A method of patterning an elastomeric polymer material includes: (a) dissolving a precursor of the elastomeric polymer material in a solvent to give an elastomeric polymer precursor solution; and (b) forming a pattern from the elastomeric polymer precursor solution on a base by using a printer, wherein a temperature of the base is maintained to be about 10° C.-30° C. higher than a boiling point of the solvent.
    Type: Application
    Filed: November 6, 2014
    Publication date: May 7, 2015
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-kyun IM, Jong-jin PARK
  • Publication number: 20150118847
    Abstract: In an imprint method of an embodiment, in the imprinting of an imprint shot including an outermost peripheral region of a substrate where resist is not desired to be entered at the time of imprinting, light curing the resist is applied to a light irradiation region with a predetermined width including a boundary between the outermost peripheral region and a pattern formation region more inside than the outermost peripheral region, whereby the resist which is to enter inside the outermost peripheral region is cured. Then, light curing the resist filled in a template pattern is applied onto a template.
    Type: Application
    Filed: January 9, 2015
    Publication date: April 30, 2015
    Inventor: Shinji Mikami
  • Publication number: 20150115415
    Abstract: Methods, apparatuses and devices relate to inkjet printing a covering layer on at least a first side of a substrate in a peripheral region thereof are discussed.
    Type: Application
    Filed: October 30, 2013
    Publication date: April 30, 2015
    Inventors: Martin Mischitz, Karl Heinz Gasser, John Cooper, Kae-Horng Wang
  • Patent number: 9018107
    Abstract: A deposition for producing a porous organosilica glass film comprising: introducing into a vacuum chamber gaseous reagents including one precursor of an organosilane or an organosiloxane, and a porogen distinct from the precursor, wherein the porogen is aromatic in nature; applying energy to the gaseous reagents in the chamber to induce reaction of the gaseous reagents to deposit a film, containing the porogen; and removing substantially all of the organic material by UV radiation to provide the porous film with pores and a dielectric constant less than 2.6.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: April 28, 2015
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Mary Kathryn Haas, Raymond Nicholas Vrtis, Laura M. Matz
  • Publication number: 20150111393
    Abstract: In the manufacturing method of a semiconductor device according to the present embodiment, a resist is supplied on a base material. A template including a first template region having a device pattern and a second template region being adjacent to the device pattern and having supporting column patterns is pressed against the resist on the base material. The resist is cured, thereby transferring the device pattern to the resist on a first material region of the base material corresponding to the first template region and at the same time transferring the supporting column patterns to the resist on a second material region of the base material corresponding to the second template region to form supporting columns. The supporting columns are contacted with the first template region when the device pattern is transferred to a resist supplied to the second material region.
    Type: Application
    Filed: February 4, 2014
    Publication date: April 23, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Taishi ISHIKURA, Atsunobu ISOBAYASHI, Akihiro KAJITA
  • Patent number: 9006720
    Abstract: Laser pyrolysis reactor designs and corresponding reactant inlet nozzles are described to provide desirable particle quenching that is particularly suitable for the synthesis of elemental silicon particles. In particular, the nozzles can have a design to encourage nucleation and quenching with inert gas based on a significant flow of inert gas surrounding the reactant precursor flow and with a large inert entrainment flow effectively surrounding the reactant precursor and quench gas flows. Improved silicon nanoparticle inks are described that has silicon nanoparticles without any surface modification with organic compounds. The silicon ink properties can be engineered for particular printing applications, such as inkjet printing, gravure printing or screen printing. Appropriate processing methods are described to provide flexibility for ink designs without surface modifying the silicon nanoparticles.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: April 14, 2015
    Assignee: NanoGram Corporation
    Inventors: Shivkumar Chiruvolu, Igor Altman, Bernard M. Frey, Weidong Li, Guojun Liu, Robert B. Lynch, Gina Elizabeth Pengra-Leung, Uma Srinivasan
  • Patent number: 9006051
    Abstract: An object is to improve water resistance and reliability of a semiconductor device by reducing the degree of peeling of a film. In a semiconductor device, a first inorganic insulating layer, a semiconductor element layer, a second inorganic insulating layer, an organic insulating layer, and a third inorganic insulating layer are sequentially stacked over a substrate. The second inorganic insulating layer is in contact with the first inorganic insulating layer in an opening portion provided in the semiconductor element layer. The third inorganic insulating layer is in contact with the second inorganic insulating layer in an opening portion provided in the organic insulating layer. In a region where the second inorganic insulating layer and the third inorganic insulating layer are in contact with each other, the second inorganic insulating layer has a plurality of irregularities or openings.
    Type: Grant
    Filed: April 14, 2009
    Date of Patent: April 14, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiaki Oikawa, Masayuki Kajiwara, Masataka Nakada, Masami Jintyou, Shunpei Yamazaki
  • Patent number: 9006019
    Abstract: A method for manufacturing a light-emitting device includes a step of forming an etching resistant protection layer on a substrate provided with an organic planarizing layer, a step of forming a plurality of electrodes on the etching resistant protection layer, a step of forming an organic compound layer on the substrate provided with the plurality of electrodes, a step of forming a resist layer on the organic compound layer formed on parts of electrodes among the plurality of electrodes using a photolithographic method, and a step of removing the organic compound layer in a region not covered with the resist layer by dry etching, wherein an entire surface of the organic planarizing layer on the substrate on which steps up to the step of forming the plurality of electrodes have been performed is covered with at least one of the etching resistant protection layer and the electrode.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 14, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Manabu Otsuka, Tomoyuki Hiroki
  • Patent number: 8999857
    Abstract: A method for forming a nano-textured surface on a substrate is disclosed. An illustrative embodiment of the present invention comprises dispensing of a nanoparticle ink of nanoparticles and solvent onto the surface of a substrate, distributing the ink to form substantially uniform, liquid nascent layer of the ink, and enabling the solvent to evaporate from the nanoparticle ink thereby inducing the nanoparticles to assemble into an texture layer. Methods in accordance with the present invention enable rapid formation of large-area substrates having a nano-textured surface. Embodiments of the present invention are well suited for texturing substrates using high-speed, large scale, roll-to-roll coating equipment, such as that used in office product, film coating, and flexible packaging applications. Further, embodiments of the present invention are well suited for use with rigid or flexible substrates.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: April 7, 2015
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Sangmoo Jeong, Liangbing Hu, Yi Cui
  • Patent number: 8999862
    Abstract: Methods of fabricating nano-scale structures are provided. A method includes forming a first hard mask pattern corresponding to first openings in a dense region, forming first guide elements on the first hard mask pattern aligned with the first openings, and forming second hard mask patterns in a sparse region to provide isolated patterns. A blocking layer is formed in the sparse region to cover the second hard mask patterns. A first domain and second domains are formed in the dense region using a phase separation of a block co-polymer layer. Related nano-scale structures are also provided.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: April 7, 2015
    Assignee: SK Hynix Inc.
    Inventors: Keun Do Ban, Cheol Kyu Bok, Myoung Soo Kim, Jung Hyung Lee, Hyun Kyung Shim, Chang Il Oh
  • Patent number: 8987019
    Abstract: A method of manufacturing an opto-electric device is disclosed, comprising the steps of providing a substrate (10), overlying a first main side of the substrate with an electrically interconnected open shunting structure (20), embedding the electrically interconnected open shunting structure in a transparent layer (30), removing the substrate from the embedded electrically interconnected open shunting structure, depositing a functional layer structure (40) over a free surface (31) formed after removal of the substrate.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: March 24, 2015
    Assignee: Koninklijke Philips N.V.
    Inventors: Antonius Maria Bernardus van Mol, Joanne Sarah Wilson, Chia-Chen Fan, Herbert Lifka, Edward Willem Albert Young, Hieronymus A.J.M. Andriessen
  • Patent number: 8987024
    Abstract: System for wafer-level phosphor deposition. In an aspect, a semiconductor wafer is provided that includes a plurality of LED dies wherein at least one die includes an electrical contact, a photo-resist post covering the electrical contact, and a phosphor deposition layer covering the semiconductor wafer and surrounding the photo-resist post. In another aspect, a semiconductor wafer is provided that comprises a plurality of LED dies wherein at least one die comprises an electrical contact, a phosphor deposition layer covering the semiconductor wafer, and a cavity in the phosphor deposition layer exposing the at least one electrical contact.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: March 24, 2015
    Assignee: Bridgelux, Inc
    Inventor: Tao Xu
  • Publication number: 20150079805
    Abstract: A semiconductor device and method of making the semiconductor device is described. A semiconductor die is provided. A polymer layer is formed over the semiconductor die. A via is formed in the polymer layer. The polymer layer is crosslinked in a first process. The polymer layer is thermally cured in a second process. The polymer layer can comprise polybenzoxazoles (PBO), polyimide, benzocyclobutene (BCB), or siloxane-based polymers. A surface of the polymer layer can be crosslinked by a UV bake to control a slope of the via during subsequent curing. The second process can further comprise thermally curing the polymer layer using conduction, convection, infrared, or microwave heating. The polymer layer can be thermally cured by increasing a temperature of the polymer at a rate greater than or equal to 10 degrees Celsius per minute, and can be completely cured in less than or equal to 60 minutes.
    Type: Application
    Filed: September 17, 2013
    Publication date: March 19, 2015
    Applicant: DECA TECHNOLOGIES INC.
    Inventors: William Boyd Rogers, Willibrordus Gerardus Maria van den Hoek
  • Patent number: 8980663
    Abstract: An organic light emitting diode (OLED) display device and a method of fabricating the same are disclosed.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: March 17, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Won-Kyu Lee, Kyu-Sik Cho, Tae-Hoon Yang, Byoung-Kwon Choo, Sang-Ho Moon, Bo-Kyung Choi, Yong-Hwan Park, Joon-Hoo Choi, Min-Chul Shin, Yun-Gyu Lee
  • Patent number: 8975164
    Abstract: The present invention provides a method of manufacturing a semiconductor device. The method at least comprises the following steps. First, the semiconductor device, which comprises a gate, a gate dielectric layer, an active layer, a source and a drain, is manufactured. However, the semiconductor device has a plurality of defects, and the active layer is a metal oxide thin film. After annealing the semiconductor device, it will be transferred into a chamber. A final step of injecting a supercritical fluid carried with a co-solvent into the chamber is then performed to modify the abovementioned defects.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: March 10, 2015
    Assignee: National Chiao Tung University
    Inventors: Po-Tsun Liu, Wei-Ya Wang, Li-Feng Teng