Abstract: There is provided a damage recovery method capable of recovering electrical characteristics of a low dielectric insulating film sufficiently while suppressing oxidation of buried metal and generation of pattern defaults. A damaged functional group generated in a surface of the low dielectric insulating film by a processing is substituted with a hydrophobic functional group (ST. 2). A damaged component present under a dense layer generated in the surface of the low dielectric insulating film by the substitution process is recovered by using an ultraviolet heating process (ST. 3).

Abstract: An object is to provide an insulating film for a semiconductor device which has characteristics of a low permittivity, a low leakage current, and a high mechanical strength, undergoes less change in these characteristics with the elapse of time, and has an excellent water resistance, as well as to provide a process and an apparatus for producing the insulating film for a semiconductor device, a semiconductor device, and a process for producing the semiconductor device.

Abstract: There is provided an apparatus including: a processing cup having an opening opened upward to allow a substrate to be loaded and unloaded, an exhaust port for exhausting an unnecessary atmosphere produced in forming a film applied on the substrate, and an aspiration port for aspirating external air; and an aspiration device aspirating the unnecessary atmosphere through the exhaust port, wherein when the substrate is accommodated in the opening of the processing cup, the substrate has a perimeter spaced from the opening by a predetermined gap, and below the substrate accommodated in the processing cup there is formed an exhaust flow path extending from the aspiration port to the exhaust port.

Abstract: A method of manufacturing an electronic device (10) provides a substrate (20) that has a plastic material and has a metallic coating on one surface. A portion of the metallic coating is etched to form a patterned metallic coating. A particulate material (16) is embedded in at least one surface of the substrate. A layer of thin-film semiconductor material is deposited onto the substrate (20).

Abstract: A semiconductor device having a wiring structure that is enhanced in adhesion between a dielectric thin film and a conductive layer and has high reliability is provided. A method of the invention includes: a step of supplying reactive plasma on a surface of a dielectric thin film in which a plurality of pores are arranged around a skeleton mainly made of a Si—O bond, to perform a pretreatment; a step of forming a conductive film on the surface of the pretreated dielectric thin film by a sputtering method; and before the pretreatment step, bringing a gas containing at least one kind of tetramethylcyclotetrasiloxane (TMCTS), hexamethyldisilazane (HMDS) and trimethylchlorosilane (TMCS) molecules into contact with the surface of the dielectric thin film.

Abstract: An apparatus and process operate to impose sonic pressure upon a spin-on film liquid mass that exhibits a liquid topography and in a solvent vapor overpressure to alter the liquid topography. Other apparatus and processes are disclosed.

Abstract: Methods and apparatus for filling gaps on partially manufactured semiconductor substrates with dielectric material are provided. In certain embodiments, the methods include introducing a first process gas into the processing chamber and accumulating a second process gas in an accumulator maintained at a pressure level substantially highest than that of the processing chamber pressure level. The second process gas is then rapidly introduced from the accumulator into the processing chamber. An excess amount of the second process gas may be provided in the processing chamber during the introduction of the second process gas. Flowable silicon-containing films forms on a surface of the substrate to at least partially fill the gaps.

Abstract: Methods of fabricating a microelectromechanical structure are provided. An exemplary embodiment of a method of fabricating a microelectromechanical structure comprises providing a substrate. A first patterned sacrificial layer is formed on portions of the substrate, the first patterned sacrificial layer comprises a bulk portion and a protrusion portion. A second patterned sacrificial layer is formed over the first sacrificial layer, covering the protrusion portion and portions of the bulk portion of the first patterned sacrificial layer, wherein the second patterned sacrificial layer does not cover sidewalls of the first patterned sacrificial layer. An element layer is formed over the substrate, covering portions of the substrate, the first patterned sacrificial layer and second patterned sacrificial layer. The first and second patterned sacrificial layers are removed, leaving a microstructure on the substrate.

Abstract: There is provided a coating and processing apparatus including a spin chuck horizontally holding a quadrangular substrate and rotating the substrate in a horizontal plane, a coating solution nozzle for supplying a coating solution to a front surface of the substrate horizontally held by the spin chuck, and a solvent supply mechanism provided in the spin chuck for supplying a solvent to a back surface of the substrate, in which the solvent supplied to the back surface of the substrate is allowed to reach the back surface and side surface of each of corners of the substrate by centrifugal force, thereby removing the coating solution attached.

Abstract: The present invention related to a method for manufacturing a semiconductor device. More particularly, this method describes how to manufacture a semiconductor device having a porous, low dielectric constant layer formed between metal lines, comprising an insulation layer enveloping fillers.

Abstract: Methods of forming a pattern and methods of fabricating a semiconductor device having a pattern are provided, the methods include forming a self-assembly induction layer including a first region and a second region on a semiconductor substrate. A block copolymer layer is coated on the self-assembly induction layer. A first pattern, a second pattern and a third pattern are formed by phase separating the block copolymer. At least one of the first, second and third patterns may be removed to form a preliminary pattern. An etching process may be performed using the preliminary pattern as an etching mask. The first pattern contains the same material as that of the second pattern, and the third pattern contains a material different from that of the first pattern.

Abstract: According to one embodiment, a method of forming a pattern includes forming a monolayer on a substrate, selectively exposing the monolayer to an energy beam and selectively modifying exposed portions thereof to form patterns of exposed and unexposed portions, forming a block copolymer layer includes first and second block chains on the monolayer, and causing the block copolymer layer to be phase-separated to form patterns of the first and second block chains of the block copolymer layer based on the patterns of the exposed and unexposed portions of the monolayer.

Abstract: In a mold in which a pattern is formed of a fine concavo-convex shape, two or more of alignment marks for determining a relative positional relation between a substrate and a mold are formed concentrically. Moreover, a damaged mark is identified from the positional information and shape of the respective marks, and an alignment between the mold and the substrate to which a resin film is applied is carried out excluding the damaged mark.

Abstract: Some embodiments include methods of forming patterns utilizing copolymer. A copolymer composition is formed across a substrate. The composition includes subunits A and B, and will be self-assembled to form core structures spaced center-to-center by a distance of L0. The core structures are contained within a repeating pattern of polygonal unit cells. Distances from the core structures to various locations of the unit cells are calculated to determine desired distributions of subunit lengths.

Abstract: A method of forming a porous composite material in which substantially all of the pores within the composite material are small having a diameter of about 5 nm or less and with a narrow PSD is provided. The porous composite material includes a first solid phase having a first characteristic dimension and a second phase comprised of pores having a second characteristic dimension, wherein the characteristic dimensions of at least one of said phases is controlled to a value of about 5 nm or less.

Abstract: Systems and methods associated with semiconductor articles are disclosed, including forming a first layer of material on a substrate, etching trenches within regions defining a passive element in the first layer, forming metal regions on sidewalls of the trenches, and forming a region of dielectric or polymer material over or in the substrate. Moreover, an exemplary method may also include forming areas of metal regions on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the passive element(s) that are aligned substantially perpendicularly with respect to a primary plane of the substrate. Other exemplary embodiments may comprise various articles or methods including capacitive and/or inductive aspects, Titanium- and/or Tantalum-based resistive aspects, products, products by processes, packages and composites consistent with one or more aspects of the innovations set forth herein.

Abstract: A method of lithography patterning includes forming a first material layer on a substrate; forming a first patterned resist layer including at least one opening therein on the first material layer; forming a second material layer on the first patterned resist layer and the first material layer; forming a second patterned resist layer including at least one opening therein on the second material layer; and etching the first and second material layers uncovered by the first and second patterned resist layers.

Abstract: A method for making a micro-electronic non-volatile memory device provided with transistors having gates placed side by side, the method comprising the steps of: a) forming in a layer based on at least one first gate material lying on a support, at least one first transistor gate block and at least one sacrificial block, said first block and said sacrificial block being separated by a given space, b) forming in said given space a stack comprising at least one insulating layer and at least one second gate material, said gate material located in said space being intended to form a second gate block separated from the first block by said insulating layer, c) suppressing said sacrificial block.

Abstract: The present invention provides an optoelectronic memory device, the method for manufacturing and evaluating the same. The optoelectronic memory device according to the present invention includes a substrate, an insulation layer, an active layer, source electrode and drain electrode. The substrate includes a gate, and the insulation layer is formed on the substrate. The active layer is formed on the insulation layer, and more particularly, the active layer is formed of a composite material comprising conjugated conductive polymers and quantum dots. Moreover, both of the source and the drain are formed on the insulation layer, and electrically connected to the active layer.

Abstract: Embodiments described herein relate to materials and processes for patterning and etching features in a semiconductor substrate. In one embodiment, a method of forming a composite amorphous carbon layer is provided. The method comprises positioning a substrate in a process chamber, introducing a hydrocarbon source gas into the process chamber, introducing a diluent source gas into the process chamber, introducing a plasma-initiating gas into the process chamber, generating a plasma in the process chamber, forming an amorphous carbon initiation layer on the substrate, wherein the hydrocarbon source gas has a volumetric flow rate to diluent source gas flow rate ratio of 1:12 or less, and forming a bulk amorphous carbon layer on the amorphous carbon initiation layer, wherein a hydrocarbon source gas used to form the bulk amorphous carbon layer has a volumetric flow rate to a diluent source gas flow rate of 1:6 or greater.

Abstract: The present invention provides a method of forming a semiconducting device comprising an organic semiconducting material, which method comprises: heating a composition comprising the organic semiconducting material to a temperature at or above the melting point or glass transition temperature of the composition to form a melt; cooling the melt to a temperature below the melting point or glass transition temperature of the composition; and wherein a first substance or object capable of inhibiting and/or preventing dewetting is adjacent the composition before or during heating, or the composition further comprises an agent capable of inhibiting and/or preventing dewetting.

Abstract: Embodiments of the invention provide methods and systems for depositing a viscous material on a substrate surface. In one embodiment, the invention provides a method of depositing a viscous material on a substrate surface, the method comprising: applying a pre-wet material to a surface of a substrate; depositing a viscous material atop the pre-wet material; rotating the substrate about an axis to spread the viscous material along the surface of the substrate toward a substrate edge; and depositing additional pre-wet material in a path along the surface and adjacent the spreading viscous material.

Abstract: A non-volatile memory device includes a plurality of unit cells. Each unit cell includes lower and upper electrodes over a substrate, a conductive organic material layer between the lower and the upper electrodes, and a nanocrystal layer located within the conductive organic material layer, wherein the nanocrystal layer includes a plurality of nanocrystals surrounded by an amorphous barrier. The unit cell receives a plurality of voltage ranges to perform a plurality of operations. A read operation is performed when an input voltage is in a first voltage range. A first write operation is performed when the input voltage is in a second voltage range higher than the first voltage range. A second write operation is performed when the input voltage is in a third voltage range higher than the second voltage range. An erase operation is performed when the input voltage is higher than the third voltage range.

Abstract: Method and systems provide growth of polymer structures at a high rate in a selective manner. In various embodiments, the method or system can expose the growth site to a polymer source and growing a polymer tube at a rate of at least 80 micrometer per hour at the growth site. The method or system can provide selectivity by providing a growth site on a substrate by patterning a metal, such as copper, that provides a seed site for the polymer. Non-selected sites can be coated with a polymer growth inhibitor, such as polyimide or silicon nitride.

Abstract: Disclosed is a low dielectric constant insulating film formed of a polymer containing Si atoms, O atoms, C atoms, and H atoms, which includes straight chain molecules in which a plurality of basic molecules with an SiO structure are linked in a straight chain, binder molecules with an SiO structure linking a plurality of the straight chain molecules. The area ratio of a signal indicating a linear type SiO structure is 49% or more, and the signal amount of the signal indicating Si(CH3) is 66% or more.

Abstract: A method for forming an organic semiconductor thin film includes the steps of forming a mixed ink layer on a principal plane of a printing plate, the mixed ink layer including a mixture of an organic semiconductor material incapable of transcription and an organic material capable of transcription from the printing plate to a substrate in ink form dissolved in a solvent, and forming an organic semiconductor thin film by transcribing the mixed ink layer onto the substrate by transcribing the mixed ink layer on the printing plate to the substrate.

Abstract: Disclosed herein is a composition for producing an insulator. More specifically, the composition comprises a silane-based organic-inorganic hybrid material containing one or more multiple bonds, an acrylic organic crosslinking agent and a silane-based crosslinking agent having six or more alkoxy groups. Also disclosed herein is an organic insulator produced using the insulator composition. The organic insulator is highly crosslinked to facilitate the fabrication of an organic thin film transistor in terms of processing.

Abstract: In the manufacture of electronic devices that use porous dielectric materials, the properties of the dielectric in a pristine state can be altered by various processing steps. In a method for restoring and preserving the pristine properties of a porous dielectric layer, a substrate is provided with a layer of processed porous dielectric on top, whereby the processed porous dielectric is at least partially exposed. A thin aqueous film is formed at least on the exposed parts of the processed porous dielectric. The exposed porous dielectric with the aqueous film is exposed to an ambient containing a mixture comprising at least one silylation agent and dense CO2, resulting in the restoration and preservation of the pristine properties of the porous dielectric.

Abstract: The present invention relates to solution processable passivation layers for organic electronic (OE) devices, and to OE devices, in particular organic field effect transistors (OFETs), comprising such passivation layers.

Abstract: The present invention relates to a solution and a process for activating the surface of a substrate comprising at least one area formed from a polymer, for the purpose of subsequently covering it with a metallic layer deposited via an electroless process. According to the invention, this composition contains: A) an activator formed from one or more palladium complexes; B) a binder formed from one or more organic compounds chosen from compounds comprising at least two glycidyl functions and at least two isocyanate functions; C) a solvent system formed from one or more solvents capable of dissolving said activator and said binder. Application: Manufacture of electronic devices such as, in particular, integrated circuits, especially in three dimensions.

Abstract: New protective coating layers for use in wet etch processes during the production of semiconductor and MEMS devices are provided. The layers include a primer layer, a first protective layer, and an optional second protective layer. The primer layer preferably comprises an organo silane compound in a solvent system. The first protective layer includes thermoplastic copolymers prepared from styrene, acrylonitrile, and optionally other addition-polymerizable monomers such as (meth)acrylate monomers, vinylbenzyl chloride, and diesters of maleic acid or fumaric acid. The second protective layer comprises a highly halogenated polymer such as a chlorinated polymer which may or may not be crosslinked upon heating.

Abstract: A method for manufacturing a thin film transistor including a step of forming a polymer film (a) to a layer above a support substrate, a step of forming a semiconductor element above the polymer film (a), and a step of separating the support substrate from the polymer film (a) formed with the semiconductor element in which the polymer film (a) has a thickness of 1 ?m or more and 30 ?m or less, a transmittance of 80% or higher to a visible light at a wavelength of 400 nm or more and 800 nm or less, a 3 wt % loss temperature of 300° C. or higher, and a melting point of 280° C. or higher.

Abstract: A method of uniformly transferring luminescent quantum dots onto a substrate, comprising: a) preparing a colloidal suspension of luminescent quantum dots in a hydrophobic solvent, wherein the density of the hydrophobic solvent is from 0.67 g/cm3 to 0.96 g/cm3; b) dispensing the suspension onto a convex aqueous surface; c) allowing the hydrophobic solvent to evaporate; d) contacting the film of luminescent quantum dots with a hydrophobic stamp; and e) depositing the film of luminescent quantum dots onto a substrate with the hydrophobic stamp is described herein. Further described is a method of preparing quantum dot based light emitting diodes.

Abstract: A method of assembling composite structures from objects in fluid includes providing a plurality of objects, each having a preselected size, shape, and spatial distribution of surface structural features characterizing a surface roughness; dispersing the objects into the fluid; and introducing a depletion agent. The depletion agent includes a plurality of particles having a size distribution preselected causing an attractive force arising from a depletion attraction between at least a first object and second object of the plurality in at least one relative position and orientation based on the preselected spatial distribution of surface structural features on the first and second objects, and the depletion attraction between the first and second objects forms at least one rigid bond or slippery bond at or proximate to respective surface portions based on the preselected spatial distribution of surface structural features on the first and second objects to form a two-object composite structure.

Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case (particularly in the latter), capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, such as silane-based SAMs, can be used to form the masking layer. The capping layer can be formed of an electrically conductive material (e.g.

Abstract: Surface-textured encapsulations for use with light emitting diodes. In an aspect, a light emitting diode apparatus is provided that includes a light emitting diode, and an encapsulation formed upon the light emitting diode and having a surface texture configured to extract light. In an aspect, a method includes encapsulating a light emitting diode with an encapsulation having a surface texture configured to extract light. In an aspect, a light emitting diode lamp is provided that includes a package, at least one light emitting diode disposed within the package, and an encapsulation formed upon the at least one light emitting diode having a surface texture configured to extract light. In another aspect, a method includes determining one or more regions of an encapsulation, the encapsulation configured to cover a light emitting diode, and surface-texturing each region of the encapsulation with one or more geometric features that are configured to extract light.

Abstract: A radiation-curable ink jet ink composition contains a polymerizable compound, an photopolymerization initiator and polysiloxane, in which the ink composition is used for recording on a package substrate as a recording medium; the polymerizable compound contains one or more kinds of compound having a pentaerythritol skeleton; an HLB value of the polysiloxane is 5 to 12; and the polysiloxane content is 0.1 to 2% by mass with respect to the total amount of the ink composition.

Abstract: The invention provides a radiation curable ink jet ink composition including: a monomer equal to or more than 20% by mass and equal to or less than 50% by mass with respect to the total mass of the ink composition, which is represented by the following formula (I); and N-vinylcaprolactam equal to or more than 5% by mass and equal to or less than 15% by mass with respect to the total mass of the ink composition: CH2?CR1—COOR2—O—CH?CH—R3??(I) wherein, R1 is a hydrogen atom or a methyl group, R2 is a divalent organic residue having 2 to 20 carbon atoms, and R3 is a hydrogen atom or monovalent organic residue having 1 to 11 carbon atoms.

Abstract: The present invention provides a production method of a semiconductor device, involving formation of a flattening layer and easy process for layers formed on a semiconductor layer, and also provides a semiconductor device preferably produced by such a production method. The present invention further provides an exposure apparatus preferably used in such a production method.

Abstract: A first nanoscale self-aligned self-assembled nested line structure having a sublithographic width and a sublithographic spacing and running along a first direction is formed from first self-assembling block copolymers within a first layer. The first layer is filled with a filler material and a second layer is deposited above the first layer containing the first nanoscale nested line structure. A second nanoscale self-aligned self-assembled nested line structure having a sublithographic width and a sublithographic spacing and running in a second direction is formed from second self-assembling block copolymers within the second layer. The composite pattern of the first nanoscale nested line structure and the second nanoscale nested line structure is transferred into an underlayer beneath the first layer to form an array of structures containing periodicity in two directions.

Abstract: A method of fabricating a semiconductor device is provided. The method begins by providing a semiconductor device structure having electronic devices formed on a semiconductor substrate, and having an upper metal layer associated with electrical contacts for the electronic devices. The method continues by forming a diffusion barrier layer overlying the upper metal layer. Next, the method deposits a first layer of graded ultra-low-k (ULK) material overlying the diffusion barrier layer, a layer of ULK material overlying the first layer of graded ULK material, and a second layer of graded ULK material overlying the layer of ULK material. The method continues by depositing a layer of low temperature oxide material overlying the second layer of graded ULK material, and forming a layer of metal hard mask material overlying the layer of low temperature oxide material.

Abstract: In the pattern forming method according to the embodiment, second templates are manufactured by an imprint technology using first templates manufactured by applying a predetermined misalignment distribution for each shot on a first substrate by an exposure apparatus. Then, an upper-layer-side pattern is formed by an imprint technology using a second template in which an inter-layer misalignment amount between a lower-layer-side pattern already formed above a second substrate and the upper-layer-side pattern to be formed above the second substrate becomes equal to or lower than a predetermined reference value.

Abstract: Some embodiments include methods of utilizing block copolymer to form patterns between weirs. The methods may utilize liners along surfaces of the weirs to compensate for partial-width segments of the patterns in regions adjacent the weirs. Some embodiments include methods in which spaced apart structures are formed over a substrate, and outer surfaces of the structures are coated with a thickness of coating. Diblock copolymer is used to form a pattern across spaces between the structures. The diblock copolymer includes a pair of block constituents that have different affinities for the coating relative to one another. The pattern includes alternating segments, with the segments adjacent to the coating being shorter than the segments that are not adjacent to the coating. The coating thickness is about the amount by which the segments adjacent to the coating are shorter than the segments that are not adjacent to the coating.

Abstract: A curable composition for an optical material including a specific silicon-containing polymer (A), a specific epoxy resin (B) and an energy ray-sensitive cationic polymerization initiator (C) as essential components.

Abstract: A method for fabricating a fine pattern in a semiconductor device includes forming a first photoresist over a substrate where an etch target layer is formed, doping at least one impurity selected from group III elements and group V elements, of the periodic table, into the first photoresist, forming a photoresist pattern over the first photoresist, performing a dry etching process using the photoresist pattern to expose the first photoresist, etching the first photoresist by an oxygen-based dry etching to form a first photoresist pattern where a doped region is oxidized, and etching the etch target layer using the first photoresist pattern as an etch barrier.

Abstract: A method of lowering the dielectric constant of an organosilicon low k dielectric layer while improving the hardness and thermal stability is provided. A deposited layer of carbon doped oxide, HSQ, or MSQ is cured and treated with a He plasma which improves hardness for a subsequent CMP step and lowers the dielectric constant. There is no loss of H2O or CH4 during the He treatment. The low k dielectric layer is then treated with a H2 plasma which converts some of the Si—O and Si—CH3 bonds near the surface to Si—H bonds, thereby further lowering the dielectric constant and increasing thermal stability that improves breakdown resistance. Moisture uptake is also reduced. The method is especially useful for interconnect schemes with deep sub-micron ground rules. Surprisingly, the k value obtained from two different plasma treatments is lower than when two He treatments or two H2 treatment are performed.

Abstract: A stack of a second photoresist having a second photosensitivity and a first photoresist having a first photosensitivity, which is greater than second photosensitivity, is formed on a substrate. A first pattern is formed in the first photoresist by a first exposure and a first development, while the second photoresist underneath remains intact. A second pattern comprising an array of lines is formed in the second photoresist. An exposed portion of the second photoresist underneath a remaining portion of the first photoresist forms a narrow portion of a line pattern, while an exposed portion of the second photoresist outside the area of the remaining portions of the photoresist forms a wide portion of the line pattern. Each wide portion of the line pattern forms a bulge in the second pattern, which increases overlay tolerance between the second pattern and the pattern of conductive vias.

Abstract: A chemical vapor deposition method such as an atomic-layer-deposition method for forming a patterned thin film includes applying a deposition inhibitor material to a substrate. The deposition inhibitor material is a hydrophilic polymer that is a neutralized acid having a pKa of 5 or less, wherein at least 90% of the acid groups are neutralized. The deposition inhibitor material is patterned simultaneously or subsequently to its application to the substrate, to provide selected areas of the substrate effectively not having the deposition inhibitor material. A thin film is substantially deposited only in the selected areas of the substrate not having the deposition inhibitor material.

Abstract: A method and a material for creating an antireflective coating on an integrated circuit. A preferred embodiment comprises applying a dark polymer material on a reflective surface, curing the dark polymer material, and roughening a top surface of the dark polymer material. The roughening can be achieved by ashing the dark polymer material in an ash chamber. The dark polymer material, preferably a black matrix resin or a polyimide black matrix resin, when ashed in an oxygen rich atmosphere for a short period of time, forms a surface that is capable of absorbing light as well as randomly refracting light it does not absorb. A protective cap layer may be formed on top of the ashed dark polymer material to provide protection for the dark polymer material.

Abstract: In one embodiment, the present invention includes a semiconductor package having a substrate with a first surface to support a semiconductor die. A second surface of the substrate includes compliant conductive pads to provide electrical connections to the semiconductor die. In this way, improved connection between the semiconductor package and a socket is provided. Other embodiments are described and claimed.