Subsequent Heating Modifying Organic Coating Composition Patents (Class 438/781)
  • Patent number: 8937023
    Abstract: A method includes forming an insulating film over a substrate by introducing a cyclic siloxane compound having a cyclic siloxane as a skeleton and having at least one volatile hydrocarbon group bonded to a side chain, and a silicon-containing compound into a plasma, and converting the insulating film to a porous insulating film by adding energy to the insulating film. The silicon-containing compound is decomposed using less energy as compared with the skeleton of the cyclic siloxane compound, the volatile hydrocarbon group, and the bond between the cyclic siloxane compound and the volatile hydrocarbon group.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: January 20, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Fuminori Ito, Yoshihiro Hayashi
  • Patent number: 8932799
    Abstract: A system and method for photoresists is provided. In an embodiment a cross-linking or coupling reagent is included within a photoresist composition. The cross-linking or coupling reagent will react with the polymer resin within the photoresist composition to cross-link or couple the polymers together, resulting in a polymer with a larger molecular weight. This larger molecular weight will cause the dissolution rate of the photoresist to decrease, leading to a better depth of focus for the line.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: January 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hau Wu, Ching-Yu Chang
  • Patent number: 8927439
    Abstract: Organoaluminum coating compositions are used to deposit films on various substrates, which films are subsequently cured to form oxide films useful in a variety of manufacturing applications, particularly where a gas barrier may be used.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: January 6, 2015
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: Deyan Wang, Kathleen M. O'Connell, Peter Trefonas, III
  • Publication number: 20140374887
    Abstract: There is provided a composition for forming a passivation film that satisfies electric insulation, heat-tolerance, solvent-tolerance, and a dry etch back property at the same time.
    Type: Application
    Filed: February 8, 2013
    Publication date: December 25, 2014
    Applicant: NISSAN CHEMICAL IMDUSTRIES, LTD.
    Inventors: Mamoru Tamura, Hiroshi Ogino, Tomoyuki Enomoto
  • Publication number: 20140370704
    Abstract: Methods of forming a dielectric layer are provided. The methods may include introducing oxygen radicals and organic silicon precursors into a chamber to form a preliminary dielectric layer on a substrate. Each of the organic silicon precursors may include a carbon bridge and a porogen such that the preliminary dielectric layer may include carbon bridges and porogens. The methods may also include removing at least some of the porogens from the preliminary dielectric layer to form a porous dielectric layer including the carbon bridges.
    Type: Application
    Filed: May 30, 2014
    Publication date: December 18, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sang-Hoon AHN, Seung-Hyuk CHOI, Kyu-Hee HAN
  • Publication number: 20140370711
    Abstract: Embodiments described herein generally relate to the fabrication of integrated circuits and more particularly to nitrogen doped amorphous carbon layers and processes for depositing nitrogen doped amorphous carbon layers on a semiconductor substrate. In one embodiment, a method of forming a nitrogen doped amorphous carbon layer on a substrate is provided. The method comprises positioning a substrate in a substrate processing chamber, introducing a nitrogen containing hydrocarbon source into the processing chamber, introducing a hydrocarbon source into the processing chamber, introducing a plasma-initiating gas into the processing chamber, generating a plasma in the processing chamber, and forming a nitrogen doped amorphous carbon layer on the substrate.
    Type: Application
    Filed: June 18, 2013
    Publication date: December 18, 2014
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Siu F. CHENG, Jacob JANZEN, Deenesh PADHI, Bok Hoen KIM
  • Publication number: 20140342167
    Abstract: An antireflective coating (ARC) formulation for use in photolithography is provided that comprises silicon-rich polysilanesiloxane resins dispersed in a solvent, as well as a substrate having a surface coated with the ARC formulation and a method of applying the ARC formulation to said surface to form an ARC layer. The polysilanesiloxane resins comprise a first component defined by structural units of (R?)2SiO2; a second component defined by structural units of (R?)SiO3 and a third component defined by structural units of (R??)q+2Si2O4?q. In these polysilanesiloxane resins, the R?, R?, and R?? are independently selected to be hydrocarbon or hydrogen (H) groups; and the subscript q is 1 or 2. Alternatively, the R?, R?, and R?? are independently selected as methyl (Me) or hydrogen (H) groups. Typically, the first component is present in a molar ratio x, the second component is present in molar ratio y, and the third component is present in a molar ratio z, such that (x+y+z)=1, x<y, and x<z.
    Type: Application
    Filed: January 17, 2013
    Publication date: November 20, 2014
    Inventors: Ming-Shin Tzou, Xiaobing Zhou
  • Patent number: 8883548
    Abstract: Electronic device quality Aluminum Antimonide (AlSb)-based single crystals produced by controlled atmospheric annealing are utilized in various configurations for solar cell applications. Like that of a GaAs-based solar cell devices, the AlSb-based solar cell devices as disclosed herein provides direct conversion of solar energy to electrical power.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: November 11, 2014
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: John W. Sherohman, Jick Hong Yee, Arthur W. Combs, III
  • Patent number: 8877657
    Abstract: The present invention relates to a process for producing a layer comprising at least one semiconductive metal oxide on a substrate, comprising at least the steps of: (A) preparing a solution comprising at least one precursor compound of the at least one metal oxide selected from the group consisting of carboxylates of mono-, di- or polycarboxylic acids having at least three carbon atoms, or derivatives of mono-, di- or polycarboxylic acids, alkoxides, hydroxides, semicarbazides, carbamates, hydroxamates, isocyanates, amidines, amidrazones, urea derivatives, hydroxylamines, oximes, urethanes, ammonia, amines, phosphines, ammonium compounds, azides of the corresponding metal and mixtures thereof, in at least one solvent, (B) applying the solution from step (A) to the substrate and (C) thermally treating the substrate from step (B) at a temperature of 20 to 200° C.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: November 4, 2014
    Assignee: BASF SE
    Inventors: Andrey Karpov, Friederike Fleischhaker, Imme Domke, Marcel Kastler, Veronika Wloka, Lothar Weber
  • Patent number: 8877658
    Abstract: Methods for performing directed self-assembly (DSA) of block copolymer (BCP) material on a substrate are disclosed. The BCP is disposed over a patterned neutral layer made from a random copolymer. The BCP is annealed with a laser to induce the directed self-assembly. The scan type may include single scan, multiple scan, or multiple scan with overlap. A variety of power settings and dwell times may be used within a single wafer to achieve multiple heating conditions within a single wafer.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: November 4, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Kenji Yoshimoto
  • Publication number: 20140322922
    Abstract: An apparatus for thermal treatment of dielectric films on substrates comprises: a microwave applicator cavity and microwave power source; a workpiece to be heated in the cavity, comprising a porous coating on a selected substrate; and, a means of introducing a controlled amount of a polar solvent into said porous coating immediately before heating by said microwave power. The interaction of the polar solvent with the microwaves enhances the efficiency of the process, to shorten process time and reduce thermal budget. A related method comprises the steps of: depositing a porous film on a substrate; soft baking the film to a selected state of dryness; introducing a controlled amount of a polar solvent into the soft baked film; and, applying microwave energy to heat the film via interaction with the polar solvent.
    Type: Application
    Filed: April 15, 2014
    Publication date: October 30, 2014
    Inventor: Iftikhar Ahmad
  • Patent number: 8871642
    Abstract: Provided is a method of forming a pattern, including (a) forming a chemically amplified resist composition into a film, (b) exposing the film to light, (c) developing the exposed film with a developer containing an organic solvent, and (d) rinsing the developed film with a rinse liquid containing an organic solvent, which rinse liquid has a specific gravity larger than that of the developer.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: October 28, 2014
    Assignee: FUJIFILM Corporation
    Inventors: Yuichiro Enomoto, Shinji Tarutani, Sou Kamimura, Keita Kato, Kana Fujii
  • Patent number: 8874254
    Abstract: An object of the present invention is to perform temperature setting of a heating plate so that a wafer is uniformly heated in an actual heat processing time. The temperature of a wafer is measured during a heat processing period from immediately after a temperature measuring wafer is mounted on the heating plate to the time when the actual heat processing time elapses. Whether the uniformity in temperature within the wafer is allowable or not is determined from the temperature of the wafer in the heat processing period, and if the determination result is negative, a correction value for a temperature setting parameter of the heating plate is calculated using a correction value calculation model from the measurement result, and the temperature setting parameter is changed.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: October 28, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Shuji Iwanaga, Nobuyuki Sata
  • Patent number: 8865599
    Abstract: Planarization methods and microelectronic structures formed therefrom are disclosed. The methods and structures use planarization materials comprising fluorinated compounds or acetoacetylated compounds. The materials are self-leveling and achieve planarization over topography without the use of etching, contact planarization, chemical mechanical polishing, or other conventional planarization techniques.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: October 21, 2014
    Assignee: Brewer Science Inc.
    Inventors: Dongshun Bai, Xie Shao, Michelle Fowler, Tingji Tang
  • Patent number: 8859442
    Abstract: In various embodiments, the present invention relates to production of encapsulated nanoparticles by dispersing said nanoparticles and an encapsulating medium in a common solvent to form a first solution system and applying a stimulus to said first solution system to induce simultaneous aggregation of the nanoparticles and the encapsulating medium.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: October 14, 2014
    Assignee: Nanoco Technologies Ltd.
    Inventors: Imad Naasani, James Gillies, Emma Fitzgerald, Xiaojuan Wang, Ombretta Masala
  • Publication number: 20140273522
    Abstract: A method of forming a patterned substrate includes casting a layer of a block copolymer having an intrinsic glass transition temperature Tg, on a substrate to form a layered substrate. The method also includes heating the layered substrate at an annealing temperature, which is greater than about 50° C. above the intrinsic glass transition temperature Tg of the block copolymer, in a first atmosphere. The method further includes thermally quenching the layered substrate to a quenching temperature lower than the intrinsic glass transition temperature Tg, at a rate of greater than about 50° C./minute in a second atmosphere. The method further includes controlling an oxygen content in the first and second atmospheres to a level equal to or less than about 8 ppm to maintain the annealing and quenching temperatures below a thermal degradation temperature Td of the block copolymer.
    Type: Application
    Filed: March 10, 2014
    Publication date: September 18, 2014
    Applicant: Tokyo Electron Limited
    Inventor: Benjamen M. Rathsack
  • Publication number: 20140273523
    Abstract: A method of forming a patterned substrate includes casting a layer of a block copolymer having an intrinsic glass transition temperature Tg, on a substrate to form a layered substrate. The method also includes heating the layered substrate at an annealing temperature, which is greater than about 50° C. above the intrinsic glass transition temperature Tg of the block copolymer, in a first atmosphere. The method further includes thermally quenching the layered substrate to a quenching temperature lower than the intrinsic glass transition temperature Tg, at a rate of greater than about 50° C./minute in a second atmosphere. The method further includes controlling an oxygen content in the first and second atmospheres to a level equal to or less than about 50 ppm to maintain the annealing and quenching temperatures below a thermal degradation temperature Td of the block copolymer.
    Type: Application
    Filed: March 10, 2014
    Publication date: September 18, 2014
    Applicant: Tokyo Electron Limited
    Inventor: Benjamen M. Rathsack
  • Publication number: 20140273521
    Abstract: A system and method for photoresists is provided. In an embodiment a cross-linking or coupling reagent is included within a photoresist composition. The cross-linking or coupling reagent will react with the polymer resin within the photoresist composition to cross-link or couple the polymers together, resulting in a polymer with a larger molecular weight. This larger molecular weight will cause the dissolution rate of the photoresist to decrease, leading to a better depth of focus for the line.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
  • Patent number: 8822351
    Abstract: The present invention relates to a composition for a thermosetting silicone resin including: a dual-end silanol type silicone oil; an alkenyl-containing silicon compound; an organohydrogensiloxane; a condensation catalyst; and a hydrosilylation catalyst, in which the condensation catalyst includes a tin complex compound.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: September 2, 2014
    Assignee: Nitto Denko Corporation
    Inventors: Ryuichi Kimura, Hiroyuki Katayama
  • Patent number: 8822138
    Abstract: There is provided a resist underlayer film having both heat resistance and etching selectivity. A composition for forming a resist underlayer film for lithography, comprising a reaction product (C) of an alicyclic epoxy polymer (A) with a condensed-ring aromatic carboxylic acid and monocyclic aromatic carboxylic acid (B). The alicyclic epoxy polymer (A) may include a repeating structural unit of Formula (1): (T is a repeating unit structure containing an alicyclic ring in the polymer main chain; and E is an epoxy group or an organic group containing an epoxy group). The condensed-ring aromatic carboxylic acid and monocyclic aromatic carboxylic acid (B) may include a condensed-ring aromatic carboxylic acid (B1) and a monocyclic aromatic carboxylic acid (B2) in a molar ratio of B1:B2=3:7 to 7:3. The condensed-ring aromatic carboxylic acid (B1) may be 9-anthracenecarboxylic acid and the monocyclic aromatic carboxylic acid (B2) may be benzoic acid.
    Type: Grant
    Filed: August 11, 2010
    Date of Patent: September 2, 2014
    Assignee: Nissan Chemical Industries, Ltd.
    Inventors: Tetsuya Shinjo, Hirokazu Nishimaki, Yasushi Sakaida, Keisuke Hashimoto
  • Patent number: 8815747
    Abstract: A method of forming a pattern on a substrate includes forming spaced features over a substrate. A polymer is adsorbed to outer lateral surfaces of the spaced features. Either material of the spaced features is removed selectively relative to the adsorbed polymer or material of the adsorbed polymer is removed selectively relative to the spaced features to form a pattern on the substrate. In one embodiment, the polymer is of known chain length and has opposing longitudinal ends. One of the longitudinal ends of the polymer adsorbs to the outer lateral surfaces whereby the adsorbed polymer projects lengthwise from the outer lateral surfaces, with said chain length defining a substantially uniform lateral thickness of the adsorbed polymer on the spaced features. Additional embodiments are contemplated.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: August 26, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Anton deVilliers, Scott Sills
  • Publication number: 20140235060
    Abstract: There is provided a resist underlayer film used in lithography process that has a high n value and a low k value, and can effectively reduce reflection of light having a wavelength of 193 nm from the substrate in a three-layer process in which the resist underlayer film is used in combination with a silicon-containing intermediate layer. A resist underlayer film-forming composition used in lithography process including: a polymer containing a unit structure including a product obtained by reaction of a condensed heterocyclic compound and a bicyclo ring compound. The condensed heterocyclic compound is a carbazole compound or a substituted carbazole compound. The bicyclo ring compound is dicyclopentadiene, substituted dicyclopentadiene, tetracyclo[4.4.0.12,5.17,10]dodeca-3,8-diene, or substituted tetracyclo[4.4.0.12,5.17,10]dodeca-3,8-diene.
    Type: Application
    Filed: July 5, 2012
    Publication date: August 21, 2014
    Applicant: NISSAN CHEMICAL INDUSTRIES, LTD.
    Inventors: Tetsuya Shinjo, Yasunobu Someya, Keisuke Hashimoto, Ryo Karasawa
  • Publication number: 20140227887
    Abstract: A phenolic self-crosslinking polymer whose self-crosslinking reaction at a heating step is performed without additives for hardening the polymer, and a composition of resist-underlayer-film containing the same, are disclosed.
    Type: Application
    Filed: September 5, 2012
    Publication date: August 14, 2014
    Inventors: Jeong-Sik Kim, Jae-Hyun Kim, Jae-Woo Lee
  • Patent number: 8802482
    Abstract: Multi-crystalline silicon processing techniques are provided. In one aspect, a method for roughening a multi-crystalline silicon surface is provided. The method includes the following steps. The multi-crystalline silicon surface is coated with a diblock copolymer. The diblock copolymer is annealed to form nanopores therein. The multi-crystalline silicon surface is etched through the nanopores in the diblock copolymer to roughen the multi-crystalline silicon surface. The diblock copolymer is removed. A multi-crystalline silicon substrate with a roughened surface having a plurality of peaks and troughs is also provided, wherein a distance from one peak to an adjacent peak on the roughened surface is from about 20 nm to about 400 nm.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Zhengwen Li, Kejia Wang, Zhen Zhang
  • Patent number: 8802506
    Abstract: A method of manufacturing a semiconductor device sealed in a cured silicone body by placing an unsealed semiconductor device into a mold and subjecting a curable silicone composition which is fed into the space between the mold and the unsealed semiconductor device to compression molding, the method being characterized by the fact that the aforementioned curable silicone composition comprises at least the following components: (A) an epoxy-containing silicone and (B) a curing agent for an epoxy resin; can reduce warping of the semiconductor chips and circuit board, and improve surface resistance to scratching.
    Type: Grant
    Filed: February 14, 2007
    Date of Patent: August 12, 2014
    Assignee: Dow Corning Toray Company, Ltd.
    Inventors: Minoru Isshiki, Tomoko Kato, Yoshitsugu Morita, Hiroshi Ueki
  • Patent number: 8796158
    Abstract: A method for forming a circuit pattern forming region in an insulating substrate may include preparing a metallic pattern, coating a polymer solution on a casting vessel, precuring the polymer solution, and forming an imprinted circuit pattern forming region in the precured polymer solution using the metallic pattern.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: August 5, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kyoung-sei Choi
  • Patent number: 8791033
    Abstract: A process for coating a semiconductor wafer with a coating composition comprises curing the coating with a pulsed UV light, thereby preventing delamination during reflow operations. In a particular embodiment, the coating composition comprises both epoxy and acrylate resins. The epoxy resin can be cured thermally; the acrylate resin is cured by UV irradiation.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: July 29, 2014
    Assignee: Henkel IP & Holding GmbH
    Inventors: Jeffrey Gasa, Dung Nghi Phan, Jeffrey Leon, Sharad Hajela, Shengqian Kong
  • Patent number: 8778815
    Abstract: A method of forming a polyimide film on a surface of a substrate by dehydration condensation of a first monomer including a bifunctional acid anhydride and a second monomer including a bifunctional amine is disclosed. The method includes loading the substrate into a processing chamber, heating the substrate at a temperature at which a polyimide film is formed, and performing a cycle a predetermined number of times. The cycle comprises supplying a first processing gas containing the first monomer to the substrate, supplying a second processing gas containing the second monomer to the substrate. The method further includes supplying a replacement gas in the processing chamber between supplying the first processing gas and supplying the second processing gas thereby replacing atmosphere in the processing chamber by the replacement gas, and evacuating the first and/or the second processing gas out of the processing chamber.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: July 15, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Tatsuya Yamaguchi, Reiji Niino
  • Patent number: 8772181
    Abstract: A production method for producing graphene on a substrate, and the like are provided. According to the method, in a forming step heating is conducted to a solid solution temperature at which a solid solution of carbon dissolved in a metal is able to be formed, and a solid solution layer (505) composed of the solid solution on a substrate (103) is formed; and in a removing step graphene (102) is grown on the substrate (103) by removing the metal from the solid solution layer (505) while maintaining the heating to the solid solution temperature. As a solvent for dissolving carbon a metal composed of a single element as well as various alloys are applicable. The graphene (102) touches directly the substrate (103), by removing the metal from the solid solution layer (505) by supplying an etching gas.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: July 8, 2014
    Assignee: Japan Science and Technology Agency
    Inventors: Suguru Noda, Soichiro Takano
  • Patent number: 8772182
    Abstract: A semiconductor device manufacture method has the steps of: (a) coating a low dielectric constant low-level insulating film above a semiconductor substrate formed with a plurality of semiconductor elements; (b) processing the low-level insulating film to increase a mechanical strength of the low-level insulating film; (c) coating a low dielectric constant high-level insulating film above the low-level insulating film; and (d) forming a buried wiring including a wiring pattern in the high-level insulating film and a via conductor in the low-level insulating film. The low-level insulating film and high-level insulating film are made from the same material. The process of increasing the mechanical strength includes an ultraviolet ray irradiation process or a hydrogen plasma applying process.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: July 8, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Yoshiyuki Ohkura
  • Publication number: 20140187054
    Abstract: A method of patterning a block copolymer layer includes: providing a guide pattern on a surface of a substrate, the guide pattern including sidewalls each elongated in a longitudinal direction and spaced apart from each other, a trench defined by a bottom surface and facing surfaces of the sidewalls, and having a uniform width over an entire length thereof in the longitudinal direction, and a latitudinal wall perpendicular to the longitudinal direction of the trench; providing a block copolymer layer on the surface of the substrate; and annealing the block copolymer to cause self-assembly of the block copolymer and to direct the same in the trench. The block copolymer has a microphase-separation into anisotropic discrete domains aligned with a period ?o in the trench by the annealing.
    Type: Application
    Filed: December 24, 2013
    Publication date: July 3, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youn Jung PARK, Haeng Deog KOH, Mi-Jeong KIM, Seong-Jun JEONG
  • Patent number: 8753986
    Abstract: A deposition for producing a porous organosilica glass film comprising: introducing into a vacuum chamber gaseous reagents including one precursor of an organosilane or an organosiloxane, and a porogen distinct from the precursor, wherein the porogen is aromatic in nature; applying energy to the gaseous reagents in the chamber to induce reaction of the gaseous reagents to deposit a film, containing the porogen; and removing substantially all of the organic material by UV radiation to provide the porous film with pores and a dielectric constant less than 2.6.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: June 17, 2014
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Mary Kathryn Haas, Raymond Nicholas Vrtis, Laura M. Matz
  • Patent number: 8741787
    Abstract: A silicon-based low-k dielectric material is formed on the basis of a single precursor material, such as OMTCS, without incorporating a porogen species. To this end, the initial deposition of the low-k dielectric material may be formed on the basis of a reduced process temperature, while a subsequent treatment, such as a UV treatment, may allow the adjustment of the final material characteristics without causing undue out-gassing of volatile organic components.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: June 3, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ulrich Mayer, Hartmut Ruelke, Christof Streck
  • Patent number: 8736014
    Abstract: A semiconductor device and method for making such that provides improved mechanical strength is disclosed. The semiconductor device comprises a semiconductor substrate; an adhesion layer disposed over the semiconductor substrate; and a porous low-k film disposed over the semiconductor substrate, wherein the porous low-k film comprises a porogen and a composite bonding structure including at least one Si—O—Si bonding group and at least one bridging organic functional group.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: May 27, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Jiun Lin, Ching-Yu Lo, Hai-Ching Chen, Tien-I Bao, Chen-Hua Yu
  • Patent number: 8736051
    Abstract: A semiconductor device includes an interlayer insulating film containing Si, O, C, and H, an under-bump metal film disposed over the interlayer insulating film and containing Ni, and a bump electrode disposed over the under-bump metal film. In the interlayer insulating film, a ratio of a peak height of Si—CH3 near a wave number 1270 cm?1 to a peak height of Si—O near a wave number 1030 cm?1 obtained by Fourier-transform infrared spectroscopy (FTIR) is 0.15 or greater and 0.27 or less. A ratio of a peak height of Si—CH2—Si near a wave number 1360 cm?1 to the peak height of Si—CH3 near the wave number 1270 cm?1 is 0.031 or greater.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: May 27, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuya Usami, Tomoyuki Nakamura, Naoki Fujimoto
  • Patent number: 8722841
    Abstract: There is provided a resist underlayer film having heat resistance that is used for a lithography process in the production of semiconductor devices, and a high refractive index film having transparency that is used for an electronic device. A polymer comprising a unit structure of Formula (1): wherein each of R1, R2, R3, and R5 may be a hydrogen atom, R4 may be phenyl group or naphthyl group. A resist underlayer film forming composition comprising the polymer, and a resist underlayer film formed from the composition. A high refractive index film forming composition comprising the polymer, and a high refractive index film formed from the composition.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: May 13, 2014
    Assignee: Nissan Chemical Industries, Ltd.
    Inventors: Daigo Saito, Hiroaki Okuyama, Hideki Musashi, Tetsuya Shinjo, Keisuke Hashimoto
  • Patent number: 8716151
    Abstract: The present disclosure relates to a method of fabricating semiconductor devices. In the method provided by the present invention, by filling with diblock copolymer a recess of an interlayer dielectric layer naturally formed between two gate lines and then performing a self-assembly process of the diblock copolymer, a small-sized contact hole precisely aligned with an doped area can be formed, and thus misalignment between the contact hole and the doped area can be eliminated or alleviated.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: May 6, 2014
    Assignee: Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Haiyang Zhang, Dongjiang Wang
  • Patent number: 8716150
    Abstract: Methods of forming a semiconductor device are provided. The methods include, for example, forming a low-k dielectric having a continuous planar surface, and, after forming the low-k dielectric, subjecting the continuous planar surface of the low-k dielectric to an ethylene plasma enhanced chemical vapor deposition (PECVD) treatment.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: May 6, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Zhiguo Sun, Songkram Srivathanakul, Huang Liu, Hung-Wei Liu
  • Patent number: 8703880
    Abstract: A curable composition that includes (A) a silane compound copolymer that includes a specific repeating unit, (B) a silane coupling agent having a reactive cyclic ether structure, and (C) a curing agent so that the mass ratio “(A):((B)+(C))” of the silane compound copolymer (A) to the silane coupling agent (B) and the curing agent (C) in total is 95:5 to 70:30, a cured product obtained by curing the curable composition, and method for using of the curable composition as an optical device-securing adhesive or an optical device sealing material, are disclosed. The curable composition produces a cured product that does not show coloration (i.e., does not show a deterioration in transparency) even when exposed to high-energy light or subjected to a high temperature, exhibits excellent transparency for a long time, and has high adhesion even at a high temperature.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: April 22, 2014
    Assignee: Lintec Corporation
    Inventor: Mikihiro Kashio
  • Publication number: 20140106575
    Abstract: Methods for performing directed self-assembly (DSA) of block copolymer (BCP) material on a substrate are disclosed. The BCP is disposed over a patterned neutral layer made from a random copolymer. The BCP is annealed with a laser to induce the directed self-assembly. The scan type may include single scan, multiple scan, or multiple scan with overlap. A variety of power settings and dwell times may be used within a single wafer to achieve multiple heating conditions within a single wafer.
    Type: Application
    Filed: October 17, 2012
    Publication date: April 17, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventor: Kenji YOSHIMOTO
  • Patent number: 8697583
    Abstract: Provided according to embodiments of the present invention are an oxidation-promoting compositions, methods of forming oxide layers, and methods of fabricating semiconductor devices. In some embodiments of the invention, the oxidation-promoting composition includes an oxidation-promoting agent having a structure of A-M-L, wherein L is a functional group that is chemisorbed to a surface of silicon, silicon oxide, silicon nitride, or metal, A is a thermally decomposable oxidizing functional group, and M is a moiety that allows A and L to be covalently bonded to each other.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: April 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-seok Oh, Kyung-mun Byun, Shin-hye Kim, Deok-young Jung, Gil-heyun Choi, Eunkee Hong
  • Patent number: 8691709
    Abstract: A method of forming metal carbide barrier layers for fluorocarbon films in semiconductor devices is described. The method includes depositing a fluorocarbon film on a substrate and depositing a metal-containing layer on the fluorocarbon film at a first temperature, where the metal-containing layer reacts with the fluorocarbon film to form a metal fluoride layer at an interface between the metal-containing layer and the fluorocarbon film. The method further includes heat-treating the metal-containing layer at a second temperature that is greater than the first temperature, wherein the heat-treating the metal-containing layer removes fluorine from the metal fluoride layer by diffusion through the metal-containing layer and forms a metal carbide barrier layer at the interface between the metal-containing layer and the fluorocarbon film, and wherein the metal-containing layer survives the heat-treating at the second temperature without blistering or pealing.
    Type: Grant
    Filed: September 24, 2011
    Date of Patent: April 8, 2014
    Assignee: Tokyo Electron Limited
    Inventor: Yoshiyuki Kikuchi
  • Patent number: 8685865
    Abstract: A method of forming patterns of a semiconductor device may include forming a photoresist layer that includes a photo acid generator (PAG) and a photo base generator (PBG), generating an acid from the PAG in a first exposed portion of the photoresist layer by first-exposing the photoresist layer, and generating a base from the PBG in a second exposed portion of the photoresist layer by second-exposing a part of the first exposed portion and neutralizing the acid. The method may also include baking the photoresist layer after the first and second-exposing and deblocking the photoresist layer of the first exposed portion in which the acid is generated to form a deblocked photoresist layer, and forming a photoresist pattern by removing the deblocked photoresist layer by using a developer.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: April 1, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-ju Park, Kyoung-mi Kim, Min-jung Kim, Dong-jun Lee, Boo-deuk Kim
  • Patent number: 8679987
    Abstract: Embodiments described herein relate to a method for processing a substrate. In one embodiment, the method includes introducing a gas mixture comprising a hydrocarbon source and a diluent gas into a deposition chamber located within a processing system, generating a plasma from the gas mixture in the deposition chamber at a temperature between about 200° C. and about 700° C. to form a low-hydrogen content amorphous carbon layer on the substrate, transferring the substrate into a curing chamber located within the processing system without breaking vacuum, and exposing the substrate to UV radiation within the curing chamber at a curing temperature above about 200° C.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: March 25, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Patrick Reilly, Shahid Shaikh, Tersem Summan, Deenesh Padhi, Sanjeev Baluja, Juan Carlos Rocha-Alvarez, Thomas Nowak, Bok Hoen Kim, Derek R. Witty
  • Patent number: 8674052
    Abstract: There is provided a resist underlayer film having heat resistance that is used for a lithography process in the production of semiconductor devices, and a high refractive index film having transparency that is used for an electronic device. A polymer comprising a unit structure of Formula (1): wherein each of R1, R2, R3, and R5 may be a hydrogen atom, R4 may be phenyl group or naphthyl group. A resist underlayer film forming composition comprising the polymer, and a resist underlayer film formed from the composition. A high refractive index film forming composition comprising the polymer, and a high refractive index film formed from the composition.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: March 18, 2014
    Assignee: Nissan Chemical Industries, Ltd.
    Inventors: Daigo Saito, Hiroaki Okuyama, Hideki Musashi, Tetsuya Shinjo, Keisuke Hashimoto
  • Patent number: 8673793
    Abstract: A method for calculating an offset value for aligned deposition of a second pattern onto a first pattern, comprising steps of: (a) loading a substrate with the first pattern on a surface of the substrate into a pattern recognition device at an original position inside the pattern recognition device; (b) determining a coordinate of a prescribed point of the first pattern by the pattern recognition device; (c) superimposing the second pattern onto the first pattern on the surface of the substrate; (d) bringing back the substrate with the first pattern and the second pattern into the original position inside the pattern recognition device; (e) determining a coordinate of a prescribed point of the second pattern by the pattern recognition device; wherein the prescribed point of the first pattern corresponds to the prescribed point of the second pattern; and (f) calculating the offset value between the first pattern and the second pattern.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: March 18, 2014
    Inventor: Andreas Meisel
  • Patent number: 8657961
    Abstract: Embodiments of the invention generally provide methods for cleaning a UV processing chamber. In one embodiment, the method includes flowing an oxygen-containing gas through a plurality of passages formed in a UV transparent gas distribution showerhead and into a processing region located between the UV transparent gas distribution showerhead and a substrate support disposed within the thermal processing chamber, exposing the oxygen-containing gas to UV radiation under a pressure scheme comprising a low pressure stage and a high pressure stage to generate reactive oxygen radicals, and removing unwanted residues or deposition build-up from exposed surfaces of chamber components presented in the thermal processing chamber using the reactive oxygen radicals.
    Type: Grant
    Filed: April 4, 2013
    Date of Patent: February 25, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Bo Xie, Alexandros T. Demos, Scott A. Hendrickson, Sanjeev Baluja, Juan Carlos Rocha-Alvarez
  • Patent number: 8652965
    Abstract: One object of the present invention is to provide a method for producing a thick film metal electrode that is able to form a positive-negative reverse type resist, which has a thickness of 7 ?m or more and excellent in-plane uniformity, on the circuit element formed on the silicon carbide substrate, and a method for producing a thick film resist, and the present invention provides a method for producing a thick film resist wherein a first positive-negative reverse type resist having a first viscosity is formed on an upper surface of a circuit element layer which is treated with HMDS, and a second positive-negative reverse type resist having a second viscosity, which is larger than the first viscosity, on the first positive-negative reverse type resist such that a total thickness of the first and second positive-negative reverse type resists constituting a thick film resist be 7 ?m or more.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: February 18, 2014
    Assignee: Showa Denko K.K.
    Inventor: Kenji Suzuki
  • Patent number: 8642444
    Abstract: Disclosed herein is a method of manufacturing a bonded substrate, including the steps of: forming a first bonding layer on a surface on one side of a semiconductor substrate; forming a second bonding layer on a surface on one side of a support substrate; adhering the first bonding layer and the second bonding layer to each other; a heat treatment for bonding the first bonding layer and the second bonding layer to each other; and thinning the semiconductor substrate from a surface on the other side of the semiconductor substrate to form a semiconductor layer.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: February 4, 2014
    Assignee: Sony Corporation
    Inventor: Nobutoshi Fujii
  • Patent number: 8642409
    Abstract: According to one embodiment, there is provided a method of manufacturing a semiconductor device. In the method, a substrate portion and a fin portion on the substrate portion are formed. A first silicon oxide film is formed on each side surface of the fin portion. A polysilazane film having an upper surface lower than the upper surface of the first silicon oxide film is formed on each side surface of the first silicon oxide film. The polysilazane film is converted into a silicon oxynitride film. The first silicon oxide film is etched to make the upper surface of the first silicon oxide film not higher than the upper surface of the silicon oxynitride film. A heavily doped semiconductor layer is formed in the fin portion.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: February 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Keisuke Nakazawa