Subsequent Heating Modifying Organic Coating Composition Patents (Class 438/781)
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Patent number: 8080483Abstract: A method of forming a nanoporous film is disclosed. The method comprises forming a coating solution including clusters, surfactant molecules, a solvent, and one of an acid catalyst and a base catalyst. The clusters comprise inorganic groups. The method further comprises aging the coating solution for a time period to select a predetermined phase that will self-assemble and applying the coating solution on a substrate. The method further comprises evaporating the solvent from the coating solution and removing the surfactant molecules to yield the nanoporous film.Type: GrantFiled: November 1, 2007Date of Patent: December 20, 2011Assignee: Purdue Research FoundationInventors: Hugh W. Hillhouse, Vikrant N. Urade, Ta-Chen Wei, Michael P. Tate
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Patent number: 8067316Abstract: A conductive paste including conductive particles each of which has a size of greater than or equal to 0.1 ?m and less than or equal to 10 ?m, a resin, and a solvent is placed over a first conductor and the solvent is vaporized. In this manner, a second conductor having the conductive particles and a memory layer including the resin between the first conductor and the conductive particles is formed.Type: GrantFiled: June 16, 2009Date of Patent: November 29, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Takaaki Nagata
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Patent number: 8058153Abstract: There is provided a damage recovery method capable of recovering electrical characteristics of a low dielectric insulating film sufficiently while suppressing oxidation of buried metal and generation of pattern defaults. A damaged functional group generated in a surface of the low dielectric insulating film by a processing is substituted with a hydrophobic functional group (ST. 2). A damaged component present under a dense layer generated in the surface of the low dielectric insulating film by the substitution process is recovered by using an ultraviolet heating process (ST. 3).Type: GrantFiled: June 12, 2008Date of Patent: November 15, 2011Assignee: Tokyo Electron LimitedInventors: Ryuichi Asako, Yusuke Ohsawa
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Patent number: 8058183Abstract: A method for restoring the dielectric constant of a low dielectric constant film is described. A porous dielectric layer having a plurality of pores is formed on a substrate. The plurality of pores is then filled with an additive to provide a plugged porous dielectric layer. Finally, the additive is removed from the plurality of pores.Type: GrantFiled: June 9, 2009Date of Patent: November 15, 2011Assignee: Applied Materials, Inc.Inventors: Zhenjiang Cui, May Yu, Alexandros T. Demos, Mehul Naik
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Patent number: 8053377Abstract: System and method for forming a structure including a MEMS device structure. In order to prevent warpage of a substrate arising from curing process for a sacrificial material (such as a photoresist), and from subsequent high temperature process steps, an improved sacrificial material comprises (i) a polymer and (ii) a foaming agent or special function group. The structure can be formed by forming a trench in a substrate and filling the trench with a sacrificial material. The sacrificial material includes (i) a polymer and (ii) a foaming agent or special function group. After further process steps are completed, the sacrificial material is removed from the trench.Type: GrantFiled: September 28, 2010Date of Patent: November 8, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shang-Ying Tsai, Chun-Ren Cheng, Jiou-Kang Lee, Jung-Huei Peng, Ting-Hau Wu
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Patent number: 8053376Abstract: In a method of making a polymer structure on a substrate a layer of a first polymer, having a horizontal top surface, is applied to a surface of the substrate. An area of the top surface of the polymer is manipulated to create an uneven feature that is plasma etched to remove a first portion from the layer of the first polymer thereby leaving the polymer structure extending therefrom. A light emitting structure includes a conductive substrate from which an elongated nanostructure of a first polymer extends. A second polymer coating is disposed about the nanostructure and includes a second polymer, which includes a material such that a band gap exists between the second polymer coating and the elongated nanostructure. A conductive material coats the second polymer coating. The light emitting structure emits light when a voltage is applied between the conductive substrate and the conductive coating.Type: GrantFiled: June 26, 2009Date of Patent: November 8, 2011Assignee: Georgia Tech Research CorporationInventors: Zhong L. Wang, Xudong Wang, Jenny R. Morber, Jin Liu
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Patent number: 8048814Abstract: A method of aligning a set of patterns on a substrate, the substrate including a substrate surface, is disclosed. The method includes depositing a set of silicon nanoparticles on the substrate surface, the set of nanoparticles including a set of ligand molecules including a set of carbon atoms, wherein a first set of regions is formed where the silicon nanoparticles are deposited and the remaining portions of the substrate surface define a second set of regions. The method also includes densifying the set of silicon nanoparticles into a thin film wherein a set of silicon-organic zones are formed on the substrate surface, wherein the first set of regions has a first reflectivity value and the second set of regions has a second reflectivity value. The method further includes illuminating the substrate surface with an illumination source, wherein the ratio of the second reflectivity value to the first reflectivity value is greater than about 1.1.Type: GrantFiled: May 19, 2009Date of Patent: November 1, 2011Assignee: Innovalight, Inc.Inventors: Andreas Meisel, Michael Burrows, Homer Antoniadis
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Publication number: 20110263136Abstract: In a composition of forming a passivation layer, the composition includes about 30 to about 60 percent by weight of a mixed polymer resin formed by blending polyamic acid and polyhydroxy amide, about 3 to about 10 percent by weight of a photoactive compound, about 2 to about 10 percent by weight of a cross-linking agent and an organic solvent. The passivation layer formed by using the composition has superior mechanical and physical properties, in which disadvantages of polyimide and polybenzoxazole are compensated by mixing both materials.Type: ApplicationFiled: March 23, 2011Publication date: October 27, 2011Inventors: Soo-Young Kim, Chang-Ho Lee, Su-Min Park
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Patent number: 8043977Abstract: Provided is a semiconductor device containing a silicon single crystal substrate 101, a silicon carbide layer 102 provided on a surface of the substrate, a Group III nitride semiconductor junction layer 103 provided in contact with the silicon carbide layer, and a superlattice-structured layer 104 constituted by Group III nitride semiconductors on the Group III nitride semiconductor junction layer. In this semiconductor device, the silicon carbide layer is a layer of a cubic system whose lattice constant exceeds 0.436 nm and is not more than 0.460 nm and which has a nonstoichiometric composition containing silicon abundantly in terms of composition, and the Group III nitride semiconductor junction layer has a composition of AlxGaYInzN1-?M? (0?X, Y, Z?1, X+Y+Z=1, 0??<1, M is a Group V element except nitrogen).Type: GrantFiled: August 7, 2006Date of Patent: October 25, 2011Assignees: Showa Denko K.K., The DoshishaInventors: Tadashi Ohachi, Takashi Udagawa
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Patent number: 8030139Abstract: A method of producing a thin film transistor includes a gate electrode formation step that forms a gate electrode on a substrate, a gate insulating layer formation step that forms a gate insulating layer on the substrate in such a manner as to cover the gate electrode formed in the gate electrode formation step, a source/drain electrodes formation step that forms a source electrode and a drain electrode on the gate insulating layer, and a semiconductor layer formation step that applies an aqueous solution for semiconductor layer formation which is an aqueous solution comprising at least a single wall carbon nanotube and a surfactant between the source electrode and the drain electrode formed in the source/drain electrodes formation step by a coating process to form a semiconductor layer comprising the single wall carbon nanotube.Type: GrantFiled: March 25, 2009Date of Patent: October 4, 2011Assignee: Brother Kogyo Kabushiki KaishaInventors: Takeshi Asano, Taishi Takenobu, Masashi Shiraishi
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Patent number: 8030132Abstract: To simplify a peeling step in a method for manufacturing a semiconductor device including the peeling step. A first layer having a metal film is formed over a substrate; a second layer having a transistor is formed over the first layer having the metal film; a resin material is applied over the layer having the transistor; the resin material is cured by a heat treatment at a first heat treatment temperature to form a resin layer; the layer having the transistor is peeled from the substrate by a heat treatment at a second heat treatment temperature which is higher than the first heat treatment temperature; and the resin layer is peeled from the layer having the transistor by a heat treatment at a third heat treatment temperature which is higher than the second heat treatment temperature.Type: GrantFiled: May 30, 2006Date of Patent: October 4, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kaori Ogita, Tomoko Tamura
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Patent number: 8030221Abstract: Hydrophobicity of a low dielectric constant film comprising a porous silica film is improved by applying a raw material for forming a porous silica film onto a substrate, and performing vapor-phase transport treatment to expose the substrate to an atmosphere of organic amine vapor to which no water is added. Simultaneously, reduction in a dielectric constant, reduction in leakage current, and improvement in mechanical strength are attained by controlling a pore diameter in a predetermined range.Type: GrantFiled: November 12, 2009Date of Patent: October 4, 2011Assignee: Elpida Memory, Inc.Inventors: Yoshinori Cho, Takamaro Kikkawa
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Patent number: 8026114Abstract: An emitter has a plurality of types of light-emitting units with different changes in emission characteristics over time. In addition, the emitter includes a deterioration adjustment device which adjusts the deterioration of the emission characteristics over time in a predetermined type of light-emitting unit. The light-emitting units respectively include a light-emitting layer and a hole donor which supplies positive holes to the light-emitting layer, and the deterioration adjustment device may be the hole donor in which the thickness is adjusted based on the deterioration in emission characteristics over time in the predetermined type of light-emitting unit.Type: GrantFiled: October 27, 2006Date of Patent: September 27, 2011Assignee: Seiko Epson CorporationInventor: Hirofumi Sakai
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Patent number: 8026185Abstract: An object of the present invention is to provide a method for manufacturing an electronic circuit component such as an organic TFT 1, which can manufacture an electronic circuit component excellent in reliability and having quality on a practical level, because an insulating layer and a conductive layer which have more excellent characteristics can be formed, particularly, on a general-purpose plastic substrate or the like by treatment at a process temperature of 200° C. or lower which has no influence on the above-mentioned plastic substrate. The method for manufacturing an electronic circuit component according to the invention includes heating a layer containing at least one of a polyimide and a precursor thereof at a temperature of 200° C.Type: GrantFiled: August 3, 2007Date of Patent: September 27, 2011Assignees: Sumitomo Electric Industries, Ltd., Nissan Chemical Industries, Ltd.Inventors: Shinichi Maeda, Go Ono, Issei Okada, Kohei Shimoda
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Patent number: 8026186Abstract: The present invention provides a microwave annealing method for a plastic substrate. The method comprises pulsed microwave annealing to an organic photo-voltaic device to avoid warpage and degradation of the plastic substrate. Utilizing pulsed microwave annealing method can improve the wettability of the organic layer on the plastic substrate verified by contact angle measurement, and achieving the organic solar cell fabricated with higher power conversion efficiency.Type: GrantFiled: October 6, 2010Date of Patent: September 27, 2011Assignee: National Tsing Hua UniversityInventors: Sheng-Fu Horng, Jen-Chun Wang, Tse-Pan Yang, Ming-Kun Lee, Tarng-Shiang Hu, Hsin-Fei Meng
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Publication number: 20110227056Abstract: It is an object to provide a novel forming agent for a gate insulating film that not only provides high insulating properties for the gate insulating film but also takes account of the electric characteristics of a thin film transistor element. A forming agent for a gate insulating film of a thin film transistor characterized by comprising an oligomer compound or a polymer compound including a structural unit containing a pyrimidinetrione ring having a hydroxyalkyl-containing group as a substituent on a nitrogen atom; a gate insulating film formed by the forming agent; and a thin film transistor.Type: ApplicationFiled: November 26, 2009Publication date: September 22, 2011Applicant: NISSAN CHEMICAL INDUSTRIES, LTD.Inventors: Shinichi Maeda, Takahiro Kishioka
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Patent number: 8021936Abstract: A thin film transistor (TFT) and a method of manufacturing the same are provided. The TFT includes a transparent substrate, an insulating layer on a region of the transparent substrate, a monocrystalline silicon layer, which includes source, drain, and channel regions, on the insulating layer and a gate insulating film and a gate electrode on the channel region of the monocrystalline silicon layer.Type: GrantFiled: March 26, 2009Date of Patent: September 20, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Takashi Noguchi, Wenxu Xianyu, Hans S. Cho, Huaxiang Yin
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Patent number: 8021974Abstract: An improved semiconductor structure consists of interconnects in an upper interconnect level connected to interconnects in a lower interconnect level through use of a conductive protrusion located at the bottom of a via opening in an upper interconnect level, the conductive protrusion extends upward from bottom of the via opening and into the via opening. The improved interconnect structure with the conductive protrusion between the upper and lower interconnects enhances overall interconnect reliability.Type: GrantFiled: January 9, 2009Date of Patent: September 20, 2011Assignee: Internatioanl Business Machines CorporationInventors: Chih-Chao Yang, David Vaclav Horak, Takeshi Nogami, Shom Ponoth
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Patent number: 8017527Abstract: Apparatuses and methods for diverting a flow of a liquid precursor during flow stabilization and plasma stabilization stages during PECVD processes are effective at eliminating particle defects in PECVD films deposited using a liquid precursor.Type: GrantFiled: December 16, 2008Date of Patent: September 13, 2011Assignee: Novellus Systems, Inc.Inventors: Arul N. Dhas, Ming Li, Joseph Bradley Laird
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Patent number: 8014895Abstract: An object of the present invention is to perform temperature setting of a heating plate so that a wafer is uniformly heated in an actual heat processing time. The temperature of a wafer is measured during a heat processing period from immediately after a temperature measuring wafer is mounted on the heating plate to the time when the actual heat processing time elapses. Whether the uniformity in temperature within the wafer is allowable or not is determined from the temperature of the wafer in the heat processing period, and if the determination result is negative, a correction value for a temperature setting parameter of the heating plate is calculated using a correction value calculation model from the measurement result, and the temperature setting parameter is changed.Type: GrantFiled: December 7, 2005Date of Patent: September 6, 2011Assignee: Tokyo Electron LimitedInventors: Shuji Iwanaga, Nobuyuki Sata
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Publication number: 20110207331Abstract: There is provided a resist underlayer film forming composition for lithography, which in order to prevent a resist pattern from collapsing after development in accordance with the miniaturization of the resist pattern, is applied to multilayer film process by a thin film resist, has a lower dry etching rate than resists and semiconductor substrates, and has a satisfactory etching resistance relative to a substrate to be processed in the processing of the substrate. A resist underlayer film forming composition used in lithography process by a multiplayer film, comprises a polymer containing a unit structure having an aromatic fused ring, a unit structure having a protected carboxyl group or a unit structure having an oxy ring. A method of forming a pattern by use of the resist underlayer film forming composition. A method of manufacturing a semiconductor device by utilizing the method of forming a pattern.Type: ApplicationFiled: April 26, 2011Publication date: August 25, 2011Applicant: NISSAN CHEMICAL INDUSTRIES, LTD.Inventors: Takahiro Sakaguchi, Tomoyuki Enomoto, Tetsuya Shinjo
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Patent number: 8003487Abstract: In methods of forming a trench, first patterns separated from each other by a first width and second patterns separated from each other by a second width are formed on a substrate. The second width is wider than the first width. The substrate is etched using the first patterns and the second patterns to form a first trench having a first depth and a preliminary second trench having a second depth. A sacrificial layer is formed to fill up a space between the first patterns. The substrate is etched using the sacrificial layer to form a second trench having a third depth deeper than the second depth.Type: GrantFiled: December 16, 2008Date of Patent: August 23, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Du-Hyun Cho, Jong-Heui Song, Sang-Sup Jeong, Tae-Woo Kang, Seung-Joo Yoo
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Patent number: 7998875Abstract: A method of treating a nanoporous low-k dielectric material formed on a semiconductor substrate is provided. The low-k dielectric material has etched openings with an etch damaged region containing silanol groups on exterior surfaces of the etched openings and on interior surfaces of interconnected pores. First, the low-k dielectric material is contacted with a vapor phase catalyst in an amount effective to form hydrogen bonds between the catalyst and the silanol groups in the etch damaged region, forming a catalytic intermediary.Type: GrantFiled: December 8, 2008Date of Patent: August 16, 2011Assignee: Lam Research CorporationInventor: James DeYoung
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Patent number: 7989361Abstract: This invention pertains to a composition for a dielectric thin film, which is capable of being subjected to a low-temperature process. Specifically, the invention is directed to a metal oxide dielectric thin film formed using the composition, a preparation method thereof, a transistor device comprising the dielectric thin film, and an electronic device comprising the transistor device. The electronic device to which the dielectric thin film has been applied exhibits excellent electrical properties, thereby satisfying both a low operating voltage and a high charge mobility.Type: GrantFiled: July 31, 2007Date of Patent: August 2, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jong Baek Seon, Hyun Dam Jeong, Sang Yoon Lee
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Patent number: 7989366Abstract: Methods are disclosed for activating dopants in a doped semiconductor substrate. A carbon precursor is flowed into a substrate processing chamber within which the doped semiconductor substrate is disposed. A plasma is formed from the carbon precursor in the substrate processing chamber. A carbon film is deposited over the substrate with the plasma. A temperature of the substrate is maintained while depositing the carbon film less than 500° C. The deposited carbon film is exposed to electromagnetic radiation for a period less than 10 ms, and has an extinction coefficient greater than 0.3 at a wavelength comprised by the electromagnetic radiation.Type: GrantFiled: August 24, 2007Date of Patent: August 2, 2011Assignee: Applied Materials, Inc.Inventors: Jeffrey C. Munro, Srinivas D. Nemani, Young S. Lee, Marlon Menezes, Christopher Dennis Bencher, Vijay Parihar
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Patent number: 7985699Abstract: A substrate processing method capable of preventing a substrate rear surface from being scratched when attracted onto an electrostatic chuck. In a coater/developer (11), a photocurable resin is coated onto a rear surface of a wafer (W), the resin is cured to form a resin protective film, and a resist is coated onto a front surface of the wafer. An exposing apparatus (12) subjects the resist to light exposure processing, irradiating ultraviolet light onto a resist portion of a pattern reversed with respect to a mask pattern. The coater/developer uses a washing liquid to remove the resist, thereby forming a resist film. In an etching apparatus (13), the front surface of the wafer is electrostatically attracted onto an electrostatic chuck (49) is subjected to RIE processing. In a washing apparatus (14), the resin protective film is dissolved and removed.Type: GrantFiled: March 21, 2007Date of Patent: July 26, 2011Assignee: Tokyo Electron LimitedInventor: Eiichi Nishimura
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Patent number: 7972976Abstract: Porous dielectric layers are produced by introducing pores in pre-formed composite dielectric layers. The pores may be produced after the barrier material, the metal or other conductive material is deposited to form a metallization layer. In this manner, the conductive material is provided with a relatively smooth continuous surface on which to deposit.Type: GrantFiled: October 27, 2009Date of Patent: July 5, 2011Assignee: Novellus Systems, Inc.Inventors: Willibrordus Gerardus Maria van den Hoek, Nerissa S. Draeger, Raashina Humayun, Richard S. Hill, Jianing Sun, Gary William Ray
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Patent number: 7973390Abstract: A modifier for lowering relative dielectric constant of a low dielectric constant film used in semiconductor devices, the modifier of the low dielectric constant film being characterized in that it contains as an effective component a silicon compound represented by formula (1) R3-nHnSiN3??(1) in which R is a C1-C4 alkyl group, and n is an integer from 0 to 3.Type: GrantFiled: July 11, 2007Date of Patent: July 5, 2011Assignee: Central Glass Company, LimitedInventors: Tsuyoshi Ogawa, Mitsuya Ohashi
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Patent number: 7968977Abstract: The present invention relates to a dicing film having an adhesive film for dicing a wafer and a die adhesive film, which are used for manufacturing a semiconductor package, and a method of manufacturing a semiconductor package using the same. More particularly, the present invention relates to a dicing film wherein a shrinkage release film is inserted between an adhesive film for dicing a wafer and a die adhesive film so that the die adhesive film and a die can be easily separated from the adhesive film for dicing a wafer when picking up a semiconductor die, and a method of manufacturing a semiconductor package using the same.Type: GrantFiled: December 10, 2004Date of Patent: June 28, 2011Assignee: LG Innotek Co., Ltd.Inventors: Joon Mo Seo, Hyuk Soo Moon, Cheol Jong Han, Jong Geol Lee, Kyung Tae Wi
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Patent number: 7960291Abstract: The present invention provides porous organosilicate layers, and vapor deposition systems and methods for preparing such layers on substrates. The porous organosilicate layers are useful, for example, as masks.Type: GrantFiled: August 28, 2008Date of Patent: June 14, 2011Assignee: Micron Technology, Inc.Inventor: Eugene P. Marsh
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Patent number: 7951729Abstract: A passivating coupling material for, on the one hand, passivating a dielectric layer in a semiconductor device, and on the other hand, for permitting or at least promoting liquid phase metal deposition thereon in a subsequent process step. In a particular example, the dielectric layer may be a porous material having a desirably decreased dielectric constant k, and the passivating coupling material provides steric shielding groups that substantially block the adsorption and uptake of ambient moisture into the porous dielectric layer. The passivating coupling materials also provides metal nucleation sides for promoting the deposition of a metal thereon in liquid phase, in comparison with metal deposition without the presence of the passivating coupling material. The use of a liquid phase metal deposition process facilitates the subsequent manufacture of the semiconductor device.Type: GrantFiled: February 12, 2010Date of Patent: May 31, 2011Assignee: NXP B.V.Inventors: Janos Farkas, Srdjan Kordic, Cindy Goldberg
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Patent number: 7951728Abstract: A method for selective oxidation of silicon containing materials in a semiconductor device is disclosed and claimed. In one aspect, a rapid thermal processing apparatus is used to selectively oxidize a substrate by in-situ steam generation at high pressure in a hydrogen rich atmosphere. Other materials, such as metals and barrier layers, in the substrate are not oxidized.Type: GrantFiled: September 24, 2007Date of Patent: May 31, 2011Assignee: Applied Materials, Inc.Inventors: Yoshitaka Yokota, Norman Tam, Balasubramanian Ramachandran, Martin John Ripley
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Patent number: 7947565Abstract: A method of forming a porous low-k layer is described. A CVD process is conducted to a substrate, wherein a framework precursor and a porogen precursor are supplied. In an end period of the supply of the framework precursor, the value of at least one deposition parameter negatively correlated with the density of the product of the CVD process is decreased.Type: GrantFiled: February 7, 2007Date of Patent: May 24, 2011Assignee: United Microelectronics Corp.Inventors: Mei-Ling Chen, Kuo-Chih Lai, Su-Jen Sung, Chien-Chung Huang, Yu-Tsung Lai
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Publication number: 20110111533Abstract: Treatment of carbon-containing low-k dielectric with UV radiation and a reducing agent enables process-induced damage repair. Also, treatment with a reducing agent and UV radiation is effective to clean a processed wafer surface by removal of metal oxide (e.g., copper oxide) and/or organic residue of CMP slurry from the planarized surface of a processed wafer with or without low-k dielectric. The methods of the invention are particularly applicable in the context of damascene processing to recover lost low-k property of a dielectric damaged during processing, either pre-metalization, post-planarization, or both, and/or provide effective post-planarization surface cleaning to improve adhesion of subsequently applied dielectric barrier and/or other layers.Type: ApplicationFiled: December 23, 2009Publication date: May 12, 2011Inventors: Bhadri Varadarajan, George A. Antonelli, Bart van Schravendijk
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Patent number: 7919350Abstract: An image sensor is formed by providing a semiconductor substrate having first, second and third pixel regions and first and second color filters disposed on their respective pixel regions. A photoresist layer is coated over the first and second color filters and the third color pixel region. The photoresist is removed from the first and second color filters, leaving a third color filter of substantially the same height as the first and second color filters. Micro lenses may then be formed on the color filters.Type: GrantFiled: August 25, 2006Date of Patent: April 5, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Hyun Cho, Jae-Ku Lee, Sun-Wook Heo
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Patent number: 7915180Abstract: A method of fabricating a dielectric material that has an ultra low dielectric constant (or ultra low k) using at least one organosilicon precursor is described. The organosilicon precursor employed in the present invention includes a molecule containing both an Si—O structure and a sacrificial organic group, as a leaving group. The use of an organosilicon precursor containing a molecular scale sacrificial leaving group enables control of the pore size at the nanometer scale, control of the compositional and structural uniformity and simplifies the manufacturing process. Moreover, fabrication of a dielectric film from a single precursor enables better control of the final porosity in the film and a narrower pore size distribution resulting in better mechanical properties at the same value of dielectric constant.Type: GrantFiled: April 17, 2009Date of Patent: March 29, 2011Assignee: International Business Machines CorporationInventors: Stephen M. Gates, Alfred Grill, Robert D. Miller, Deborah A. Neumayer, Son Nguyen
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Patent number: 7915126Abstract: Some embodiments include methods of utilizing polysilazane in forming non-volatile memory cells. The memory cells may be multi-level cells (MLCs). The polysilazane may be converted to silicon nitride, silicon dioxide, or silicon oxynitride with thermal processing and exposure to an ambient that contains one or both of oxygen and nitrogen. The methods may include using the polysilazane in forming a charge trapping layer of a non-volatile memory cell. The methods may alternatively, or additionally include using the polysilazane in forming intergate dielectric material of a non-volatile memory cell. Some embodiments include methods of forming memory cells of a NAND memory array.Type: GrantFiled: February 14, 2007Date of Patent: March 29, 2011Assignee: Micron Technology, Inc.Inventor: Ronald A. Weimer
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Patent number: 7910498Abstract: A method for manufacturing a semiconductor device, including: (a) forming an energy cured resin layer on a semiconductor substrate having an electrode pad and a passivation film; (b) fusing the resin layer without being cured and shrunk by a first energy supply processing; (c) forming a resin boss by curing and shrinking the resin layer after fusion by a second energy supply processing; and (d) forming an electrical conducting layer which is electrically connected to the electrode pad and passes through over the resin boss.Type: GrantFiled: June 22, 2006Date of Patent: March 22, 2011Assignee: Seiko Epson CorporationInventors: Yasuo Yamasaki, Shuichi Tanaka, Nobuaki Hashimoto
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Patent number: 7901743Abstract: A method and system for treating a dielectric film on a plurality of substrates includes disposing the plurality of substrates in a batch processing system, the dielectric film on the plurality of substrates having a dielectric constant value less than the dielectric constant of SiO2. The plurality of substrates are heated, and a treating compound comprising a CxHy containing compound, wherein x and y represent integers greater than or equal to unity is introduced to the process system. A plasma is formed and at least one surface of the dielectric film on said plurality of substrates is exposed to the plasma.Type: GrantFiled: September 30, 2005Date of Patent: March 8, 2011Assignee: Tokyo Electron LimitedInventors: Eric M. Lee, Dorel I. Toma
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Patent number: 7902073Abstract: A method for etching features in an etch layer disposed below a mask on a process wafer is provided. A hydrocarbon based glue layer is deposited. The etch layer on the process wafer is etched with at least one cycle, wherein each cycle comprises depositing a hydrofluorocarbon layer over the mask and on the hydrocarbon based glue layer, wherein the hydrocarbon based glue layer increases adhesion of the hydrofluorocarbon layer and etching the etch layer.Type: GrantFiled: December 14, 2006Date of Patent: March 8, 2011Assignee: Lam Research CorporationInventors: Ji Soo Kim, Sangheon Lee, Deepak K. Gupta, S. M. Reza Sadjadi
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Patent number: 7897521Abstract: Disclosed is a low dielectric constant plasma polymerized thin film using linear organic/inorganic precursors and a method of manufacturing the low dielectric constant plasma polymerized thin film through plasma enhanced chemical vapor deposition and annealing using an RTA apparatus. The low dielectric constant plasma polymerized thin film is effective for the preparation of multilayered metal thin films having a thin film structure with very high thermal stability, a low dielectric constant, and superior mechanical properties.Type: GrantFiled: August 14, 2008Date of Patent: March 1, 2011Assignee: Sungkyunkwan University Foundation For Corporate CollaborationInventors: Donggeun Jung, Sungwoo Lee, Jihyung Woo
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Patent number: 7897504Abstract: A method for fabricating a semiconductor device, in which a lifting phenomenon can be prevented from occurring in forming an amorphous carbon film on an etched layer having tensile stress. According to the invention, since a compression stress on the etched layer or the amorphous carbon film can be reduced or a compression stress film is formed between the etched layer or the amorphous carbon film to prevent a lifting phenomenon from occurring and thus another pattern can be formed to fabricate a highly integrated semiconductor device.Type: GrantFiled: May 11, 2007Date of Patent: March 1, 2011Assignee: Hynix Semiconductor Inc.Inventors: Jung Geun Kim, Cheol Mo Jeong, Whee Won Cho, Seong Hwan Myung
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Patent number: 7897519Abstract: Disclosed is a composition for preparing an organic insulator, including an organic silane material, having a vinyl group, an acetylene group or an acryl group as a functional group for participating in a crosslinking reaction, a crosslinking agent, and a solvent for dissolving the above components. The organic insulator of example embodiments may be provided in the form of a solid insulating film, which may increase charge mobility while decreasing the threshold voltage and operating voltage of OTFTs, and which also may generate relatively slight hysteresis.Type: GrantFiled: June 11, 2007Date of Patent: March 1, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Eun Jeong Jeong, Joo Young Kim, Kyung Seok Son, Eun Kyung Lee, Sang Yoon Lee
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Patent number: 7893538Abstract: An insulating-film-forming composition for a semiconductor device comprising an organic silica sol with a carbon atom content of 11 to 17 atom % and an organic solvent is disclosed. The organic silica sol comprises a hydrolysis-condensation product P1 and a hydrolysis-condensation product P2. The hydrolysis-condensation product P1 is obtained by hydrolyzing and condensing (A) a silane monomer comprising a hydrolyzable group and (B) a polycarbosilane comprising a hydrolyzable group in the presence of (C) a basic catalyst, and the hydrolysis-condensation product P2 is obtained by hydrolyzing and condensing (D) a silane monomer comprising a hydrolyzable group.Type: GrantFiled: January 31, 2007Date of Patent: February 22, 2011Assignee: JSR CorporationInventors: Hisashi Nakagawa, Tatsuya Yamanaka, Masahiro Akiyama, Terukazu Kokubo, Youhei Nobe
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Patent number: 7892985Abstract: Improved methods for preparing a low-k dielectric material on a substrate using microwave radiation are provided. The use of microwave radiation allows the preparation of low-k films to be accomplished at low temperatures. According to various embodiments, microwave radiation is used to remove porogen from a precursor film and/or to increase the strength of the resulting porous dielectric layer. In a preferred embodiment, methods involve (a) forming a precursor film that contains a porogen and a structure former on a substrate, (b) exposing the precursor film to microwave radiation to remove the porogen from the precursor film to thereby create voids within the dielectric material and form the porous low-k dielectric layer and (c) exposing the dielectric material to microwave radiation in a manner that increases the mechanical strength of the porous low-k dielectric layer.Type: GrantFiled: November 15, 2005Date of Patent: February 22, 2011Assignee: Novellus Systems, Inc.Inventors: Seon-Mee Cho, George D. Papasouliotis, Mike Barnes
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Publication number: 20110039420Abstract: A wall surface of a film forming container is heated to or above a vaporization temperature of a material monomer, which is used to form an organic film, by using an external heater formed along the wall surface of the film forming container, substrates are heated to a thermal polymerization reaction temperature by using an internal heater that is disposed apart from the external heater and near a substrate-supporting container in which the substrates are received, and the organic film is formed through thermal polymerization occurring on the substrates by supplying the material monomer into the film forming container.Type: ApplicationFiled: March 16, 2009Publication date: February 17, 2011Applicant: TOKYO ELECTRON LIMITEDInventors: Ken Nakao, Muneo Harada
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Patent number: 7888273Abstract: Multi-cycle methods result in dense, seamless and void-free dielectric gap fill are provided. The methods involve forming liquid or flowable films that partially fill a gap, followed by a solidification and/or anneal process that uniformly densifies the just-formed film. The thickness of the layer formed is such that the subsequent anneal process creates a film that does not have a density gradient. The process is then repeated as necessary to wholly or partially fill or line the gap as desired. The methods of this invention may be used to line or fill high aspect ratio gaps, including gaps having aspect ratios greater than about 6:1 with widths less than about 0.13 ?m.Type: GrantFiled: August 6, 2007Date of Patent: February 15, 2011Assignee: Novellus Systems, Inc.Inventors: Feng Wang, Victor Y. Lu, Brian Lu, Wai-Fan Yau
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Patent number: 7879739Abstract: Embodiments of the invention provide a method to form a high-k dielectric layer on a group III-V substrate with substantially no oxide of the group III-V substrate between the substrate and high-k dielectric layer. Oxide may be removed from the substrate. An organometallic compound may form a capping layer on the substrate from which the oxide was removed. The high-k dielectric layer may then be formed, resulting in a thin transition layer between the substrate and high-k dielectric layer and substantially no oxide of the group III-V substrate between the substrate and high-k dielectric layer.Type: GrantFiled: May 9, 2006Date of Patent: February 1, 2011Assignee: Intel CorporationInventors: Willy Rachmady, James Blackwell, Suman Datta, Jack T. Kavalieros, Mantu K. Hudait
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Patent number: 7875556Abstract: Classes of liquid aminosilanes have been found which allow for the production of silicon carbo-nitride films of the general formula SixCyNz. These aminosilanes, in contrast, to some of the precursors employed heretofore, are liquid at room temperature and pressure allowing for convenient handling. In addition, the invention relates to a process for producing such films. The classes of compounds are generally represented by the formulas: and mixtures thereof, wherein R and R1 in the formulas represent aliphatic groups typically having from 2 to about 10 carbon atoms, e.g., alkyl, cycloalkyl with R and R1 in formula A also being combinable into a cyclic group, and R2 representing a single bond, (CH2)n, a ring, or SiH2.Type: GrantFiled: May 16, 2005Date of Patent: January 25, 2011Assignee: Air Products and Chemicals, Inc.Inventors: Manchao Xiao, Arthur Kenneth Hochberg
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Patent number: 7867797Abstract: In a method of fabricating organic light emitting diode display, a planarization layer is annealed, cured, provided with an ashing treatment, and surface-treated to reduce roughness of the planarization layer. Therefore, it is possible to improve reduce problems such as a decrease in reflectivity and variation of color coordinates of the organic light emitting diode display due to the roughness of the planarization layer.Type: GrantFiled: September 12, 2008Date of Patent: January 11, 2011Assignee: Samsung Mobile Display Co., Ltd.Inventors: Soo-Beom Jo, Jong-Mo Yeo, Jong-Hoon Son, In-Young Jung, Kyung-Jin Yoo, Dae-Hyun No, Do-Hyun Kwon, Choong-Youl Im