Abstract: A method of depositing a film on a substrate, comprising placing the substrate in the presence of plasma energy, and contacting the substrate with a reactive gas component comprising a compound of the formula (R—NH)4−nSiXn, wherein R is an alkyl group, n is 1, 2, or 3, and X is selected from hydrogen or the halogens. The reactive gas composition may further comprise an oxidizer and/or a reducing agent.

Abstract: A method of forming a contact structure in a semiconductor device includes forming an interlayer insulating layer containing impurities on a semiconductor substrate. The interlayer insulating layer is patterned to form a pad contact hole. The pad contact hole is filled with a conductive pad. Thermal oxidation annealing is then carried out to form an oxide layer on a top surface of the conductive pad and at an interface between the conductive pad and the interlayer insulating layer.

Abstract: A method for modifying the hydrophobicity of the surface of a carbon-doped oxide film is disclosed. Carbon-doped oxide films have exhibited a high hydrophobic nature which inhibits effective cleaning of its surface by conventional techniques. The present invention uses a surface treatment comprising a solution of sulfuric acid and hydrogen peroxide in water to alter the hydrophobicity of the carbon-doped oxide. After treatment by the sulfuric acid and hydrogen peroxide solution, the surface of the carbon-doped oxide becomes hydrophilic. Moreover, the modification of the carbon-doped oxide only occurs at the surface. Therefore, the low k dielectric characteristics of the carbon-doped oxide are retained.

Abstract: The invention encompasses a method of forming a silicon-doped aluminum oxide. Aluminum oxide and silicon monoxide are co-evaporated. Subsequently, at least some of the evaporated aluminum oxide and silicon monoxide is deposited on a substrate to form the silicon-doped aluminum oxide on the substrate. The invention also encompasses methods of forming transistors and flash memory devices.

Abstract: A method of formation of a damascene FSG film with good adhesion to silicon nitride in an HDP-CVD system. Silane (SiH4), silicon tetrafluoride (SiF4), oxygen (O2) and argon (Ar) are used as the reactant gases. SiH4, SiF4, and O2 react to form the FSG. Ar is introduced to promote gas dissociation. All four gases are used for depositing most of the FSG film. SiH4 is not used during deposition of the interfacial part of the FSG film. The interfacial part of the FSG film refers either to the topmost portion, if silicon nitride is to be deposited on top of the FSG or the bottom portion if the FSG is to be deposited on top of silicon nitride. Using SiH4 with the SiF4 tends to mitigate the destructive effects of SiF4 throughout most of the deposition. By removing the SiH4 from the deposition of the interfacial part of the FSG film less hydrogen is incorporated into the film in the interfacial region and adhesion to overlying or underlying silicon nitride is improved.

Abstract: A method is provided that conditions the chamber walls of a HDP CVD reactor by forming a layer of doped material prior to depositing dielectric layers of the doped material onto wafers. A consistent deposition rate can be maintained during subsequent deposition. When deposition is halted, the chamber is cleaned and a thin layer of the doped material is formed on the walls. Consequently, the chamber is kept at equilibrium even during periods of idle, thereby allowing the deposition rates to be consistent even after deposition resumes after the idle periods. For prolonged idle times, the chamber is re-cleaned and the doped material is re-deposited periodically, such as every 12 hours.

Abstract: The present invention is related to a metallization structure on a fluorine-containing dielectric and a method for fabrication thereof. This metallization structure comprises a conductive pattern; a fluorine-containing dielectric; and a barrier layer containing a material, i.e. a near noble metal such as Co, Ni, Pt and Pd, said barrier layer comprising at least a first part, being positioned between said fluorine-containing dielectric and said conductive pattern, said first part containing at least a first and a second sub-layer, said first sub-layer contacting said fluorine-containing dielectric and being impermeable for fluorine. Particularly by depositing a layer of said material on a fluorine-containing dielectric, a stable and thin layer of a fluoride of said material is formed in a self-limiting way.

Abstract: A semiconductor device having a dual damascene structure having a highly reliable multilayered interconnection is applied to the present invention. A protective film (12) is formed on a first interconnection (11), and a modified SOG film (13a) is then provided thereon. An etch stopper film (14) is formed on the modified SOG film (13a), and a modified SOG film (15a) is then formed. The modified SOG film (15a), the etch stopper film (14), and the modified SOG film (13a) are etched away using a resist pattern, to form a via hole (17). The modified SOG film (15a) is etched away using the resist pattern, to form a recess (19) serving as a trench interconnection portion. The etch stopper film (14) and the protective film (12) which are exposed are removed, and the recess is filled with a conductive material (20), to form a conductive plug in the via hole and a second interconnection.

Abstract: In one aspect of the invention, a method for forming an integrated circuit having an at least substantially doped porous dielectric includes forming a semiconductor device. The semiconductor device includes at least a portion of a semiconductor substrate. The method also includes forming a dielectric layer disposed outwardly from the semiconductor substrate and surrounding at least a portion of the semiconductor device. The dielectric layer includes an at least substantially porous dielectric material doped with at least one dopant. In addition, the method includes forming a contact layer disposed outwardly from the dielectric layer and operable to provide electrical connection to the semiconductor device.

Abstract: There is provided a film, which is excellent in thermal resistance, has low dielectric constant, and is applicable to a semiconductor device or electric appliances. The low dielectric constant film having thermal resistance comprises molecules comprising boron, nitrogen, and hydrogen, wherein the number of the nitrogen atom is 0.7 to 1.3 and the number of the hydrogen atom is 1.0 to 2.2 based on one boron atom, and of which dielectric constant is at most 3 2.4.

Abstract: A fabrication method for an inter-metal dielectric layer is applicable to multi-level interconnects. A substrate is provided with metal lines formed thereon. A first (fluorinated silicon glass) FSG layer with low fluorine content is then formed on the substrate, followed by forming a biased-clamped FSG layer on the first FSG layer. A second FSG layer with low fluorine content is formed on the biased-clamped layer, prior to forming an oxide cap layer on the second FSG layer. The oxide cap layer is planarized until the oxide cap layer is level with the second FSG layer.

Abstract: A method for making an anisotropic dielectric layer includes the steps of: forming a fluid layer comprising a plurality of magnetizable particles, for example, in a fluid capable of solidifying to fix the configuration of the magnetizable particles in a dielectric matrix; aligning the magnetizable particles of the fluid layer in a predetermined configuration by applying a magnetic field thereto; and fixing the aligned magnetizable particles in the predetermined configuration within the dielectric matrix by solidifying the fluid. In one particularly advantageous application, the fluid layer is coated onto a surface portion of an integrated circuit, such as a fingerprint sensor, to provide mechanical protection without effecting the image resolution.

Abstract: A method of nitriding the gate oxide layer of a semiconductor device includes the chemical growth on a silicon substrate of a native silicon oxide layer ≦1 nm thick; treating said substrate coated with the native silicon oxide layer with gas NO at a temperature ≦700° C. and a pressure level ≦104 Pa to obtain a nitrided native silicon oxide layer; and the growth of the gate oxide layer. The method is applicable to PMOS devices. Further modifications and alternative embodiments of various aspects of the invention will be apparent to those skilled in the art in view of this description. Accordingly, this description is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the general manner of carrying out the invention. It is to be understood that the forms of the invention shown and described herein are to be taken as the presently preferred embodiments.

Abstract: The present invention provides a manufacturing method of a semiconductor device which does not give rise to peeling of a metal film caused by oxygen held in a interlayer insulating film even when the wafer is subjected to a heat treatment after the metal film is formed on the interlayer insulating film. After the formation of the interlayer insulating film, oxygen held in the interlayer insulating film is removed from the interlayer insulating film, then a metal film on the interlayer insulating film.

Abstract: In the fabrication of EDRAM/SDRAM silicon chips with ground rules beyond 0.18 microns, a Si3N4 barrier layer is deposited onto the patterned structure during the borderless polysilicon contact fabrication. It is required that this layer be conformal and has a high hydrogen atom content to prevent junction leakage. These objectives are met with the method of the present invention. In a first embodiment, the Si3N4 layer is deposited in a Rapid Thermal Chemical Vapor Deposition (RTCVD) reactor using a NH3/SiH4 chemistry at a temperature and a pressure in the 600-950° C. and 50-200 Torr ranges respectively. In a second embodiment, it is deposited in a Low Pressure Chemical Vapor Deposition (LPCVD) furnace using a NH3/SiH2Cl2 chemistry (preferred ratio 1:1) at a temperature and a pressure in the 640-700° C. and 0.2-0.8 Torr ranges respectively.

Abstract: An anti-reflective film for deep ultraviolet (DUV) photolithograghy includes silicon oxime having the formula Si(1−x+y+z)NxOy:H2, wherein x, y, and z represent the atomic percentage of nitrogen, oxygen, and hydrogen, respectively. The film is characterized by a substantial lack of bonding between silicon atoms and oxygen atoms, and has a thickness of less than approximately 600 Å which is selected to produce destructive interference between incident and reflected light at a selected DUV wavelength.

Abstract: A CMOS memory device includes source and drain regions diffused into a substrate, a polysilicon gate structure formed over a channel region located between the first and second diffusion regions, and a pre-metal dielectric structure formed over the polysilicon gate structure. The pre-metal dielectric structure is a triple layer structure including a lower Borophosphosilicate glass (BPSG) layer formed over the polysilicon gate structure, a Nitride layer formed on the lower BPSG layer, and an upper dielectric layer (e.g., BPSG or USG) formed on the Nitride layer. The Phosphorous concentration in the lower BPSG layer is greater than the Phosphorous concentration in the upper dielectric layer, thereby providing retention protection for the underlying memory structures while facilitating optimal chemical mechanical polishing (CMP) planarization characteristics.

Abstract: A method for ion implantation of high dielectric constant materials with dopants to improve sidewall stoichiometry is disclosed. Particularly, the invention relates to ion implantation of (Ba,Sr)TiO3(BST) with Ti dopants. The invention also relates to varying the ion implantation angle of the dopant to uniformly dope the high dielectric constant materials when they have been fabricated over a stepped structure. Additionally, the invention relates to forming a capping layer over a horizontal portion of the BST film to reduce excess dopant from being implanted into the horizontal section of the BST film. The invention also relates to integrated circuits having a thin film high dielectric material with improved sidewall stoichiometry used as an insulating layer in a capacitor structure.

Abstract: The present invention provides a method of fabricating capacitor dielectric layer. A bottom electrode covered by a native oxide layer on a chip is provided. The chip is disposed into a low pressure furnace. A mixture of dichlorosilane and ammonia is introduced into the low pressure furnace to form a nitride layer on the native oxide layer. In the same low pressure furnace, nitrogen monoxide or nitric oxygen is infused to form an oxynitride layer on the nitride layer.

Abstract: A ferroelectric Pb5Ge3O11 (PGO) thin film is provided with a metal organic vapor deposition (MOCVD) process and RTP (Rapid Thermal Process) annealing techniques. The PGO film is substantially crystallization with c-axis orientation at temperature between 450 and 650° C. The PGO film has an average grain size of about 0.5 microns, with a deviation in grain size uniformity of less than 10%. Good ferroelectric properties are obtained for a 150 nm thick film with Ir electrodes. The films also show fatigue-free characteristics: no fatigue was observed up to 1×109 switching cycles. The leakage currents increase with increasing applied voltage, and are about 3.6×10−7 A/cm2 at 100 kV/cm. The dielectric constant shows a behavior similar to most ferroelectric materials, with a maximum dielectric constant of about 45. These high quality MOCVD Pb5Ge3O11 films can be used for high density single transistor ferroelectric memory applications because of the homogeneity of the PGO film grain size.

Abstract: A film of low k dielectric material formed on a semiconductor substrate is treated to inhibit cracking of the film of low k dielectric material during subsequent exposure of the film of low k dielectric material to elevated temperatures by implanting the film of low k dielectric material with hydrogen ions by applying a negative DC bias to the semiconductor substrate in the presence of a plasma of hydrogen ions. The semiconductor substrate is mounted on an electrically conductive substrate support in a reactor and the negative DC bias is applied to the semiconductor substrate by connecting the electrically conductive substrate support to a source of negative DC bias while hydrogen ions are generated by the plasma in the reactor to thereby cause the hydrogen ions to implant into the film of low k dielectric material on the semiconductor substrate.

Abstract: A boro-silicate-glass (BSG) is deposited on a silicon substrate coated with a bottom SiO2 and an overlying Si3N4 layer by LPCVD using an O3/TEB/TEOS mixture at low pressure (less than 300 mTorr), low temperature (less than 500° C.) and a TEB flow which is adjusted to have a boron concentration in the BSG layer less than 10% (in weight). The BSG material deposited that way has been found to be resistant to aggressive silicon dry etch chemistries and is easily and rapidly etched in standard BSG etchants. However, very high etch rates are obtained with a HF/ethylene glycol wet chemistry. The disclosed BSG deposition method finds a valuable application in the fabrication of the buried plate in deep trench cell capacitors because no undercuts are produced in the bottom SiO2 layer sidewall exposed in the trench during the BSG layer removal.

Abstract: A process for manufacturing a silicon semiconductor device having a reduced surface recombination velocity of charge carriers within a silicon wafer includes forming a plurality of semiconductor zones in the surface; reducing surface recombination velocity of charge carriers within the silicon wafer by maintaining temperature below 100° C. while sequentially performing the steps of cleaning the surface to remove oxide; drying the surface by blowing a non-oxidizing gas thereon; directly applying a layer of lacquer onto the surface at a temperature below 100° C.; and drying the layer of lacquer at a temperature below 100° C. to generate an electrically non-conducting layer and reduce the surface recombination velocity of charge carriers within the silicon wafer in which the layer of lacquer contains halogen in a concentration of more than 0.1 volume %; and forming at least one conducting structure on the surface of the layer of lacquer.

Abstract: An insulating layer having a BPSG layer, a semiconductor device and methods for fabricating them. After preparing an oxidizing atmosphere using an oxygen gas, a first seed layer is formed with a tetraethylorthosilicate (TEOS) and the oxygen gas. Thereafter, a second seed layer, used to form an insulating layer capable of controlling an amount of a boron, is formed by means of using a triethylborate (TEB), the TEOS and the oxygen gas. Then, the insulating layer having a BPSG layer is formed using the TEB, a triethylphosphate, the TEOS and an ozone gas. About 5.25 to 5.75% by weight of the boron and about 2.75 to 4.25% by weight of the phosphorous are added to the insulating layer.

Abstract: A semiconductor device superior in reliability and suitable for microminiaturization is provided. An organic SOG film is formed on a silicon oxide film. Boron ions are implanted into the organic SOG film. By introducing boron ions into the organic SOG film, the organic components in the film are decomposed. Also, the moisture and hydroxyl group included in the film are reduced. After a metal interconnection is embedded in a modified SOG film by the Damascene method, a modified SOG film is formed thereon. Then, contact holes are formed. After a contact hole interconnection is embedded in the contact holes, a modified SOG film and an upper metal interconnection are formed by the Damascene method.

Abstract: A semiconductor device includes a substrate and wirings located on the substrate. A passivation film including a first insulating film containing an impurity is located on the wirings. The first insulating film is formed from silicon oxide film materials containing greater than one percent carbon.

Abstract: A method for forming through a dielectric layer a trench contiguous with a via. There is first provided a substrate having a contact region formed therein. There is then formed upon the substrate a blanket first dielectric layer. There is then formed upon the blanket first dielectric layer a blanket etch stop layer. There is then formed upon the blanket etch stop layer a patterned first photoresist layer which defines a location of a via to be formed through the blanket etch stop layer and the blanket first dielectric layer to access the contact region. There is then etched while employing a first etch method the blanket etch stop layer to form a patterned etch stop layer.

Abstract: A siloxan polymer insulation film has a dielectric constant of 3.1 or lower and has —SiR2O— repeating structural units with a C atom concentration of 20% or less. The siloxan polymer also has high thermal stability and high humidity-resistance. The siloxan polymer is formed by directly vaporizing a silicon-containing hydrocarbon compound of the formula Si&agr;O&agr;−1R2&agr;−&bgr;+2(OCnH2n+1)&bgr; wherein &agr; is an integer of 1-3, &bgr; is 2, n is an integer of 1-3, and R is C1-6 hydrocarbon attached to Si, and then introducing the vaporized compound with an oxidizing agent to the reaction chamber of the plasma CVD apparatus. The residence time of the source gas is lengthened by reducing the total flow of the reaction gas, in such a way as to form a siloxan polymer film having a micropore porous structure with low dielectric constant.

Abstract: A method of forming an arsenic doped oxide layer in a process chamber is disclosed. The method comprises the steps of: setting the process chamber to a temperature of approximately 400-500° C. and a pressure of about 40-250 torr; flowing tetraethylorthosilicate (TEOS) into the process chamber; flowing triethylarsenate (TEAS or TEASAT) into the process chamber; and flowing ozone into the process chamber.

Abstract: The present invention provides a method of depositing an amorphous fluorocarbon film using a high bias power applied to the substrate on which the material is deposited. The invention contemplates flowing a carbon precursor at rate and at a power level so that equal same molar ratios of a carbon source is available to bind the fragmented fluorine in the film thereby improving film quality while also enabling improved gap fill performance. The invention further provides for improved adhesion of the amorphous fluorocarbon film to metal surfaces by first depositing a metal or TiN adhesion layer on the metal surfaces and then stuffing the surface of the deposited adhesion layer with nitrogen. Adhesion is further improved by coating the chamber walls with silicon nitride or silicon oxynitride.

Abstract: Methods of forming dielectric layers and methods of forming capacitors are described. In one embodiment, a substrate is placed within a chemical vapor deposition reactor. In the presence of activated fluorine, a dielectric layer is chemical vapor deposited over the substrate and comprises fluorine from the activated fluorine. In another embodiment, a fluorine-comprising material is formed over at least a portion of an internal surface of the reactor. Subsequently, a dielectric layer is chemical vapor deposited over the substrate. During deposition, at least some of the fluorine-comprising material is dislodged from the surface portion and incorporated in the dielectric layer. In another embodiment, the internal surface of the reactor is treated with a gas plasma generated from a source gas comprising fluorine, sufficient to leave some residual fluorine thereover.

Abstract: A method for manufacturing a semiconductor device comprises forming a silicon nitride film, a BPSG film, and a SOG silicon oxide film containing boron or phosphorous on a transistor element, thermally treating the resultant wafer in a pressurized steam ambient, and thermally treating the wafer in an inactive gas ambient. The first thermal treatment causes hydrolysis of the SOG film to form a gel state of the SOG film, whereas the second thermal treatment hardens the SOG film by removing H2O content in the SOG film. The phosphorous or boron in the SOG film weakens the bonds in —Si—O—Si— chains in the SOG film to assist the separation of the —Si—O—Si— chains and the planarization of the SOG film.

Abstract: Method for fabrication of on-chip inductors and related structure are disclosed. According to one embodiment, inductors are formed by patterning conductors within a certain dielectric layer in a semiconductor die. Thereafter, the entire dielectric layer in the semiconductor die is subjected to a blanket implantation or sputtering of high permeability material. According to another embodiment, a first area in a semiconductor die is covered, for example, with photoresist. A second area in the semiconductor die includes a patterned conductor which is to be used as an inductor. The patterned conductor is also covered, for example, with photoresist. The second area, excluding the covered patterned conductor is subjected to implantation or sputtering of high permeability material. According to yet another embodiment, a first area of a semiconductor die is covered, for example, with photoresist. A second area in the semiconductor area includes a patterned conductor which is to be used as an inductor.

Abstract: Certain embodiments of the present invention relate to a semiconductor device that has a pad section having an excellent coherency with an interlayer dielectric layer, and a method for manufacturing the same. A semiconductor device 1000 has a pad layer 30A formed over an interlayer dielectric layer 20. The interlayer dielectric layer 20 includes at least a first silicon oxide layer 20b that is formed by a polycondensation reaction of a silicon compound and hydrogen peroxide, and a second silicon oxide layer 20c formed over the first silicon oxide layer and containing an impurity. The pad section 30A includes a wetting layer 32, an alloy layer 34 and a metal wiring layer 37.

Abstract: A method of forming a fluorinated silicon oxide layer or an FSG film having a dielectric constant less than 3.2 is disclosed. The method includes introducing a fluorine-rich gas into a reacting chamber, introducing an oxygen-rich gas into the reacting chamber, creating a plasma environment in the reacting chamber to deposit the FSG film, and adjusting the flow rate of the oxygen-rich gas till the ratio of the flow rate of the oxygen-rich gas to the total flow rate of the fluorine-rich gas and silicon-rich gas is less than or equal to a pre-selected value to form the FSG film. The refraction index (RI) of the fluorinated silicon oxide layer must be greater than or equal to 1.46.

Abstract: A method for forming BPSG layers over PECVD silicon oxide layers by atmospheric chemical vapor deposition using ozone and TEOS is described. The method prevents the formation of voids in deep depressions such as are found between metallization lines or closely spaced polysilicon structures in flash memory integrated circuits. The method deposits the BPSG layer at ozone/TEOS flow rate ratio of 12:1 or greater. The voids are caused by excessive shrinkage of the BPSG which produces high stresses in the depressions during planarization reflow causing the BPSG to become detached from the underlying silicon oxide. The voids are measured as line defects in a double polysilicon flash memory circuit. The high ozone/TEOS ratio increases the density of the as-deposited BPSG layer which in turn produces reduced shrinkage of the layer during the subsequent planarization reflow. A correlation is found between BPSG shrinkage and line yield.

Abstract: The present invention comprises a method for preventing particle formation in a substrate overlying a DARC coating. The method comprising providing a semiconductor construct. A DARC coating is deposited on the construct with a plasma that comprises a silcon-based compound and N2O. The DARC coating is exposed to an atmosphere that effectively prevents a formation of defects in the substrate layer. The exposed DARC coating is overlayed with the substrate.

Abstract: A method of fabricating a capacitor. An isolation layer is formed on a substrate. An ion implantation step is performed. The isolation layer is patterned to form an opening in the isolation layer. The opening exposes a portion of the substrate. A patterned conductive layer is formed on the isolation layer to fill the opening. A hemispherical grained silicon layer is performed on the conductive layer. In addition, the step order of the ion implantation step can be changed. The ion implantation can also be performed after the opening is formed.

Abstract: In one aspect, the invention includes a method of forming an insulating material comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising a Si, F and ozone within the reaction chamber; and c) depositing an insulating material comprising fluorine, silicon and oxygen onto the substrate from the reactants. In another aspect, the invention includes a method of forming a boron-doped silicon oxide having Si—F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising Triethoxy fluorosilane, a boron-containing precursor, and ozone within the reaction chamber; and c) depositing a boron-doped silicon oxide having Si—F bonds onto the substrate from the reactants.

Abstract: A high density plasma chemical vapor deposition apparatus includes a vacuum chamber provided with an inlet and an outlet for a reaction gas; a suscepter positioned within the vacuum chamber to mount a wafer thereon, the suscepter having a wafer chuck at its upper surface to prevent the wafer from moving horizontally; a coil antenna surrounding the upper outer wall of the vacuum chamber; an RF generator for applying an RF power to the coil antenna; and a heating unit for heating the wafer mounted on the suscepter. Since the wafer 111 is heated in advance by the wafer heating unit, which is not proposed in the conventional HDP-CVD apparatus, the previously sputtered insulation material is restrained from re-depositing. Therefore, even though a gap has a high aspect ratio, it can be filled without a void.

Abstract: A semiconductor device that allows improvement in adhesion between insulation films having a 2-layered structure together with improvement of planarization and film characteristics, and a fabrication method thereof are obtained. In the fabrication method of the semiconductor device, an insulation film of a 2-layered structure having at least an upper layer and a lower layer is formed on a semiconductor substrate. Then, impurities are introduced into the upper insulation film under a condition where impurities arrive at least at the interface between the upper insulation film and the lower insulation film. By improving the adhesion between the upper and lower insulation films, the upper insulation film does not easily peel off.

Abstract: Reflection of incident optical radiation from a highly reflective metal layer (12), such as aluminum, copper or titanium, into a photoresist layer (16) is reduced by interposing a layer of silicon oxynitride (14) between the metal and photoresist layers. The silicon oxynitride layer (14) is pre-treated with an oxidizing plasma to deplete surface nitrogen and condition the silicon oxynitride layer (14) to be more compatible with deep ultraviolet photoresists. The silicon oxynitride layer (14) further serves as an etch stop in the formation of interconnect openings (40), such as vias, contacts and trenches. The interconnect opening (40) is filled with a second metallization layer to achieve multi-layer electrical interconnection.

Abstract: A method for forming through a dielectric layer a trench contiguous with a via. There is provided a substrate having a contact region formed therein. There is then formed upon the substrate a patterned first dielectric layer defining a via accessing the contact region, where the patterned first dielectric layer is formed of a first dielectric material which is not susceptible to etching with an oxygen containing plasma. There is then formed completely covering the patterned first dielectric layer and filling the via a the blanket second dielectric layer formed of a second dielectric material which is susceptible to etching within the oxygen containing plasma. There is then formed upon the blanket second dielectric layer a blanket hard mask layer formed from a hard mask material which is not susceptible to etching within the oxygen containing plasma.

Abstract: A method is provided for forming fluorosilicate glass (FSG) layers that serve as inter-metal dielectric (IMD) layers in a semiconductor wafer with a high moisture-resistant capability. In particular, the method can nonetheless allow the resultant semiconductor circuit to have a low RC delay. The method includes the step of subjecting the FSG layer to a plasma treatment so as to form a moisture-resistant layer over the FSG layer. In the plasma treatment, the ionized gas of ammonia is used as the plasma. As a result of this plasma treatment, a layer of nitrogen-containing compound having a high moisture-resistant property is formed over the FSG layer, which serves as a moisture-resistant layer that can protect the FSG layer from absorbing moistures.

Abstract: An interlayer dielectric for a damascene structure includes a first etch stop layer formed on a substrate. A first interlayer dielectric layer containing fluorine is formed on the first etch stop layer by deposition. A second etch stop layer is formed on the first interlayer dielectric layer. A second interlayer dielectric layer containing fluorine is formed on the second etch stop layer by deposition. The first and second interlayer dielectric layers and the first and second etch stop layers are etched to form at least one trench and at least one via. The at least one trench and the at least one via are treated with an H2/N2 plasma in-situ, wherein a fluorine-depleted region in the first and second interlayer dielectric layers is formed, and wherein a nitrided region is formed adjacent the fluorine-depleted region, with the nitrided region corresponding to a side surface of the at least one trench and the at least one via.

Abstract: A thin film transistor including a gate, a source, and a drain is formed on a substrate. An insulating film containing H2O is formed on the thin film transistor. For example, spin-on glass (SOG) containing H2O may be used. H2O contained in the insulating film is diffused through the thin film transistor by performing thermal processing on the insulating film. Trapping centers in the polysilicon may therefore be reduced.

Abstract: In a semiconductor device having a multilayer metallization structure using SiOF film as an interlayer insulating film, with respect to the interlayer insulating film, the fluorine concentration of SiOF films (11, 16) in a wiring gap portion in the same layer wiring is set to be higher than the fluorine concentration of SiOF films (12, 17) between the upper and lower layer wirings (8, 15; 15, 20).

Abstract: A method of fabricating an improved spacer comprising the steps of providing a semiconductor substrate that has a gate already formed thereon. A PNO spacer is formed on a sidewall of the gate. The method of forming the PNO spacer comprises first forming a PNO layer on the conductive layer and the semiconductor, and performing an anisotropic etching step on the PNO layer to form the PNO spacer. The step of forming the PNO layer includes chemical vapor deposition (CVD) using PH3, O2, NH3 and N2 as reagents. The step of etching the PNO layer includes plasma etching using CFX+O2 as plasma source. The material of the PNO spacer is a chemical compound PXNYOZ containing phosphorous (P), nitrogen (N) and oxygen (O) and does not contain silicon. Therefore, the PNO spacer can avoid erosion during etching and does not react with Ti during the Salicide process.

Abstract: The invention includes semiconductor processing methods, including trench isolation. In one implementation, an oxide layer is deposited over a substrate. The deposited oxide layer is exposed to a chlorine containing gas effective to getter metals outwardly therefrom. In one implementation, a dielectric layer, for example silicon dioxide, is plasma enhanced chemical vapor deposited over a substrate within a chamber comprising an internal metal surface under conditions effective to incorporate metal from the chamber surface within the dielectric layer. The dielectric layer is then exposed to a chlorine containing gas effective to getter at least some of said metal outwardly therefrom. In one implementation, a trench isolation method comprises forming a series of isolation trenches into a semiconductive substrate. Silicon dioxide is chemical vapor deposited to within the trenches, with the silicon dioxide comprising metal impurity therein.

Abstract: A layer of doped or undoped germanosilicate glass is formed on a substrate and the layer of germanosilicate glass is thermally treated in steam to remove germanium from the germanosilicate glass, and thereby raise the reflow temperature of the germanosilicate glass so treated. The layer of germanosilicate glass on the substrate may be a nonplanar layer of germanosilicate glass. When thermally treating the nonplanar layer of germanosilicate glass in steam, the layer of germanosilicate glass may be planarized simultaneously with the removal of germanium from the planarized germanosilicate glass. This process may be repeated to create a hierarchy of reflowed glass where each underlying layer reflows at a higher temperature than the next deposited glass layer. The steam thermal treatment step may be preceded by a thermal pretreatment of the layer of germanosilicate glass in at least one of a noble gas and nitrogen gas, to reflow the layer of germanosilicate glass.