Abstract: The method for forming an insulating film having a low dielectric constant, which is suitable for intermetal insulating film applications, by plasma enhanced chemical vapor deposition (PECVD) includes the step of supplying a first source gas containing fluorine and carbon to a dual-frequency, high density plasma reactor. The method also includes the step of supplying a second source gas containing silicon dioxide to the reactor. In this manner a fluorocarbon/silicon dioxide film is formed on a substrate in the reactor.

Abstract: Disclosed is a method of manufacturing a semiconductor device aimed at improving reliability of wiring, more particularly, of a via hole when a silicon oxide film formed by a high density plasma CVD process is used as an inter-level dielectric film in an integrated circuit having a multi-level wiring structure. When the multi-level wiring structure is formed on a semiconductor substrate, after underlying wiring is formed, a silicon oxide film is formed on the entire surface of the substrate by a high density plasma CVD process, and heat treated in inert gas or oxygen atmosphere at a temperature of 300.degree. C. or more but 500.degree. C. or less for 10 minutes or more. Excess hygrogen incorporated in the silicon oxide during the CVD process is removed by the above heat treatment. Subsequently, via holes are opened, and upper wiring is formed.

Abstract: A method of making an inter-metal oxide layer over a patterned metallization layer of a substrate, and the resulting structure having the inter-metal oxide layer are provided. The method includes depositing a fluorine doped high density plasma (HDP) oxide layer over the patterned metallization layer. The fluorine doped HDP oxide layer is configured to evenly deposit in high aspect ratio regions of the patterned metallization layer. The method also includes depositing a plasma enhanced chemical vapor deposition (PECVD) oxide layer over the fluorine doped HDP oxide layer. The PECVD oxide layer is doped with a phosphorous material. A CMP operation is then performed over the PECVD oxide layer to remove topographical oxide variations, such that the CMP operation will be configured to preferably leave at least a coating of the PECVD oxide layer over the HDP oxide layer.

Abstract: A method of rapid thermal annealing (RTA) a TEOS oxide layer 50 that underlies a silicon nitride stop layer 60. The RTA of the TEOS-Oxide ILD layer 50 prevents the nitride stop layer 60 and oxide ILD layer 50 from peeling in subsequent thermal steps. The process comprises providing a semiconductor structure 10 with an uneven surface; forming an interlevel dielectric layer 50 composed of PE-TEOS oxide over the structure 10; rapid thermal annealing (RTA) the third interlevel dielectric layer 50 at a temperature between about 850 and 1015.degree. C. for a time between about 10 and 50 seconds; depositing a silicon nitride layer 60 over the third interlevel dielectric layer 50; and planarizing the silicon nitride layer 60 and the third interlevel dielectric layer 50.

Abstract: An improved field effect transistor (FET) structure is disclosed. It comprises a first insulator layer containing at least one primary level stud extending through the layer; an undoped cap oxide layer disposed over the insulator layer and abutting the upper region of each stud; a primary level thin film transistor (TFT) disposed over the undoped cap oxide layer; and a planarized oxide layer disposed over the TFT. Multiple TFT's can be stacked vertically, and connected to other levels of studs and metal interconnection layers. Another embodiment of the invention includes the use of a protective interfacial cap over the surface of tungsten-type studs. The FET structure can serve as a component of a static random access memory (SRAM) cell. Related processes are also disclosed.

Abstract: The present invention is directed toward the formation of implanted thermally and electrically conductive structures in a dielectric. An electrically conductive structure, such as an interconnect, is formed through ion implantation into several levels within a dielectric layer to penetrate into an electrically conductive region beneath the dielectric layer, such as a semiconductor substrate. Ion implantation continues in discreet, overlapping implantations of the ions from the electrical conductive region up to the top of the dielectric layer so as to form a continuous interconnect. Structural qualities achieved by the method of the present invention include a low interconnect-conductive region resistivity and a low thermal-cycle stress between the interconnect and the dielectric layer in which the interconnect has been implanted.

Abstract: An apparatus and methods for forming a dielectric layer, such as PSG, that exhibits low moisture content, good gap fill capability, good gettering capability, and compatibility with planarization techniques. The PSG film deposited using the apparatus and methods of the present invention are particularly suitable for use as a PMD layer. According to one embodiment, the present invention provides a process for depositing a film on a substrate disposed on a pedestal in a processing chamber. The process includes introducing a process gas into said processing chamber, where the process gas includes SiH.sub.4, PH.sub.3, O.sub.2, and argon. The process also includes controlling the temperature of the pedestal to between about 400-650.degree. C. during a first time period, maintaining a pressure ranging between about 1-10 millitorr in the processing chamber during the first time period.

Abstract: A process for the low temperature deposition of a thin film of borophosphosilicate glass ("BPSG") for use in semiconductor devices, such as DRAMs, is disclosed. The process includes utilizing R--OH groups as reagents to provide additional --OH groups so that an intermediate {Si(OH).sub.4 }.sub.n is formed having superior reflow properties so that the annealing and reflow steps may occur at temperatures less than 750.degree. C., which is the current processing temperature.

Abstract: A semiconductor device and method of forming a patterned conductive layer on a semiconductor substrate are provided so as to prevent fluorine substance outflow from a fluorinated silicate glass (FSG) layer thereon and simultaneously so as to suppress back reflection of light waves into a photoresist layer during photolithographic processing. The substrate is coated in turn with a conductive layer, a dielectric (e.g., silicon dioxide) liner, a FSG layer, a silicon oxynitride layer preventing fluorine substance outflow therethrough from the FSG layer and also forming an antireflective coating (ARC), and a photoresist layer. The photoresist layer is exposed and developed to uncover pattern portions of the underlying silicon oxynitride layer. The uncovered pattern portions of the silicon oxynitride ARC layer and corresponding underlying portions of the FSG layer and dielectric liner are then removed, e.g., by a single dry etching step, to expose pattern portions of the conductive layer for metallization.

Abstract: A semiconductor device includes a substrate, an insulation film formed above the substrate and containing silicon-fluorine bonds, and a titanium-based metal wiring layer formed on the insulation film, the titanium-based metal wiring layer containing fluorine which is diffused from the insulation film and has a fluorine concentration of less than 1.times.10.sup.20 atoms/cm.sup.3.

Abstract: A permanent curable photosensitive liquid dielectric polymer composition is disclosed for making copper printed circuit boards having at least one photosensitive dielectric polymer layer containing vias and circuitry thereon wherein the polymer layer has enhanced copper to dielectric adhesion. The dielectric composition preferably comprises an acrylated epoxy and a metal adhesion effective amount of amorphous silica. Printed circuit boards made using the photodefinable dielectric polymer and a method for making the printed circuit boards are also disclosed. A twice performed permanganate etching process for texturing the dielectric surface is also preferably used to further enhance the copper to dielectric adhesion.

Abstract: A method for etching metal which can increase the metal-to-photoresist etching selectivity of a metal layer aimed to be etched with respect to a photoresist layer overlaying the metal layer. The method includes a first step of forming a cap oxide layer over the metal layer; a second step of forming a photoresist layer with a desired pattern over the cap oxide layer; a third step of conducting an ion implantation process on the photoresist layer; and a final step of conducting an etching process on the semiconductor wafer by using the photoresist layer as a mask so as to etch away exposed portions of the metal layer that are uncovered by the photoresist layer. Through experiments, it is found that the invention provides a significantly improved etching selectivity over the prior art.

Abstract: An insulating layer may be fabricated on a microelectronic substrate by spinning a layer of spin-on-glass (SOG) on a microelectronic substrate and curing the SOG layer by irradiating the SOG layer with an electronic beam. Irradiating may take place simultaneously with heating the substrate to a temperature below about 500.degree. C. An underlying and/or overlying capping layer may also be provided. Alternatively, rather than irradiating the SOG layer, an overlying capping layer may be irradiated.

Abstract: The present invention discloses a method of doping and preventing silicide formation in selective areas of a polysilicon gate in MOS, PMOS, NMOS or CMOS manufacturing technologies. The process includes the steps of: depositing a non-conformal dopant containing layer on the top surface of the body and the top surface of the polysilicon gate; removing a portion of the non-conformal dopant containing layer to expose the top surface of the polysilicon gate; and heating to diffuse dopant from the dopant containing layer. Silicidation is then provided by depositing a metal layer and annealing the metal layer. As a first alternative method, the heating and removing step may be reversed. As a second alternative method, after removal of the non-conformal layer, a metal layer can be deposited followed by a combination anneal of the metal layer and non-conformal dopant containing layer.

Abstract: A method of manufacturing the semiconductor device comprises elements described below;(a) forming a wiring pattern on an insulating film on a semiconductor substrate,(b) forming a reflow SiO.sub.2 film having a reflow shape by introducing SiH.sub.4 gas and H.sub.2 O.sub.2 gas into a reaction chamber which accommodates said semiconductor substrate and mutually reacting the SiH.sub.4 and H.sub.2 O.sub.2 gases in a temperature range of about -10.degree. C. to about +10.degree. C. in a vacuum of about 665 Pa or below,(c) plasma treating a surface of said reflow SiO.sub.2 film by introducing a gas including fluorine into said reaction chamber and discharging plasma in said reaction chamber, and(d) heat treating said semiconductor substrate.

Abstract: The present invention provides systems, methods and apparatus for high temperature (at least about 500-800.degree. C.) processing of semiconductor wafers. The systems, methods and apparatus of the present invention allow multiple process steps to be performed in situ in the same chamber to reduce total processing time and to ensure high quality processing for high aspect ratio devices. Performing multiple process steps in the same chamber also increases the control of the process parameters and reduces device damage. In particular, the present invention can provide high temperature deposition, heating and efficient cleaning for forming dielectric films having thickness uniformity, good gap fill capability, high density, low moisture, and other desired characteristics.

Abstract: A method of forming a contact via includes forming a wiring, a first insulator layer, and a spin-on glass layer, respectively, over a semiconductor substrate. Fluorine ions are implanted into the spin-on glass layer. A second insulator layer is formed over the spin-on glass layer. The wiring is exposed by patterning the second insulator layer, the spin-on glass layer, and the first insulator layer, respectively.

Abstract: The present invention is a liner and/or barrier layer that will encapsulate the low k materials and act as a diffusion barrier between the low k material and the surrounding metal layers. As the temperatures of the processing sequence increase the liner and/or barrier layer will decrease the diffusion of fluorine from the low k material into the surrounding metal layers. Thus, the present invention will reduce potential corrosion problems of the metal layers.

Abstract: A semiconductor device formed in a semiconductor substrate with a low hydrogen content barrier layer formed over the semiconductor device. The barrier layer is implanted with phosphorus ions. The semiconductor device may have a hydrogen getter layer formed under the barrier layer. The barrier layer is a high temperature PECVD nitride film, a high temperature PECVD oxynitride film or a high temperature LPCVD nitride film. The hydrogen getter layer is P-doped film having a thickness between 1000 and 2000 Angstroms and is a PSG, BPSG, PTEOS deposited oxide film, or BPTEOS deposited oxide film. Interconnects are made by a tungsten damascene process.

Abstract: The present invention relates to a dual damascene structure and its manufacturing method. The invention uses two implanting step to form two stop layers. It uses the stop layers to perform an anisotropic etching step so as to form a via and trench. Finally, a conductive layer is filled into the via and trench followed by the completion of forming of the dual damascene structure. The invention controls the etching stop. Another advantage of the present invention is that of using the spacer as the trench mask instead of the multi-mask. Therefore, misalignment is prevented in the present invention.

Abstract: A polycrystalline silicon film is formed on the surface of a semiconductor substrate. An oxide film having a first impurity concentration is formed to cover the polycrystalline silicon film. A polycrystalline silicon film and a refractory metal silicide are formed on the surface of the oxide film having the first impurity concentration. An oxide film having a second impurity concentration higher than the first impurity concentration is formed to cover the polycrystalline silicon film and the refractory metal silicide. The third conductive layer is formed on the surface of the oxide film having the second impurity concentration.

Abstract: A substrate for forming a compound semiconductor device is placed in a reaction chamber. An MOCVD method or a GS-MBE method is used to grow compound semiconductor layers on the substrate. The grown layers include, for example, a GaN buffer layer, an n-GaN layer, an InGaN active layer, a p-AlGaN layer, and a p.sup.+ -GaN contact layer. After the growth of the layers, the substrate is kept in the reaction chamber, and a passivation film of, for example, SiNx, SiO2, or SiON is formed on top of the grown layers according to a CVD or GS-MBE method. Since the top of the grown layers is not exposed to air outside the reaction chamber, no oxidization or contamination occurs on the top of the grown layers. The compound semiconductor device is manufactured through simpler processes compared with a prior art that needs separate apparatuses for growing and forming the layers and passivation film.

Abstract: An interlevel dielectric and a method for making same wherein boron is introduced into the dielectric though an implantation process. During the implantation process, either the boron-10 or the boron-11 boron isotope may be selected and introduced into the dielectric. Boron is introduced to make the dielectric flow at lower temperatures. Selectively implanting boron-10 or boron-11 during implantation, as opposed to buying boron comprising a specific boron isotope from a supplier and introducing boron during CVD, lowers the production costs. Furthermore, by introducing boron into the dielectric during the implantation process as opposed to during deposition of the dielectric during a CVD process, the dielectric layer is free of boron bumps. Boron-bearing dielectrics can be made to made to flow at lower temperatures than dielectrics which do not contain boron.

Abstract: Interconnects for integrated circuit substrates are formed by forming a diffusion-barrier film on an integrated circuit substrate and amorphizing the diffusion-barrier film to create an amorphous diffusion-barrier film. A copper film is then formed on the amorphous diffusion-barrier film. Amorphizing may be performed by implanting ions into the diffusion-barrier film. The diffusion-barrier film can include Mo, W, Ti, Wn, TiW, TiN and the ions may be boron, nitrogen and silicon ions. Interconnect structures according to the invention include an amorphous conductive diffusion-barrier film on an integrated circuit substrate and a copper film on the amorphous conductive diffusion-barrier film. The amorphous conductive diffusion-barrier film preferably contains ions therein. The amorphous conductive diffusion-barrier film and the ions may be selected from materials as described above.

Abstract: A polysilicon diffusion doping method which employs a deposited dopant-rich oxide layer with a highly uniform distribution of dopant atoms and thickness. Polysilicon layers 1,500 angstroms thick have been doped, achieving average resistance values of 60 ohms and non-uniformity values of 5 percent. Resistance values were measured using the four-point probe method with probe spacings of 0.10 cm. After a polysilicon layer has been formed upon a surface of a silicon wafer, a dopant-rich oxide layer is deposited upon the polysilicon layer at reduced pressure. The dopant-rich oxide layer is deposited, and serves as a source of dopant atoms during the subsequent diffusion process. The dopant-rich oxide layer is a phosphosilicate glass (PSG) including phosphorus pentoxide (P.sub.2 O.sub.5) and phosphorus trioxide (P.sub.2 O.sub.3) and deposited using a PECVD technique.

Abstract: A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. An anti-reflective coating helps protect against reflective gate notching. A variety of silicided and non-silicided) structures may be formed.

Abstract: A method for forming an interlayer insulating film, which involves a first oxide film deposition, a GeBPSG film deposition, a thermal treatment and a second oxide film deposition all being carried out in a continuous manner in an LPCVD device. In accordance with this method, it is possible to form an interlayer insulating film having a superior planarization characteristic in a single pass. The deposition and thermal treatment of the interlayer insulating film are carried out in a continuous manner in a single processing device. Accordingly, it is possible to effectively suppress the degradation of the GeBPSG film caused by a moisture absorption. Since a protective oxide film is deposited over the GeBPSG film in a continuous manner after the thermal treatment of the GeBPSG film, the degradation of the GeBPSG film caused by the moisture absorption can be affectively suppressed.

Abstract: A process for doping a region in a substrate from a solid phase source. An inert gas is bubbled through a dopant containing ester and supplied to a chamber along with the gases used to form a silicon dioxide layer such as a TEOS formed layer. The flow of the inert gas can be modulated to grade the dopant concentration in the silicon dioxide layer. The dopant is diffused from the silicon dioxide layer into the substrate to form, for instance, source and drain regions in field-effect transistors.

Abstract: The invention provides a method for producing wiring and contacts in an integrated circuit including the steps of forming insulated gate components on a semiconductor substrate; applying a photo-reducible dielectric layer to cover the substrate; etching holes and forming contacts; photo-reducing the dielectric to increase its conductivity; covering the resulting structure with an interconnect layer; etching the interconnect layer to define wiring in electrical contact with the contacts; and oxidizing the dielectric to reduce its conductivity.

Abstract: A semiconductor processing method of forming a contact opening includes providing a substrate having a node location to which electrical connection is to be made. A layer comprising doped silicon dioxide is formed over the node location. Thereafter, both O.sub.2 and O.sub.3 are flowed simultaneously to the substrate along with tetraethylorthosilicate to the substrate to form a continuous layer comprising undoped silicon dioxide on the layer comprising doped silicon dioxide. During the flowing, a ratio of O.sub.3 to O.sub.2 flows is increased to form an outer portion of the continuous layer comprising undoped silicon dioxide to have a higher etch rate for a selected wet etch chemistry than an inner portion of said continuous layer. A common contact opening is anisotropically dry etched into the layer comprising undoped silicon dioxide and into the layer comprising doped silicon dioxide over the node location to outwardly expose the node location.

Abstract: A method of smoothing irregularities in a surface of a semiconductor device using flowable particles which are dispersed onto the surface of the semiconductor device. The irregularities in the surface of the semiconductor device are filled with flowable particles smaller in size than the irregularities which are to be smoothed, and the particles are thereafter heated so that they flow and fill the irregularities, forming a smooth layer of flowable particle material which does not require polishing. The flowable particles may be mixed with non-flowable particles which are encapsulated in the layer of flowable particle material to form a homogeneous layer. The non-flowable particles may be augmentors which modify the properties of the layer. The particles may be dispersed with a spin-on process.

Abstract: A silicon oxide film is formed to cover an island non-monocrystalline silicon region by plasma CVD using an organic silane having ethoxy groups (e.g., TEOS) and oxygen as raw materials, while hydrogen chloride or a chlorine-containing hydrocarbon (e.g., trichloroethylene) of a fluorine-containing gas is added to the plasma CVD atmosphere, preferably in an amount of from 0.01 to 1 mol % of the atmosphere so as to reduce the alkali elements from the silicon oxide film formed and to improve the reliability of the film. Prior to forming the silicon oxide film, the silicon region may be treated in a plasma atmosphere containing oxygen and hydrogen chloride or a chlorine-containing hydrocarbon. The silicon oxide film is obtained at low temperatures and this has high reliability usable as a gate-insulating film in a semiconductor device.

Abstract: A method of manufacturing a semiconductor device comprises the steps of forming a first layer interconnect pattern overlying a substrate, forming consecutively a thin silicon oxide film and a thick silicon fluoride oxide film, selectively etching the silicon fluoride oxide film to expose a part of the silicon oxide film by using a first gas of a low fluorine content, and etching the exposed silicon oxide film by using a second gas of a high fluorine content to form a via-hole reaching the first layer interconnect pattern The silicon oxide film has a thickness from 50 to 200 nm while the silicon fluoride oxide film has a thickness of 1 .mu.m or higher. The thin silicon oxide film provides a reduced amount of an over-etch while thick silicon fluoride oxide film provides a low capacitance for the interconnect to achieve a higher operation of the LSI.

Abstract: An apparatus for producing thin film coatings and/or dopant levels on semiconductor wafers or other substrates with improved film growth uniformity (of thickness and composition) and/or dopant uniformity is provided. The apparatus is positioned in a furnace tube between the wafers and a gas inlet. The apparatus comprises a conical shaped baffle.

Abstract: The present invention provides a method of manufacturing an interlevel dielectric layer (ILD) which has reduced precipitates after an etch back of the borophosphosilicate glass (BPSG) ILD layer. A dielectric layer containing boron and phosphorous is deposited on the substrate. A reflow process is performed on the dielectric layer at a temperature in a range of between about 800.degree. and 950.degree. C. The dielectric layer is etched back using a reactive ion etch. In an important step, a surface treatment is performed on the dielectric layer thorough a plasma treatment. A plasma source gas for the surface treatment is of a gas selected from the group consisting of Ar, NO.sub.2, N.sub.2, and O.sub.2, at a temperature in a range of between about 250.degree. and 400.degree. C. at a pressure in a range of between about 1 mtorr and 5 torr, at a RF power in a range of between about 300 and 400 watts, and for a time in a range of between about 15 and 80 seconds.

Abstract: For a multilayer insulating film of a semiconductor device, the distributed quantity of carbon or fluorine is maximized at the interface between insulating films. The concentration of carbon present at the interface is 1.times.10.sup.20 atoms/cm.sup.3 or more.

Abstract: A method for forming a thin film of a silicon oxide on a silicon substrate is disclosed. An Si oxide film is formed by an ECR plasma. CVD with the use of a silicon compound gas containing fluorine, whereby the generation of particles can be suppressed to improve the quality of the device and the yield, the planarity of the Si oxide film functioning as an interlayer dielectric film or a passivation film can be improved, and the higher speed operation in a semiconductor device can be accomplished.

Abstract: A method for making a device and the device itself which utilizes a passivation layer displaying improved crack resistance is disclosed. This is accomplished through the incorporation of boron into a PSG passivation layer. The temperature of the passivation deposition may need to be kept to a temperature low enough so that the boron compound used for the boron source does not decompose prior to reacting with other reactants.

Abstract: A wafer edge seal ring structure is disclosed to provide reduced particulate contaminant generation during wafer processing of high density integrated circuits. The structure is formed by delimiting the deposition of layers at the peripheral edges of wafers. It is shown that as each layer is deposited and then essentially trimmed back from the edge of the wafer through a judicious use of mask and etching, and/or edge-bead rinsing (EBR) and later sealed by wafer edge exposure (WEE), the otherwise present abnormal growth of layers are prevented from building up into protrusions at the edge of wafer that later peel or break up to form particulate matter and fine dust. The method, which is also disclosed, teaches how each layer is recessed at appropriate distances from the wafer edge and how the whole ring structure is sealed against attacking particles.

Abstract: A method is provided for the controlled formation of voids in integrated circuit doped glass dielectric films. The film can be formed of borophosphosilica glass (BPSG) or other types of doped glass. The method involves the steps of providing a substrate on which conductors are formed, depositing a first layer of doped glass to a thickness in a predetermined ratio to the size of the space between conductors, reflowing the first doped glass layer, applying one or more additional doped glass layers to make up for any shortfall in desired total doped glass thickness, and performing a high temperature densification to smooth each additional layer. The method provides for increased integrated circuit speed by controlled formation of voids which have a low dielectric constant and therefore reduce capacitance between adjacent conductors. The method can be performed using existing doped glass deposition and reflow equipment.

Abstract: With forming an element isolation oxide layer on p-well in a thickness of 3500 .ANG., n-type MOS transistor with a gate electrode and source and drain regions are fabricated. Thereafter, an oxide layer is deposited by an atmospheric pressure chemical vapor deposition. Subsequently, with taking TEOS as material, a TEOS-BPSG layer is deposited by way of a reduced pressure chemical vapor deposition. Then, under inert atmosphere, heat treatment is performed at a temperature higher than or equal to 700.degree. C. to remove organic component in the layer. Thereafter, reflow process is performed at a temperature of approximately 900.degree. C. under nitrogen atmosphere at normal pressure. By this, the organic component in the BPSG layer formed utilizing TEOS can be removed out of the layer to improve element isolation characteristics and reduce leak current.

Abstract: An SiOF layer is formed by using as raw material an organic Si compound having Si-F bonds. Since an organic Si compound is used as raw material, an intermediate product being formed during the formation of an SiOF layer is liable to polymerize and has fluidity. Moreover, since the organic Si compound has Si-F bonds, low in bond energy, and is thus capable of easily getting only Si-F bonds separated, the SiOF layer is prevented from getting contaminated by reaction by-products and fluorine can be introduced into the SiOF layer in stable fashion. Therefore, an insulator layer, low in dielectric constant, low in hygroscopicity and excellent in step coverage, can be formed by using a low powered apparatus.

Abstract: The characteristic of semiconductor devices is satisfactorily maintained because the planarization of a dielectric film of a semiconductor device is carried out at a lower flow temperature. In the case of a silicon dioxide film being a dielectric film, a network structure is composed of atoms of silicon which serve as a main constituent, and of atoms of oxygen which serve as a sub-constituent of a matrix of the dielectric film. These oxygen atoms are replaced by non-bridging constituents such as atoms of halogen including fluorine. This breaks a bridge, via an oxygen atom, between the silicon atoms, at a position where such a replacement takes place. In consequence, the viscosity of the dielectric film falls with the flow temperature. If, for example, part of the oxygen in a BPSG film is substituted by fluorine, this allows the dielectric film to flow at a lower temperature of 850.degree. C. The short channel effects can be suppressed.