Abstract: A low-temperature pre-metal dielectric deposition process using phosphine-based chemistry in a high-density plasma chemical-vapor deposition technique. The process uses a phosphorous-doped oxide of up to 3.5 percent (wt) deposited at less than 350 degrees C. capable of filling 0.4 micron spaces between poly-silicon gates without microvoids.

Abstract: The present invention provides an apparatus (400) (500) for abating edge material from a substrate, e.g., SOI. The apparatus includes, among other elements, a housing and a rotatable member (401) coupled to the housing. The rotatable member is a susceptor, which is relatively flat for securing a substrate. A movable dispensing head (421) is coupled to the housing and is overlying the rotatable member. The movable dispensing head (421) is operable to emit a stream of directed fluid to one or more locations of the susceptor. The apparatus also includes a fluid source, which is coupled to the movable dispensing head. The fluid source provides fluid to ablate material from the substrate.

Abstract: A dual damascene manufacturing process, which is applicable to a dual damascene structure, is described. The method includes forming sequentially a first organic dielectric layer with a low dielectric constant, a thermal diffusion layer and a second organic dielectric layer with a low dielectric constant on a substrate. A first mask layer with a trench line pattern and a second mask layer with a via opening pattern are then formed on the substrate, respectively. The second organic dielectric layer with a low dielectric constant and the thermal diffusion layer are etched using the second mask layer as a hard mask layer to transfer the via opening pattern onto the thermal diffusion layer, and the second mask layer is then removed. The first and the second organic dielectric layer with a low electric constant are removed by using the first mask layer and the thermal diffusion layer as hard mask layers to form a trench line and a via opening. After that, the dual damascene structure is completed.

Abstract: A method for improving the reflow characteristics of a BPSG film. According to the method, a fluorine- or other halogen-doped BPSG layer is deposited over a substrate and reflowed using a rapid thermal pulse (RTP) method. The use of such an RTP reflow method results in superior reflow characteristics as compared to a 20-40 minute conventional furnace reflow process. The inventors discovered that reflowing FBPSG films in a conventional furnace may result in the highly mobile fluorine atoms diffusing from the film prior to completion of the anneal. Thus, the FBPSG layer loses the improved reflow characteristics provided by the incorporation of fluorine into the film. The RTP reflow reflows the film in a minimal amount of time (e.g., 10-90 seconds depending on the temperature used to reflow the layer and the degree of planarization required among other factors).

Abstract: In one aspect, the invention includes an etching process, comprising: a) providing a first material over a substrate, the first material comprising from about 2% to about 20% carbon (by weight); b) providing a second material over the first material; and c) etching the second material at a faster rate than the first material. In another aspect, the invention includes a capacitor forming method, comprising: a) forming a wordline over a substrate; b) defining a node proximate the wordline; c) forming an etch stop layer over the wordline, the etch stop layer comprising carbon; d) forming an insulative layer over the etch stop layer; e) etching through the insulative layer to the etch stop layer to form an opening through the insulative layer; and e) forming a capacitor construction comprising a storage node, dielectric layer and second electrode, at least a portion of the capacitor construction being within the opening.

Abstract: Within a method for fabricating a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a microelectronic device. There is then formed over the microelectronic device a passivating dielectric layer formed from a passivating dielectric material selected from the group consisting of fluorosilicate glass (FSG) passivating dielectric materials, atmospheric pressure chemical vapor deposited (APCVD) passivating dielectric materials, subatmospheric pressure chemical vapor deposited (SACVD) passivating dielectric materials and spin-on-glass (SOG) passivating dielectric materials to form from the microelectronic device a passivated microelectronic device. Finally, there is then annealed thermally, while employing a thermal annealing method employing an atmosphere comprising hydrogen, the passivated microelectronic device to form a stabilized passivated microelectronic device.

Abstract: A method for insulating metal conductors by spin-on-glass in inter-metal dielectric layers and devices formed by such method are disclosed. In the method, an additional step of scrubber clean is incorporated after an etch-back process on the spin-on-glass layer is conducted. Contaminating metal ions such as those of calcium is thus removed to eliminate formation of voids by such particles. The method can be easily implemented by including the additional scrubber clean step into a total wafer fabrication recipe.

Abstract: An improved method of forming an inter-metal dielectric layer on a semiconductor substrate is described. A plurality of conductive lines is formed on the substrate wherein an gap is simultaneously formed between every two conductive lines to expose a part of the substrate. A conformal first dielectric layer is formed on the plurality of conductive lines and the exposed substrate. A spin-coating material layer is formed in the gap wherein the first dielectric layer on top of the plurality of conductive lines is exposed. A plasma treatment is performed on the exposed first dielectric layer. The remaining spin-coating material layer is removed until the first dielectric layer is exposed. A second dielectric layer is formed over the first dielectric layer.

Abstract: A semiconductor device including an insulation film superior in insulation characteristic is obtained. Boron ions are introduced by ion implantation into an organic SOG film with a silicon nitride film formed on the organic SOG film. By this boron implantation, the property of the organic SOG film is modified. The moisture and hydroxyl group included in the film are greatly reduced irrespective of the amount of dose of ions. By using such a layered film of a modified SOG film and a silicon nitride film thereupon as an interlayer insulation film or a passivation film, the water resistance of a semiconductor device can be improved sufficiently.

Abstract: A method of fabricating a contact window of a semiconductor device, whereby a contact window of a semiconductor device is increased to offset any incline phenomenom and avoid unwanted increase in contact sheet resistance, comprises forming a lower conductive member on a semiconductor substrate, forming a first insulative film on the lower conductive member, the first insulative film being formed of an insulative material doped with impurities at a first level of concentration, the first insulative film having a wet etch rate that is proportional to the level of concentration of impurities, forming a second insulative film on the first insulative film, the second insulative film being formed of an insulative material doped with impurities at a second level of concentration that is lower than the first level of concentration of impurities, the second insulative film also having a wet etch rate that is proportional to the level of concentration of impurities, opening a contact window and exposing the lower condu

Abstract: A method for use with the formation of a capacitor includes providing a capacitor structure by forming a first electrode on a portion of a substrate assembly, forming a high dielectric material over at least a portion of the first electrode, and forming a second electrode over the high dielectric material. An additional layer may be formed over at least a portion of the second electrode. The portion of the substrate assembly on which the first electrode is formed and/or the layer formed over the second electrode are formed of an excess oxygen containing material.

Abstract: A protective layer in a ferroelectric integrated circuit contains small amounts of oxygen to protect ferroelectric oxide material against hydrogen degradation during the fabrication process. Typically, the protective layer is a hydrogen diffusion barrier layer formed to cover a thin film of ferroelectric oxide material. In one method, a small amount of oxygen is included in the sputter atmosphere during deposition of a hydrogen diffusion barrier or a metallized wiring layer. The oxygen forms oxides that inhibit diffusion of hydrogen towards the ferroelectric oxide material. The oxygen forms a concentration gradient so that the oxygen concentration in the interior of the protective layer is zero, and the oxygen concentration near the surfaces of the layer is about two weight percent.

Abstract: An integrated circuit (IC) fabrication method is provided for fabricating a conductive plug, such as a contact plug or a via plug, with a low junction resistance in an integrated circuit. This method is characterized by the inclusion of a preliminary doping process to form a doped region in the exposed area through the contact opening or via opening. By conventional method, the exposed area would be formed with an undesired oxide layer or laid with undesired reactant remnants after the etching process for forming the contact opening or via opening. When being subjected to a high temperature during the subsequent deposition process, the dopant atoms in the doped region diffuse into these undesired insulative matters, thereby reducing the junction resistance of the resulting contact or via plug.

Abstract: A method for annealing a contact in a doped dielectric layer without the occurrence of dopant diffusion problem by depositing a sacrificial barrier layer of oxide material in the contact opening which is capable of preventing diffusion of dopant ions into the contact opening during a high temperature reflow process for the doped dielectric layer and followed by a deposition of an electrically conductive metal into the contact opening.

Abstract: A method for forming an inter-metal dielectric layer without voids therein is described. Wiring lines are formed on a provided substrate. Each of the wiring lines comprises a protective layer thereon. A liner layer is formed over the substrate and over the wiring lines. A fluorinated silicate glass (FSG) layer is formed on the liner layer by using high density plasma chemical vapor deposition (HDPCVD). A thickness of the FSG layer is about 0.9-1 times a thickness of the wiring lines. A cap layer is formed on the FSG layer using HDPCVD. A thickness of the cap layer is about 0.2-0.3 times a thickness of the wiring lines. An oxide layer is formed on the cap layer to achieve a predetermined thickness. A part of the dielectric layer is removed to obtain a planarized surface.

Abstract: A semiconductor producing method includes the steps of: forming an SOG pre-film on a semimanufactured semiconductor device by means of spin-on-glass (SOG) process; and forming a modified SOG film by doping the SOG pre-film with at least one impurity ion selected from: inert gas ions; simple ions of Groups IIIb, IVb, Vb, VIb, VIIb, IVa and Va elements; and ions of compounds containing any one of Groups IIIb, IVb, Vb, VIb, VIIb, IVa and Va elements.

Abstract: A gas pipe system for a process reactor is described, which may be, for example, a vertical oven for depositing an As-doped SiO2 layer onto wafers. The gas pipe system has a TEAS bubbler which is connected on the input side to a carrier gas source and, on the output side, is connected via at least one heated pipe to the process reactor. Furthermore, a TEOS evaporator is provided, which is connected on the input side to a gas source and, on the output side, is connected via at least one heated pipe to the process reactor. Furthermore, a vertical oven and a method for deposition of an As-doped SiO2 layer onto wafers are described, with the gas pipe system being used in each case.

Abstract: A method is shown for manufacturing a semiconductor device in which a silicon oxide film acts as an insulating film for electrically isolating conductive layers included in the semiconductor device. An oxynitride silicon-oxide-like film is formed containing fluorine, carbon and nitrogen and having a given dielectric constant by CVD method using a source gas which contains at least silicon, nitrogen, carbon, oxygen and fluorine contributors. By controlling the ratio of nitrogen to oxygen in the source gas as used in the CVD method, the ultimate nitrogen, carbon and fluorine concentrations in the film can be controlled and hence the dielectric constant of the film so produced.

Abstract: A method for forming a titanium silicide on a silicon wafer. The method includes the steps of removing native oxide film formed on the silicon wafer; depositing a titanium thin film on the silicon wafer using standard type (low power) sputtering method; quickly heat-treating the silicon wafer on which the titanium thin film is deposited so that diffusion occurs between the titanium thin film and the silicon wafer, thereby forming the titanium silicide, and removing the titanium thin film. A degas process before the titanium deposition is proposed also to remove impurities on the wafer.

Abstract: A high-k dielectric film is provided which remains amorphous at relatively high annealing temperatures. The high-k dielectric film is a metal oxide of either Zr or Hf, doped with a trivalent metal, such as Al. Because the film resists the formation of a crystalline structure, interfaces to adjacent films have fewer irregularities. When used as a gate dielectric, the film can be made thin to support smaller transistor geometries, while the surface of the channel region can be made smooth to support high electron mobility. Also provided are CVD, sputtering, and evaporation deposition methods for the above-mentioned, trivalent metal doped high dielectric films.

Abstract: A method for use with the formation of a capacitor includes providing a capacitor structure by forming a first electrode on a portion of a substrate assembly, forming a high dielectric material over at least a portion of the first electrode, and forming a second electrode over the high dielectric material. An additional layer may be formed over at least a portion of the second electrode. The portion of the substrate assembly on which the first electrode is formed and/or the layer formed over the second electrode are formed of an excess oxygen containing material.

Abstract: An ultra-large scale integrated circuit is manufactured by using silicon-based, low dielectric constant materials which are spin-coated, dried, cured, and capped in-situ in chemical vapor deposition equipment. The low dielectric constant material is spun on, processed in chemical vapor deposition equipment, subject to chemical-mechanical polishing, and then processed by a conventional photolithographic process for depositing conductors. The material is then reprocessed for each successive layer of conductor separated by dielectric.

Abstract: A method for forming a fluorosilicate glass (FSG) layer. There is first provided a substrate. There is then formed over the substrate a fluorosilicate glass (FSG) layer. Finally, there is then removed, while employing a plasma etch method, a surface layer of the fluorosilicate glass (FSG) layer to form an etched fluorosilicate glass (FSG) layer. Within the method, the surface layer of the fluorosilicate glass (FSG) layer has a higher moisture content than the remaining etched fluorosilicate glass (FSG) layer. The method is particularly applicable for removing hydrated surface layers of chemical mechanical polish (CMP) planarized fluorosilicate glass (FSG) layers to provide non-hydrated underlying remainder layers of chemical mechanical polish (CMP) planarized fluorosilicate glass (FSG) layers which are stabilized with respect to hydrolysis involving loosely bound mobile fluorine atoms.

Abstract: A process for making flexible circuits wherein the etching of a polymeric film is accomplished by dissolving portions thereof with concentrated aqueous base using a UV-curable 100% active liquid photoresist as a mask, comprising the steps of laminating the resist on a polymeric film, exposing a pattern into the resist, developing the resist with a dilute aqueous solution until desired image is obtained, etching portions of the polymeric film not covered by the crosslinked resist with a concentrated base at a temperature of from about 50° C. to about 120° C., and then stripping the resist off the polymeric film.

Abstract: A dual damascene manufacturing method includes utilizing a low dielectric constant material to form the dielectric layers and to prevent current due to the reduced line width. An implanting step is performed on the dielectric layers to reduce the incoherence and fragility of the dielectric layers, to densify the dielectric layers and to protect the dielectric layers from damage in the subsequent processes. The present invention utilizes the hard mask layer formed over the dielectric layer to reduce the difficulty of the depositing process of the barrier layer. The openings formed within the hard mask layer are broad at the top and narrow at the bottom. so that the barrier layer is more easily deposited into the opening and the subsequent deposition step of the conductive material layer is easily performed. Moreover, the hard mask layer can be utilized as the etching stop layer in the CMP process.

Abstract: The present invention discloses a method for planarizing a semiconductor device used in an integrated circuit. According to the method, a semiconductor substrate on which a patterned layer having topology is formed, is loaded into a reactor chamber. Afterwards, an interlevel insulating layer is formed on the semiconductor substrate. Thereafter, a layer for the planarization containing a dopant is formed on the interlevel insulating layer. The dopant contained in the layer for the planarization, is diffused outwards from the surface of the layer. The dopant diffused outwards from the layer for the planarization is pumped out to the outside of the reactor chamber without introducing an inert gas to the reactor chamber. Finally, the layer for the planarization is flowed.

Abstract: A method of depositing a fluorinated borophosphosilicate glass (FBPSG) on a semiconductor device as either a final or interlayer dielectric film. Gaps having aspect ratios greater than 6:1 are filled with a substantially void-free FBPSG film at a temperature of about 480.degree. C. at sub-atmospheric pressures of about 200 Torr. Preferably, gaseous reactants used in the method comprise TEOS, FTES, TEPO and TEB with an ozone/oxygen mixture. Dopant concentrations of boron and phosphorus are sufficiently low such that surface crystallite defects and hygroscopicity are avoided. The as-deposited films at lower aspect ratio gaps are substantially void-free such that subsequent anneal of the film is not required. Films deposited into higher aspect ratio gaps are annealed at or below about 750.degree. C., well within the thermal budget for most DRAM, logic and merged logic-DRAM chips. The resultant FBPSG layer contains less than or equal to about 5.0 wt % boron, less than about 4.0 wt % phosphorus, and about 0.

Abstract: Methods of forming dielectric layers and methods of forming capacitors are described. In one embodiment, a substrate is placed within a chemical vapor deposition reactor. In the presence of activated fluorine, a dielectric layer is chemical vapor deposited over the substrate and comprises fluorine from the activated fluorine. In another embodiment, a fluorine-comprising material is formed over at least a portion of an internal surface of the reactor. Subsequently, a dielectric layer is chemical vapor deposited over the substrate. During deposition, at least some of the fluorine-comprising material is dislodged from the surface portion and incorporated in the dielectric layer. In another embodiment, the internal surface of the reactor is treated with a gas plasma generated from a source gas comprising fluorine, sufficient to leave some residual fluorine thereover.

Abstract: A method for manufacturing a gate oxide film in a semiconductor device includes: preparing a semiconductor substrate having a first and a second active region; implanting germanium ions into the first active region; and forming a first and a second gate oxide films on the first and the second active regions, respectively, wherein the first gate oxide film is thicker than the second gate oxide film.

Abstract: A semiconductor device manufacturing method comprises the steps of depositing a first insulation coating on a substrate, forming a wiring groove on the first insulation coating, depositing aluminum or its alloy on the wiring groove, eliminating the aluminum or its alloy deposited over the other portion than the wiring groove, depositing a second insulation coating doped with at least B or P on the substrate, depositing a third insulation coating on the second insulation coating, applying a photoresist on the third insulation coating, and exposing the photoresist to a light of short wavelength.

Abstract: An integrated circuit and its method of formation are disclosed. The circuit utilizes a spin-on glass as an interlevel dielectric. Above and below the spin-on glass is located a phosphorous doped dielectric. The doped dielectric prevents sodium from becoming mobile under the influence of subsequently applied electric fields.

Abstract: Provision of differential etching of layers by, for example, an etch stop layer or implantation, allows a second trough etch to be performed in accordance with a block-out mask (which does not require high accuracy of registration) to provide troughs or recesses of different depths in layers of insulator. When the recesses or troughs are filled by metal deposition and patterned by planarization in accordance with damascene processing, structurally robust conductors of differing thicknesses may be achieved and optimized to enhance noise immunity and/or signal propagation speed in different functional regions of an integrated circuit such as the so-called array and support portions of a dynamic random access memory.

Abstract: A semiconductor device with satisfactory bonding avility of a plasma SiOF oxide layer on a wiring and satisfactory burying ability for buring wiring space portions. The semiconductor device is deposited by forming a metal layer to be a base of wiring on a semiconductor substrate, forming an anti-reflection layer of a refractory metal or compound thereof, on the metal layer, and forming an insulation layer on the anti-reflection layer. There after, the insulation layer is patterned and a wiring is patterned by etching the anti-reflection layer and the metal layer to be the base of the wiring with taking the patterned insulation layer as a mask with leasing the anti-reflection layer and the insulation layer on the wiring. Subsequently, the patterned wiring is buried with an SiOF layer as an Si oxide layer containing fluorine, together with the anti-reflection layer and the insulation layer on the upper surface.

Abstract: A EEPROM 140 has a storage transistor 160 with a gate insulating layer 104 of BPSG and a polysilicon gate 112.2 of the same layer as the polysilicon gate 112.1 of the FET transistor 150. The BPSG layer 104 has POHC traps that capture holes injected into N well 103.2. A positive voltage applied to N well 103.2 programs the storage transistor 160 off. Applying a positive voltage to the gate 112.2 neutralizes the holes stored in layer 104 and erases the memory of transistor 160.

Abstract: Methods of forming refractory metal silicide components are described. In accordance with one implementation, a refractory metal layer is formed over a substrate. A silicon-containing structure is formed over the refractory metal layer and a silicon diffusion restricting layer is formed over at least some of the silicon-containing structure. The substrate is subsequently annealed at a temperature which is sufficient to cause a reaction between at least some of the refractory metal layer and at least some of the silicon-containing structure to at least partially form a refractory metal silicide component. In accordance with one aspect of the invention, a silicon diffusion restricting layer is formed over or within the refractory metal layer in a step which is common with the forming of the silicon diffusion restricting layer over the silicon-containing structure.

Abstract: A method for forming a MOSFET device on a semiconductor substrate is disclosed here. First, a gate oxide layer, a polysilicon layer, a metal silicide layer and a silicon oxynitride layer are formed on the semiconductor substrate in sequence. Then, the silicon oxynitride layer, the metal silicide layer, the polysilicon layer and the gate oxide layer are etched to define a gate pattern. The sidewall spacers are formed on the sidewalls of the gate structure. The source and drain areas are defined by forming the doping areas in the semiconductor substrate. Next, a non-doped dielectric layer is formed above the semiconductor substrate to cover the gate structure, the sidewall spacers and the source/drain areas. An annealing procedure is next performed about 10 to 15 minutes at a temperature of about 800 to 850.degree. C. Then, a dielectric layer is formed on said non-doped dielectric layer.

Abstract: A method and apparatus for forming a halogen-doped silicon oxide film, preferably a fluorinated silicon glass (FSG) film, having compressive stress less than about -5.times.10.sup.8 dynes/cm.sup.2. In a specific embodiment, the FSG film is formed by a sub-atmospheric CVD thermal process at a pressure of between about 60-650 torr. The relatively thin film, besides having a low dielectric constant and good gap fill capability, has low compressive stress, and is particularly suitable for use as an intermetal (IMD) layer.

Abstract: A method and apparatus for controlling the introduction of contaminates into a deposition chamber that occur naturally within the chamber components. The CVD chamber is "seasoned" with a protective layer after a dry clean operation and before a substrate is introduced into the chamber. The deposited seasoning layer has a lower diffusion rate for typical contaminants in relation to the chamber component materials and covers the chamber component, reducing the likelihood that the naturally occurring contaminants will interfere with subsequent processing steps. After deposition of the seasoning layer is complete, the chamber is used for one to n substrate deposition steps before being cleaned by another clean operation as described above and then reseasoned.

Abstract: Reduction in the net charge at the interface of a dielectric and a semiconductor material is achieved by placing atomic species in the dielectric near the interface. Preferably, these species are selected from the group of alkaline earth metals. The presence of these atoms results in a redistribution of the electronic density near the interface. The placement of the atoms is effected by ion implantation followed by multiple annealing steps at alternating low and high temperatures.

Abstract: A fluorine-doped silicate glass (FSG) layer having a low dielectric constant and a method of forming such an insulating layer is described. The FSG layer is treated with a post-treatment step to make the layer resistant to moisture absorption and outgassing of fluorine atoms. In one embodiment, the post-treatment step includes forming a thin, undoped silicate glass layer on top of the FSG layer, and in another embodiment, the stability of the FSG film is increased by a post-treatment plasma step.

Abstract: A chemical vapor deposition (CVD) method for forming a doped silicate glass dielectric layer within a microelectronics fabrication. There is first positioned within a reactor chamber a substrate employed within a microelectronics fabrication. There is then stabilized within the reactor chamber with respect to the substrate a first flow of a silicon source material absent a flow of a dopant source material. There is then deposited upon the substrate within the reactor chamber a doped silicate glass dielectric layer through a chemical vapor deposition (CVD) method. The doped silicate glass dielectric layer is formed employing a second flow of the silicon source material, a flow of an oxidant source material and the flow of the dopant source material. There may subsequently be formed through the doped silicate glass dielectric layer an anisotropically patterned via through an anisotropic patterning method.

Abstract: A method for preventing bubble defects in borophosphosilicate glass (BPSG) film is provided. A wafer for depositing borophosphosilicate glass (BPSG) film is loaded in deposition chamber. After the wafer is properly positioned, the wafer is heated to a predetermined temperature. A process gas is introduced from the gas distribution system to the deposition chamber. A selected pressure of the deposition chamber is set and maintained throughout deposition process. After deposition of the BPSG film, the wafer is loaded out the chamber. Subsequently, helium gas is introduced to purge the liquid injection valve and delivery path. After pumping out the purge gas, the another wafer is then loaded in the chamber for depositing BPSG film.

Abstract: A semiconductor device including an interlayer insulation film is obtained, superior in planarization, insulation characteristics, and adhesion, suitable for microminiaturization of an element, and without inducing the problem of signal delay. In the fabrication method of this semiconductor device, an interconnection is formed on semiconductor substrate. Then, a first insulation film is formed so as to be in contact on the interconnection. Impurities are introduced into the first insulation film under a condition where the impurities arrive at least at the interconnection. As a result, the first insulation film is reduced in moisture and becomes less hygroscopic. Therefore, the insulation characteristics of the first insulation film is improved. When an SOG film superior in planarization is employed as the first insulation film, it is possible to directly form that SOG film on an underlying interconnection.

Abstract: A method to form polysilicon resistors shielded from hydrogen intrusion is described. A semiconductor substrate is provided. Field oxide isolation regions are provided overlying the substrate. A polysilicon layer is deposited overlying the field oxide regions and the substrate. The polysilicon layer is etched away where it is not covered by a mask to form a polysilicon resistor. An interlevel dielectric layer is deposited overlying the polysilicon resistor. Nitrogen ions are implanted into the interlevel dielectric layer. The interlevel dielectric layer is annealed to form a silicon oxynitride shield layer in the interlevel dielectric layer. Contact openings are etched through the interlevel dielectric layer to the polysilicon resistor. The contact openings are filled with a metal layer. The metal layer is patterned.

Abstract: A method of fabricating an oxidation barrier for a thin film is provided. The method may include forming a thin film (10) outwardly from a semiconductor substrate (12) and separated from the semiconductor substrate (12) by a primary insulator layer (14). A reactive layer (16) may be formed in-situ adjacent to the thin film (10). An oxidation barrier (20) may be formed by a chemical reaction between the thin film (10) and the reactive layer (16). The oxidation barrier (20) may comprise a silicide alloy that operates to reduce oxidation of the thin film (10).

Abstract: A method of deposition with 4-PASS which is performed by a WJ-1000 or WJ-999 machine. Before each deposition is performed, it is necessary to turn the wafer an angle of 90.degree. in the same direction. When deposition is this manner is performed four times on the same wafer, the uniformity in the four corners of the layer deposited on the 8-inch wafer can be improved. Over-polishing or recesses can be reduced and the kink effect can be prevented. 4-PASS deposition performed on the WJ-1000 or WJ-999 machine can make the uniformity within the wafer better and the yield of production can be increased.

Abstract: A method for improving the planarization of a BPSG layer over a semiconductor substrate, where the substrate contains underlying structures, is disclosed. The method comprises the steps of: forming a first borophosphosilicate glass (BPSG) layer over and between the underlying structures; reflowing the first BPSG layer using a thermal process; performing a chemical mechanical polishing (CMP) step on the first BPSG layer; forming a second BPSG layer over the first BPSG layer; and reflowing the second BPSG layer using a thermal process.

Abstract: A method is provided for forming tantalum adhesion/barrier layers on semiconductor channels or in vias in low dielectric constant, fluorinated dielectric layers. The dielectric layers are defluorinated using hydrogen, ammonia, methane, or silane plasma and a subsequent tantalum deposition forms a less fluorine reactive tantalum carbide or tantalum silicide. Tantalum or tantalum nitride is then deposited over the less reactive form of tantalum to form the adhesion/barrier for deposition of a subsequent seed layer and a conductive material to form the vias and channels.

Abstract: The invention provides a method for producing wiring and contacts in an integrated circuit including the steps of forming insulated gate components on a semiconductor substrate; applying a photo-reducible dielectric layer to cover the substrate; etching holes and forming contacts; photo-reducing the dielectric to increase its conductivity; covering the resulting structure with an interconnect layer; etching the interconnect layer to define wiring in electrical contact with the contacts; and oxidizing the dielectric to reduce its conductivity.

Abstract: A semiconductor device having relatively low permittivity fluorine bearing oxide between conductive lines and a method for fabricating such a device is provided. At least two adjacent conductive lines are formed over a substrate. An oxide layer is formed between the adjacent conductive lines. A mask is formed over the oxide layer and selectively removed to expose a portion of the oxide layer between the adjacent conductive lines. A fluorine bearing species is implanted into the exposed portion of the oxide layer to reduce the permittivity of the oxide layer between the adjacent conductive lines. The permittivity or dielectric constant of the oxide layer between the adjacent conductive lines can, for example, be reduced from about 3.9 to 4.2 to about 3.0 to 3.5.