Abstract: A method for depositing a dielectric film on a substrate includes positioning a plurality of substrates in a process chamber, heating the process chamber to a deposition temperature between 400° C. and less than 650° C., flowing a first process gas comprising water vapor into the process chamber, flowing a second process gas comprising dichlorosilane (DCS) into the process chamber, establishing a gas pressure of less than 2 Torr, and reacting the first and second process gases to thermally deposit a silicon oxide film on the plurality of substrates. One embodiment further includes flowing a third process gas comprising nitric oxide (NO) gas into the process chamber while flowing the first process gas and the second process gas; and reacting the oxide film with the third process gas to form a silicon oxynitride film on the substrate.

Abstract: Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g.

Abstract: The present invention relates to a process of making a zinc-oxide-based thin film semiconductor, for use in a transistor, comprising thin film deposition onto a substrate comprising providing a plurality of gaseous materials comprising first, second, and third gaseous materials, wherein the first gaseous material is a zinc-containing volatile material and the second gaseous material is reactive therewith such that when one of the first or second gaseous materials are on the surface of the substrate the other of the first or second gaseous materials will react to deposit a layer of material on the substrate, wherein the third gaseous material is inert and wherein a volatile indium-containing compound is introduced into the first reactive gaseous material or a supplemental gaseous material.

Abstract: A film formation apparatus for a semiconductor process includes a source gas supply circuit to supply into a process container a source gas for depositing a thin film on target substrates, and a mixture gas supply circuit to supply into the process container a mixture gas containing a doping gas for doping the thin film with an impurity and a dilution gas for diluting the doping gas. The mixture gas supply circuit includes a gas mixture tank disposed outside the process container to mix the doping gas with the dilution gas to form the mixture gas, a mixture gas supply line to supply the mixture gas from the gas mixture tank into the process container, a doping gas supply circuit to supply the doping gas into the gas mixture tank, and a dilution gas supply circuit to supply the dilution gas into the gas mixture tank.

Abstract: A method including providing a semiconductor substrate in a reaction chamber; flowing a first reactant including silicon and oxygen, a boron dopant and a phosphorus dopant into the reaction chamber so that a layer of BPTEOS is deposited on the semiconductor substrate; stopping the flow of the first reactant, boron dopant and phosphorus dopant into the reaction chamber and so that a phosphorus dopant and boron dopant rich film is deposited over the layer of BPTEOS; and reducing the film comprising exposing the film to an O2 plasma.

Abstract: A method for depositing a low dielectric constant film by flowing a oxidizing gas into a processing chamber, flowing an organosilicon compound from a bulk storage container through a digital liquid flow meter at an organosilicon flow rate to a vaporization injection valve, vaporizing the organosilicon compound and flowing the organosilicon compound and a carrier gas into the processing chamber, maintaining the organosilicon flow rate to deposit an initiation layer, flowing a porogen compound from a bulk storage container through a digital liquid flow meter at a porogen flow rate to a vaporization injection valve, vaporizing the porogen compound and flowing the porogen compound and a carrier gas into the processing chamber, increasing the organosilicon flow rate and the porogen flow rate while depositing a transition layer, and maintaining a second organosilicon flow rate and a second porogen flow rate to deposit a porogen containing organosilicate dielectric layer.

Abstract: Some embodiments include methods of forming low k dielectric regions between electrically conductive lines. A construction may be formed to have a plurality of spaced apart electrically conductive lines, and to have sacrificial material between the electrically conductive lines. The sacrificial material may be removed. Subsequently, electrically insulative material may be deposited over and between the lines. The deposition of the insulative material may occur under conditions in which bread-loafing of the insulative material creates bridges of the insulative material across gas-filled gaps between the lines. The gas-filled gaps may be considered to correspond to low k dielectric regions between the electrically conductive lines. In some embodiments the sacrificial material may be carbon. In some embodiments, the deposited insulative material may be a low k dielectric material, and in other embodiments the deposited insulative material may not be a low k dielectric material.

Abstract: Methods of preparing a carbon doped oxide (CDO) layers having a low dielectric constant are provided. The methods involve, for instance, providing a substrate to a deposition chamber and exposing it to one or multiple carbon-doped oxide precursors having molecules with at least one carbon-carbon triple bond, or carbon-carbon double bond, or a combination of these groups and depositing the carbon doped oxide dielectric layer under conditions in which the resulting dielectric layer has a dielectric constant of not greater than about 2.7. Methods of preparing a low stress porous low-k dielectric material on a substrate are provided. The methods involve the use of a structure former precursor and/or porogen precursor with one or more organic functional groups. In some cases, the structure former precursor has carbon-carbon double or triple bonds. In other cases, one or both of the structure former precursor and porogen precursor has one or more bulky organic groups.

Abstract: An organic electroluminescent display device and a method of preparing the same are provided. The organic electroluminescent display device may include a first electrode formed on a substrate. A second electrode may be formed so as to be insulated from the first electrode. One or more organic layers may be interposed between the first electrode and the second electrode and include at least an emission layer. A protective layer may be formed so as to cover the second electrode. The protective layer may have a surface roughness (rms) of about 5 ? to about 50 ?. The organic electroluminescent display device including a protective layer having a low surface roughness may benefit from superior lifespan characteristics.

Abstract: A method for etching features in an etch layer disposed below a mask on a process wafer is provided. A hydrocarbon based glue layer is deposited. The etch layer on the process wafer is etched with at least one cycle, wherein each cycle comprises depositing a hydrofluorocarbon layer over the mask and on the hydrocarbon based glue layer, wherein the hydrocarbon based glue layer increases adhesion of the hydrofluorocarbon layer and etching the etch layer.

Abstract: Methods of forming integrated circuit devices according to embodiments of the present invention include forming a PMOS transistor having P-type source and drain regions, in a semiconductor substrate, and then forming a diffusion barrier layer on the source and drain regions. A silicon nitride layer is deposited on at least portions of the diffusion barrier layer that extend opposite the source and drain regions. Hydrogen is removed from the deposited silicon nitride layer by exposing the silicon nitride layer to ultraviolet (UV) radiation. This removal of hydrogen may operate to increase a tensile stress in a channel region of the field effect transistor. This UV radiation step may be followed by patterning the first and second silicon nitride layers to expose the source and drain regions and then forming silicide contact layers directly on the exposed source and drain regions.

Abstract: A method including introducing a fluorine-free organometallic precursor in the presence of a substrate; and forming a conductive layer including a moiety of the organometallic precursor on the substrate according to an atomic layer or chemical vapor deposition process. A method including forming an opening through a dielectric layer to a contact point; introducing a fluorine-free copper film precursor and a co-reactant; and forming a copper-containing seed layer in the opening. A system including a computer including a microprocessor electrically coupled to a printed circuit board, the microprocessor including conductive interconnect structures formed from fluorine-free organometallic precursor.

Abstract: A method including providing a semiconductor substrate in a reaction chamber; flowing a first reactant including silicon and oxygen, a boron dopant and a phosphorus dopant into the reaction chamber so that a layer of BPTEOS is deposited on the semiconductor substrate; stopping the flow of the first reactant, boron dopant and phosphorus dopant into the reaction chamber and so that a phosphorus dopant and boron dopant rich film is deposited over the layer of BPTEOS; and reducing the film comprising exposing the film to an O2 plasma.

Abstract: The present invention provides method of forming a gate dielectric that includes forming a metal source layer (210) comprising a metal and at least one nonmetallic element over a substrate (110). The metal source layer (210) is formed having a composition rich in the metal. A dielectric layer (310) comprising the metal is formed over the metal source layer (210).

Abstract: This invention includes methods of forming a phosphorus doped silicon dioxide comprising layers, and methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of forming a phosphorus doped silicon dioxide comprising layer includes positioning a substrate within a deposition chamber. First and second vapor phase reactants are introduced in alternate and temporally separated pulses to the substrate within the chamber in a plurality of deposition cycles under conditions effective to deposit a phosphorus doped silicon dioxide comprising layer on the substrate. One of the first and second vapor phase reactants is PO(OR)3 where R is hydrocarbyl, and an other of the first and second vapor phase reactants is Si(OR)3OH where R is hydrocarbyl.

Abstract: A semiconductor substrate undergoing processing to fabricate integrated circuit devices thereon is spun about a rotational axis while introducing liquid onto a surface of the substrate. An annular-shaped sheet of liquid is formed on the surface, the sheet of liquid having an inner diameter defining a liquid-free void. The size of a diameter of the void is reduced by manipulation of the annular-shaped sheet of liquid. The void may then be enlarged until the surface is substantially dry. The annular-shaped sheet of liquid may be formed and altered by selectively moving a contact area on the surface of the substrate on which the liquid is introduced. Systems for processing a substrate and configured to deposit and manipulate a sheet of liquid thereon are also disclosed.

Abstract: A capacitor structure comprises a first and a second electrode of conducting material. Between the first and second electrodes, an atomic layer deposited dielectric film is disposed, which comprises zirconium oxide and a dopant oxide. Herein, the dopant comprises an ionic radius that differs by more than 24 pm from an ionic radius of zirconium, while the dielectric film comprises a dopant content of 10 atomic percent or less of the dielectric film material excluding oxygen. A process for fabricating a capacitor comprises a step of forming a bottom electrode of the capacitor. On the bottom electrode, a dielectric film comprising zirconium oxide is deposited, and a step for introducing a dopant oxide into the dielectric film performed. On the dielectric structure, a top electrode is formed.

Abstract: A thin film including multi components and a method of forming the thin film are provided, wherein a method according to an embodiment of the present invention, a substrate is loaded into a reaction chamber. A unit material layer is formed on the substrate. The unit material layer may be formed of a mosaic atomic layer composed of two kinds of precursors containing components constituting the thin film. The inside of the reaction chamber is purged, and the MAL is chemically changed. The method of forming the thin film of the present invention requires fewer steps than a conventional method while retaining the advantages of the conventional method, thereby allowing a superior thin film yield in the present invention than previously obtainable.

Abstract: The present invention generally provides methods and apparatuses that are adapted to form a high quality dielectric gate layer on a substrate. Embodiments contemplate a method wherein a metal plasma treatment process is used in lieu of a standard nitridization process to form a high dielectric constant layer on a substrate. Embodiments further contemplate an apparatus adapted to “implant” metal ions of relatively low energy in order to reduce ion bombardment damage to the gate dielectric layer, such as a silicon dioxide layer and to avoid incorporation of the metal atoms into the underlying silicon. In general, the process includes the steps of forming a high-k dielectric and then terminating the surface of the deposited high-k material to form a good interface between the gate electrode and the high-k dielectric material.

Abstract: A metal pattern of the present invention is a metal pattern (13?) formed on a surface of a substrate by etching, and a monomolecular film containing fluorinated alkyl chains (CF3(CF2)n—, where n represents an integer) is formed on a surface of a metal film composing the metal pattern (13?), and a masking film (18) is formed by penetration of a molecule having a mercapto group (—SH) or a disulfide (—SS—) group into interstices between molecules composing the monomolecular film.

Abstract: The present invention generally provides methods and apparatuses that are adapted to form a high quality dielectric gate layer on a substrate. Embodiments contemplate a method wherein a metal plasma treatment process is used in lieu of a standard nitridization process to form a high dielectric constant layer on a substrate. Embodiments further contemplate an apparatus adapted to “implant” metal ions of relatively low energy in order to reduce ion bombardment damage to the gate dielectric layer, such as a silicon dioxide layer and to avoid incorporation of the metal atoms into the underlying silicon. In general, the process includes the steps of forming a high-k dielectric and then terminating the surface of the deposited high-k material to form a good interface between the gate electrode and the high-k dielectric material.

Abstract: Methods of forming a dielectric layer having a low dielectric constant and high mechanical strength are provided. The methods involve depositing a sub-layer of the dielectric material on a substrate, followed by treating the sub-layer with a plasma. The process of depositing and plasma treating the sub-layers is repeated until a desired thickness has been reached.

Abstract: A method for manufacturing a semiconductor device which includes: alternately supplying a silicon source and an oxidant to deposit a silicon oxide film on a surface of a semiconductor substrate, wherein the silicon source is supplied under a supply condition where an adsorption amount of molecules of the silicon source on the semiconductor substrate is increased without causing an adsorption saturation of the molecules of the silicon source on the semiconductor substrate, and wherein the oxidant is supplied under a supply condition where impurities remain in the molecules of the silicon source adsorbed on the semiconductor substrate.

Abstract: A method of forming a porous film on a semiconductor substrate includes: supplying a silicon compound containing at least one Si—O bond in its molecule in a gaseous phase into a reaction chamber; forming a siloxane oligomer through plasma reaction of the silicon compound; and supplying an organic amine in a gaseous phase into the reaction chamber and reacting the organic amine with the siloxane oligomer, thereby forming a porous film on the semiconductor substrate.

Abstract: A method for forming a semiconductor device is provided. In one embodiment, the method includes providing a semiconductor substrate with a surface region. The surface region includes one or more layers overlying the semiconductor substrate. In addition, the method includes depositing a dielectric layer overlying the surface region. The dielectric layer is formed by a CVD process. Furthermore, the method includes forming a diffusion barrier layer overlying the dielectric layer. In addition, the method includes forming a conductive layer overlying the diffusion barrier layer. Additionally, the method includes reducing the thickness of the conductive layer using a chemical-mechanical polishing process. The CVD process utilizes fluorine as a reactant to form the dielectric layer. In addition, the dielectric layer is associated with a dielectric constant equal or less than 3.3.

Abstract: Methods and devices for a dielectric are provided. One method embodiment includes forming a passivation layer on a substrate, wherein the passivation layer contains a composition of silicon, oxygen, and nitrogen. The method also includes forming a lanthanide dielectric film on the passivation layer, and forming an encapsulation layer on the lanthanide dielectric film.

Abstract: An object of the present invention is to prevent the deterioration of a TFT (thin film transistor). The deterioration of the TFT by a BT test is prevented by forming a silicon oxide nitride film between the semiconductor layer of the TFT and a substrate, wherein the silicon oxide nitride film ranges from 0.3 to 1.6 in a ratio of the concentration of N to the concentration of Si.

Abstract: Low dielectric materials and films comprising same have been identified for improved performance when used as interlevel dielectrics in integrated circuits as well as methods for making same. In certain embodiments of the invention, there is provided a low-temperature process to remove at least a portion of at least one pore-forming material within a composite film thereby forming a porous film. The pore-forming material may be removed via exposure to at least one energy source, preferably an ultraviolet light source, in a non-oxidizing atmosphere.

Abstract: A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in a way so that film deposition occurs from the bottom of the trench upwards, with step coverage well in excess of 100%. In a second fill step, deposition conditions are changed to reduce the impact of dopant on deposition rate, and deposition proceeds at a rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.

Abstract: A method for manufacturing a semiconductor device, in which a substrate is disposed in a chamber and a fluorine-containing silicon oxide film is formed on the substrate using a plasma CVD process. The fluorine-containing silicon oxide film is formed such that the release of fluorine from this silicon oxide layer is suppressed. According to this semiconductor device manufacturing method, a stable semiconductor device can be provided such that the device includes a fluorine-containing silicon oxide film (FSG film) at which the release of fluorine is suppressed, and thus peeling does not occur.

Abstract: A method for depositing a low dielectric constant film by flowing a oxidizing gas into a processing chamber, flowing an organosilicon compound from a bulk storage container through a digital liquid flow meter at an organosilicon flow rate to a vaporization injection valve, vaporizing the organosilicon compound and flowing the organosilicon compound and a carrier gas into the processing chamber, maintaining the organosilicon flow rate to deposit an initiation layer, flowing a porogen compound from a bulk storage container through a digital liquid flow meter at a porogen flow rate to a vaporization injection valve, vaporizing the porogen compound and flowing the porogen compound and a carrier gas into the processing chamber, increasing the organosilicon flow rate and the porogen flow rate while depositing a transition layer, and maintaining a second organosilicon flow rate and a second porogen flow rate to deposit a porogen containing organosilicate dielectric layer.

Abstract: An electronic apparatus includes an insulative substrate containing an aluminum-based glass and a layer containing a semiconductive material over the substrate. The insulative substrate can include aluminum oxycarbide. The insulative substrate can exhibit a CTE sufficiently close to a CTE of the semiconductive material layer such that a strain of less than 1% would exist between a 1000 Angstroms thickness of the semiconductive material layer and the insulative substrate. The semiconductive material layer can include monocrystalline silicon. The electronic apparatus can be a silicon-on-insulator integrated circuit. An electronic apparatus fabrication method includes forming an insulative substrate containing an aluminum-based glass and forming a layer containing a semiconductive material over the substrate.

Abstract: The present invention discloses a process for depositing a carbon containing silicon oxide film, or a carbon containing silicon nitride film having enhanced etch resistance. The process comprises using a silicon containing precursor, a carbon containing precursor and a chemical modifier. The present invention also discloses a process for depositing a silicon oxide film, or silicon nitride film having enhanced etch resistance comprising using an organosilane precursor and a chemical modifier.

Abstract: A method of using a film formation apparatus for a semiconductor process includes a step of removing a by-product film deposited on an inner surface of a reaction chamber of the film formation apparatus. This step is performed while supplying a cleaning gas containing hydrogen fluoride into the reaction chamber, and forming a first atmosphere within the reaction chamber, which allows water to be present as a liquid film.

Abstract: A two-step high density plasma-CVD process is described wherein the argon content in the film is controlled by using two different argon concentrations in the argon/silane/oxygen gas mixture used for generating the high density plasma. The first step deposition uses high argon concentration and low sputter etch-to-deposition (E/D) ratio. High E/D ratio maintains the gap openings without necking. In the second step, a lower argon concentration and lower E/D ratio are used. Since observed metal defects are caused by argon diffusion in the top 200-300 nm of the HDP-CVD film, by controlling argon concentration in the top part of the film (i.e. second step deposition) to a low value, a reduced number of metal defects are achieved.

Abstract: Methods and apparatus are provided for forming thin films for semiconductor devices, which enable supplying and removing reactants containing constituent elements of a thin film to be formed, by preheating and supplying a process gas and a purging gas at a predetermined temperature in forming the thin film on a substrate. For example, a method for forming a thin film includes supplying a first reactant to a chamber to chemically adsorb the first reactant onto a substrate, the first reactant being bubbled by a first gas that is preheated, purging the chamber to remove residues on the substrate having the first reactant chemically adsorbed, and forming the thin film by a means of chemical displacement by supplying a second reactant to the chamber to chemically adsorb the second reactant onto the substrate.

Abstract: A liquid injector is used to vaporize and inject a silicon precursor into a process chamber to form silicon-containing layers during a semiconductor fabrication process. The injector is connected to a source of silicon precursor, which preferably comprises liquid trisilane in a mixture with one or more dopant precursors. The mixture is metered as a liquid and delivered to the injector, where it is then vaporized and injected into the process chamber.

Abstract: A method for forming IMD films. A substrate is provided. A plurality of dielectric films are formed on the substrate, wherein each of the dielectric layers are deposited in-situ in one chamber with only one thermal cycle.

Abstract: Embodiments of the invention provide a relatively hydrophilic layer in a low k dielectric layer. The hydrophilic layer may be formed by exposing the dielectric layer to light having enough energy to break Si—C and C—C bonds but not enough to break Si—O bonds.

Abstract: A method of forming films in a semiconductor device that can appropriately control a resistance value of a thin film resistance on an ozone TEOS film while preventing a metal thin film from remaining around a surface step unit after the metal thin film was dry etched. First, as shown in FIG. 1A, a step unit with the height of about 1 ?m is formed by forming elements such as HBT on a semiconductor substrate made up of semi-insulating GaAs. Next, as shown in FIG. 1B, a first ozone TEOS film with the thickness of 900 nm by a Normal pressure CVD method using mixed gas of tetraethoxysilane with ozone. Then, a second ozone TEOS film with the thickness of 100 nm is formed by reducing the ozone concentration to 10 g/m3, while maintaining the substrate temperature at 350° C.

Abstract: A processing method for depositing porous silica and doped silica films is provided. The method uses a cyclic scheme wherein each cycle comprises first codepositing silica with silicon, then selectively removing the silicon from the codeposit to form a porous structure. In a preferred embodiment, the codeposition is carried out by plasma enhanced chemical vapor deposition. After codeposition, the codeposit is exposed to a selective silicon removal reagent that can preferentially remove the silicon in the codeposit, leaving behind a porous structure. Repeated execution of the codeposition and the selective silicon removal steps build up thickness of the porous film. A porous film with highly uniform small pores and a desired porosity profile can be obtained with this method. This method is advantageous for forming a broad range of low-k dielectrics for semiconductor integrated circuit fabrication. The general method is also advantageous for forming other porous films for other applications.

Abstract: A method for fabricating a semiconductor device comprises the step of depositing an insulation film 32a with a first pressure set in a deposition chamber; the step of gradually decreasing the pressure in the deposition chamber to a second pressure which is lower than the first pressure; and the step of further depositing the insulation film 32b with the second pressure set in the deposition chamber. The insulation film is deposited with the first pressure a little lower than a second pressure set in a deposition chamber, and the insulation film is further deposited with the second pressure lower than the first pressure set in the deposition chamber. Furthermore, the insulation film is not deposited in the state where the pressure in the deposition chamber is extremely low, and an atmosphere in the deposition chamber is unstable. Thus, a semiconductor device having the insulation film with a sufficiently flat surface can be fabricating without using reflow process.

Abstract: A semiconductor structure including an insulator layer formed of a first polymer. The structure also includes an organic semiconductor layer formed of a second polymer. The polymers self-assemble into a well-ordered co-polymer structure with the semiconductor layer positioned adjacent the insulator layer. The structure may be an organic, thin-film semiconductor device including, without limitation, a transistor, a multi-gate transistor, a thyristor, and the like. Also disclosed is a process of manufacturing the semiconductor structure.

Abstract: A method of planarizing a layer of an integrated circuit. In one embodiment, a liquid film is applied over the layer, using extrusion coating techniques. In another embodiment, the layer itself may be applied as a liquid film, using extrusion techniques.

Abstract: A method of forming phoslon (PNO) comprising the following steps. A CVD reaction chamber having a reaction temperature of from about 300 to 600° C. is provided. From about 10 to 200 sccm PH3 gas, from about 50 to 4000 sccm N2 gas and from about 50 to 1000 sccm NH3 gas are introduced into the CVD reaction chamber. Either from about 10 to 200 sccm O2 gas or from about 50 to 1000 sccm N2O gas is introduced into the CVD reaction chamber. An HFRF power of from about 0 watts to 4 kilowatts is also employed. An LFRF power of from about 0 to 5000 watts may also be employed. Employing a phoslon etch stop layer in a borderless contact fabrication. Employing a phoslon lower etch stop layer and/or a phoslon middle etch stop layer in a dual damascene fabrication.

Abstract: A method for controlling the properties of a dielectric anti-reflective coating (DARC) is provided. In the process of forming the DARC, a nitrogen-containing gas is added to a reaction gas comprising silicon-containing gas and oxygen for controlling the n value of the DARC. Furthermore, the proportion of the silicon-containing gas to the oxygen or the proportion of the silicon-containing gas to the nitrogen-containing gas is increased to control the k value of the DARC. By means of proper control of the n value and the k value, the DARC can have the lowest substrate reflectivity.

Abstract: The invention is a method of determining a set temperature profile of a method of controlling respective substrate temperatures of plurality of groups in accordance with respective corresponding set temperature profiles. The invention includes a first heat processing step of controlling respective substrate temperatures of a plurality of groups in accordance with respective predetermined provisional set temperature profiles for first-batch substrates that are classified into the plurality of groups, and of introducing a process gas to conduct a heat process to form films on the substrates; a first film-thickness measuring step of measuring a thickness of the films formed on the substrates; and a first set-temperature-profile amending step of respectively amending the provisional set temperature profiles based on the measured thickness, in such a manner that a thickness of films formed during a heat process is substantially the same between the plurality of groups.

Abstract: A processing method for depositing porous silica and doped silica films is provided. The method uses a cyclic scheme wherein each cycle comprises first codepositing silica with silicon, then selectively removing the silicon to form a porous structure. In a preferred embodiment, the codeposition is carried out by plasma enhanced chemical vapor deposition. The reagent feed stream comprises a mixture of codeposition reagents and a selective silicon removal reagent. RF power modulation is used to control the codeposition and the selective silicon removal steps with the later proceeds whenever the RF power is turned off or reduced to a low level. A porous film with highly uniform small pores and a desired porosity profile can be obtained with this method. This method is advantageous for forming a broad range of low-k dielectrics for semiconductor integrated circuit fabrication. The method is also advantageous for forming other porous films for other applications.

Abstract: This invention includes methods of forming phosphorus doped silicon dioxide comprising layers, and methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of forming a phosphorus doped silicon dioxide comprising layer includes positioning a substrate within a deposition chamber. First and second vapor phase reactants are introduced in alternate and temporally separated pulses to the substrate within the chamber in a plurality of deposition cycles under conditions effective to deposit a phosphorus doped silicon dioxide comprising layer on the substrate. One of the first and second vapor phase reactants is PO(OR)3 where R is hydrocarbyl, and an other of the first and second vapor phase reactants is Si(OR)3OH where R is hydrocarbyl.

Abstract: A method of forming a pre-metal dielectric film having good as deposited gapfill characteristics, as well as good mobile-ion gettering capability. The method involves first depositing a layer of high-ozone undoped silicon dioxide film having a high ozone/TEOS volume ratio. Then, a low-ozone doped BPSG film is deposited over the high-ozone undoped silicon dioxide layer. The film layers are heat treated to densify the film, and then the top layer is planarized using known planarization techniques to a thickness that allows for adequate mobile-ion gettering.