Silicon Oxide Formation Patents (Class 438/787)
  • Patent number: 8461015
    Abstract: A method for forming an STI structure is provided. In one embodiment, a trench is formed in a substrate, the trench having a first sidewall and a second sidewall opposite the first sidewall, the sidewalls extending down to a bottom portion of the trench. An insulating material is deposited to line the surfaces of the sidewalls and the bottom portion. The insulating material proximate the top portions and the bottom portion of the trench are thereafter etched back. The insulating material is deposited to line the inside surfaces of the trench at a rate sufficient to allow a first protruding insulating material deposited on the first sidewall and a second protruding insulating material deposited on the second sidewall to approach theretogether. The steps of etching back and depositing are repeated to have the first and second protruding materials abut, thereby forming a void near the bottom of the trench.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: June 11, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Han-Pin Chung, Shiang-Bau Wang
  • Patent number: 8455374
    Abstract: Embodiments of the present invention generally provide a process and apparatus for increasing the absorption coefficient of a chamber component disposed in a thermal process chamber. In one embodiment, a method generally includes providing a substrate carrier having a first surface and a second surface, the first surface is configured to support a substrate and being parallel and opposite to the second surface, subjecting the second surface of the substrate carrier to a surface treatment process to roughen the second surface of the substrate carrier, wherein the substrate carrier contains a material comprising silicon carbide, and forming an oxide-containing layer on the roughened second surface of the substrate carrier. The formed oxide-containing layer has optical absorption properties at wavelengths close to the radiation delivered from one or more energy sources used to heat the chamber component.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: June 4, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Hiroji Hanawa, Kyawwin Jason Maung
  • Patent number: 8450218
    Abstract: A method of forming silicon oxide includes depositing a silicon nitride-comprising material over a substrate. The silicon nitride-comprising material has an elevationally outermost silicon nitride-comprising surface. Such surface is treated with a fluid that is at least 99.5% H2O by volume. A polysilazane-comprising spin-on dielectric material is formed onto the H2O-treated silicon nitride-comprising surface. The polysilazane-comprising spin-on dielectric material is oxidized to form silicon oxide. Other implementations are contemplated.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: May 28, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Yunjun Ho, Brent Gilgen
  • Patent number: 8450813
    Abstract: There is provided a fin transistor structure and a method of fabricating the same. The fin transistor structure comprises a fin formed on a semiconductor substrate, wherein a bulk semiconductor material is formed between a portion of the fin serving as the channel region of the transistor structure and the substrate, and an insulation material is formed between remaining portions of the fin and the substrate. Thereby, it is possible to reduce the current leakage while maintaining the advantages of body-tied structures.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: May 28, 2013
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Zhijiong Luo, Haizhou Yin, Huilong Zhu
  • Patent number: 8445973
    Abstract: There is provided a fin transistor structure and a method of fabricating the same. The fin transistor structure comprises a fin formed on a semiconductor substrate, wherein an insulation material is formed between a portion of the fin serving as the channel region of the transistor structure and the substrate, and a bulk semiconductor material is formed between remaining portions of the fin and the substrate. Thereby, it is possible to reduce the current leakage while maintaining the advantages such as low cost and high heat transfer.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: May 21, 2013
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Zhijiong Luo, Huilong Zhu, Haizhou Yin
  • Patent number: 8435906
    Abstract: Methods and apparatus for forming an oxide layer on a semiconductor substrate are disclosed. In one or more embodiments, plasma oxidation is used to form a conformal oxide layer by controlling the temperature of the semiconductor substrate at below about 100° C. Methods for controlling the temperature of the semiconductor substrate according to one or more embodiments include utilizing an electrostatic chuck and a coolant and gas convection.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: May 7, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Agus S. Tjandra, Christopher S. Olsen, Johanes F. Swenberg, Yoshitaka Yokota
  • Publication number: 20130109200
    Abstract: There can be obtained a method for manufacturing a semiconductor device in which adherence of particles can be suppressed and printing onto a substrate can be done. The method for manufacturing a semiconductor device includes the steps of: preparing a substrate formed of a semiconductor; forming a protective film to cover at least a part of a main surface of the substrate; and doing printing onto the substrate by irradiating, with laser, the main surface having the protective film. In the step of forming a protective film, the protective film made of a material having a band gap larger than that of the semiconductor constituting the substrate is formed. In the step of doing printing onto the substrate, the substrate is irradiated with laser Lb having such a wavelength that an absorptance of the material for the protective film is smaller than that of the semiconductor constituting the substrate.
    Type: Application
    Filed: October 24, 2012
    Publication date: May 2, 2013
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventor: Sumitomo Electric Industries, Ltd.
  • Patent number: 8431494
    Abstract: A film formation method of forming a silicon oxide film on a surface of an object to be processed in a process chamber includes absorbing a seed gas comprising a silane-based gas on the surface of the object to be processed by supplying the seed gas into the process chamber, forming a silicon film having an impurity by supplying a silicon-containing gas as a material gas, and an addition gas including the impurity into the process chamber, and oxidizing the silicon film to convert the silicon film into the silicon oxide film. Accordingly, the silicon oxide film having the high density and the high stress is formed on the surface of the object to be processed.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: April 30, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Hiroki Murakami, Kazuhide Hasebe, Kazuya Yamamoto, Toshihiko Takahashi, Daisuke Suzuki
  • Patent number: 8420553
    Abstract: A manufacturing method of a semiconductor device, which includes the steps of forming a gate electrode layer over a substrate having an insulating surface, forming a gate insulating layer over the gate electrode layer, forming an oxide semiconductor layer over the gate insulating layer, forming a source electrode layer and a drain electrode layer over the oxide semiconductor layer, forming an insulating layer including oxygen over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and after formation of an insulating layer including hydrogen over the insulating layer including oxygen, performing heat treatment so that hydrogen in the insulating layer including hydrogen is supplied to at least the oxide semiconductor layer.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: April 16, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8415258
    Abstract: Provided is a method of manufacturing a semiconductor device. The method includes: loading a substrate into a process vessel; performing a process to form an film on the substrate by alternately repeating: (a) forming a layer containing an element on the substrate by supplying at least two types of source gases into the process vessel, each of the at least two types of source gases containing the element, and (b) changing the layer containing the element by supplying reaction gas into the process vessel, the reaction gas being different from the at least two types of source gases; and unloading the processed substrate from the process vessel.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: April 9, 2013
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Naonori Akae, Yoshiro Hirose, Yushin Takasawa, Yosuke Ota, Ryota Sasajima
  • Patent number: 8404583
    Abstract: A method for improving conformality of oxide layers along sidewalls of vias in semiconductor substrates includes forming a nitride layer over an upper surface of a semiconductor substrate and forming a via extending through the nitride layer and into the semiconductor substrate. The via may have a depth of at least about 50 ?m from a top surface of the nitride layer and an opening of less than about 10 ?m at the top surface of the nitride layer. The method also includes forming an oxide layer over the nitride layer and along sidewalls and bottom of the via. The oxide layer may be formed using a thermal chemical vapor deposition (CVD) process at a temperature of less than about 450° C., where a thickness of the oxide layer at the bottom of the via is at least about 50% of a thickness of the oxide layer at the top surface of the nitride layer.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: March 26, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Zhong Qiang Hua, Manuel A. Hernandez, Lei Luo, Kedar Sapre
  • Publication number: 20130072032
    Abstract: A method for depositing a silicon oxide layer on a substrate including a silicon region and a silicon-germanium region, including the steps of: forming a very thin silicon layer having a thickness ranging from 0.1 to 1 nm above silicon-germanium; and depositing a silicon oxide layer on the substrate.
    Type: Application
    Filed: July 27, 2012
    Publication date: March 21, 2013
    Applicants: STMicroelectronics S.A., International Business Machines Corporation, STMicroelectronics (Crolles 2) SAS
    Inventors: Didier Dutartre, Nicolas Breil, Yves Campidelli, Olivier Gourhant
  • Patent number: 8399363
    Abstract: Methods of forming integrated circuit substrates include forming first and second trenches having unequal widths in a semiconductor substrate and then depositing a first oxide layer at a first temperature into the first and second trenches. The first oxide layer has a thickness sufficient to completely fill the first trench but only partially fill the second trench, which is wider than the first trench. A step is also performed to selectively remove a portion of the first oxide layer from a bottom of the second trench. A second oxide layer is then deposited at a second temperature onto the bottom of the second trench. The second temperature is greater than the first temperature. For example, the first temperature may be in a range from about 300° C. to about 460° C. and the second temperature may be in a range from about 500° C. to about 600° C.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: March 19, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-chan Lee, Seung-jae Lee, Jin-gi Hong, Young-min Ko
  • Patent number: 8394668
    Abstract: Oxide thin film, electronic devices including the oxide thin film and methods of manufacturing the oxide thin film, the methods including (A) applying an oxide precursor solution comprising at least one of zinc (Zn), indium (In) and tin (Sn) on a substrate, (B) heat-treating the oxide precursor solution to form an oxide layer, and (C) repeating the steps (A) and (B) to form a plurality of the oxide layers.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: March 12, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Baek Seon, Myung-Kwan Ryu, Kyung-Bae Park, Sang-Yoon Lee, Bon-Won Koo
  • Patent number: 8394656
    Abstract: MEMS devices (such as interferometric modulators) may be fabricated using a sacrificial layer that contains a heat vaporizable polymer to form a gap between a moveable layer and a substrate. One embodiment provides a method of making a MEMS device that includes depositing a polymer layer over a substrate, forming an electrically conductive layer over the polymer layer, and vaporizing at least a portion of the polymer layer to form a cavity between the substrate and the electrically conductive layer.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: March 12, 2013
    Assignee: Qualcomm MEMS Technologies, Inc.
    Inventors: Chun-Ming Wang, Jeffrey Lan, Teruo Sasagawa
  • Patent number: 8367924
    Abstract: The present invention relates to methods and apparatuses for providing a buried insulator isolation for solar cell contacts. According to certain aspects, the invention places a buried oxide under the emitter of a polysilicon emitter solar cell. The oxide provides an excellent passivation layer over most of the surface. Holes in the oxide provide contact areas, increasing the current density to enhance efficiency. The oxide isolates the contacts from the substrate, achieving the advantage of a selective emitter structure without requiring deep diffusions. The oxide further enables use of screen printing on advanced shallow emitter cells. Positioning of the grid lines close to the openings also enables use of a very thin emitter to maximize blue response.
    Type: Grant
    Filed: January 27, 2009
    Date of Patent: February 5, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Peter Borden, Li Xu
  • Patent number: 8367557
    Abstract: A method of manufacturing a semiconductor device, the method comprising: forming an oxide film on a substrate by alternately repeating: (a) forming an element-containing layer on the substrate by supplying a source gas containing an element into a process vessel accommodating the substrate; and (b) changing the element-containing layer to an oxide layer by supplying an oxygen-containing gas and a hydrogen-containing gas into the process vessel having an inside pressure lower than atmospheric pressure, reacting the oxygen-containing gas with the hydrogen-containing gas to generate oxidizing species containing oxygen, and oxidizing the element-containing layer by the oxidizing species; wherein the hydrogen-containing gas is supplied into the process vessel together with the source gas in step (a).
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: February 5, 2013
    Assignee: Hitachi Kokosai Electric, Inc.
    Inventors: Naonori Akae, Yoshiro Hirose, Yushin Takasawa, Yosuke Ota
  • Patent number: 8357619
    Abstract: A silicon-containing insulating film is formed on a target substrate by CVD, in a process field to be selectively supplied with a first process gas including di-iso-propylaminosilane gas and a second process gas including an oxidizing gas or nitriding gas. The film is formed by performing a plurality of times a cycle alternately including first and second steps. The first step performs supply of the first process gas, thereby forming an adsorption layer containing silicon on a surface of the target substrate. The second performs supply of the second process gas, thereby oxidizing or nitriding the adsorption layer on the surface of the target substrate. The second step includes an excitation period of supplying the second process gas to the process field while exciting the second process gas by an exciting mechanism.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: January 22, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Kazuhide Hasebe, Shigeru Nakajima, Jun Ogawa
  • Publication number: 20130015502
    Abstract: A structure and method for fabricating a light emitting diode and a light detecting diode on a silicon-on-insulator (SOI) wafer is provided. Specifically, the structure and method involves forming a light emitting diode and light detecting diode on the SOI wafer's backside and utilizing a deep trench formed in the wafer as an alignment marker. The alignment marker can be detected by x-ray diffraction, reflectivity, or diffraction grating techniques. Moreover, the alignment marker can be utilized to pattern openings and perform ion implantation to create p-n junctions for the light emitting diode and light detecting diode. By utilizing the SOI wafer's backside, the structure and method increases the number of light emitting diodes and light detecting diodes that can be formed on a SOI wafer, enables an increase in overall device density for an integrated circuit, and reduces attenuation of light signals being emitted and detected by the diodes.
    Type: Application
    Filed: July 11, 2011
    Publication date: January 17, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin A. Fox, Nathaniel J. Gibbs, Andrew B. Maki, David M. Onsongo, Trevor J. Timpane
  • Patent number: 8349746
    Abstract: Embodiments of the present invention pertain to the formation of microelectronic structures. Low k dielectric materials need to exhibit a dielectric constant of less than about 2.6 for the next technology node of 32 nm. The present invention enables the formation of semiconductor devices which make use of such low k dielectric materials while providing an improved flexural and shear strength integrity of the microelectronic structure as a whole.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: January 8, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Bo Xie, Alexandros T. Demos, Daemian Raj, Sure Ngo, Kang Sub Yim
  • Patent number: 8349694
    Abstract: When forming the strain-inducing semiconductor alloy in one type of transistor of a sophisticated semiconductor device, superior thickness uniformity of a dielectric cap material of the gate electrode structures may be achieved by forming encapsulating spacer elements on each gate electrode structure and providing an additional hard mask material. Consequently, in particular, in sophisticated replacement gate approaches, the dielectric cap material may be efficiently removed in a later manufacturing stage, thereby avoiding any irregularities upon replacing the semiconductor material by an electrode metal.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: January 8, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Markus Lenski, Andy Wei, Martin Gerhardt
  • Patent number: 8343881
    Abstract: A silicon dioxide layer is deposited onto a substrate using a process gas comprising BDEAS and an oxygen-containing gas such as ozone. The silicon dioxide layer can be part of an etch-resistant stack that includes a resist layer. In another version, the silicon dioxide layer is deposited into through holes to form an oxide liner for through-silicon vias.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: January 1, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Yong-Won Lee, Vladimir Zubkov, Mei-Yee Shek, Li-Qun Xia, Prahallad Iyengar, Sanjeev Baluja, Scott A Hendrickson, Juan Carlos Rocha-Alvarez, Thomas Nowak, Derek R Witty
  • Patent number: 8338220
    Abstract: Embodiments of the invention are directed to methods and apparatus for processing of a solar substrate for making a photovoltaic device. In particular, methods and apparatus for creating a negatively charged passivation layer by are provided.
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: December 25, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Peter G. Borden, Christopher Sean Olsen
  • Patent number: 8334181
    Abstract: A double gate germanium metal-oxide semiconductor field-effect transistor (MOSFET) includes a germanium fin, a first gate formed adjacent a first side of the germanium fin, and a second gate formed adjacent a second side of the germanium fin opposite the first side. A triple gate MOSFET includes a germanium fin, a first gate formed adjacent a first side of the germanium fin, a second gate formed adjacent a second side of the germanium fin opposite the first side, and a top gate formed on top of the germanium fin. An all-around gate MOSFET includes a germanium fin, a first sidewall gate structure formed adjacent a first side of the germanium fin, a second sidewall gate structure formed adjacent a second side of the germanium fin, and additional gate structures formed on and around the germanium fin.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: December 18, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Judy Xilin An, Zoran Krivokapic, Haihong Wang, Bin Yu
  • Patent number: 8334222
    Abstract: A processing method of a semiconductor wafer is provided. The method comprising the steps of: removing at least part of oxide film from a surface of the semiconductor wafer; removing liquid from the surface; and providing at least partial oxide film on the surface by applying an oxidizing gas wherein a gas flow of the oxidizing gas and/or an ambient gas involved by the oxidizing gas is characterized by an unsaturated vapor pressure of the liquid such that the liquid on the surface vaporizes. The above-described steps are conducted in this order.
    Type: Grant
    Filed: May 1, 2009
    Date of Patent: December 18, 2012
    Assignee: Sumco Techxiv Corporation
    Inventors: Isamu Gotou, Tomonori Kawasaki
  • Publication number: 20120315770
    Abstract: A method of manufacturing a semiconductor device according to the invention includes the step S1 of cleaning the silicon carbide substrate 1 surface, the step S2 of bringing a material gas into a plasma and irradiating the atoms contained in the material gas to silicon carbide substrate 1 for growing silicon nitride film 2 on silicon carbide substrate 1, the step S3 of depositing silicon oxide film 3 on silicon nitride film 2 by the ECR plasma CVD method, and the step S4 of annealing silicon carbide substrate 1 including silicon nitride film 2 and silicon oxide film 3 formed thereon in a nitrogen atmosphere. By the method of manufacturing a semiconductor device according to the invention, a semiconductor device that exhibits excellent interface properties including an interface state density and a flat band voltage is obtained.
    Type: Application
    Filed: May 21, 2012
    Publication date: December 13, 2012
    Applicants: KYUSHU UNIVERSITY, NATIONAL UNIVERSITY CORP., FUJI ELECTRIC CO., LTD.
    Inventors: Hiroshi Nakashima, Haigui Yang, Hitoshi Sumida
  • Patent number: 8330193
    Abstract: The present invention provides a high-performance silicon oxide film as a gate insulation film and a semiconductor device having superior electric characteristics. The silicon oxide film according to the present invention includes CO2 in the film, wherein, when an integrated intensity of a peak is expressed by (peak width at half height)×(peak height) in an infrared absorption spectrum, the integrated intensity of a CO2-attributed peak which appears in the vicinity of a wave number of 2,340 cm?1 is 8E-4 times or more with respect to the integrated intensity of an SiO2-attributed peak which appears in the vicinity of a wave number of 1,060 cm?1.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: December 11, 2012
    Assignee: NLT Technologies, Ltd.
    Inventors: Shigeru Mori, Hiroshi Tanabe, Jun Tanaka
  • Patent number: 8329598
    Abstract: Methods of forming a top oxide around a charge storage material layer of a memory cell and methods of improving quality of a top oxide around a charge storage material layer of a memory cell are provided. The method can involve providing a charge storage layer on a semiconductor substrate, a nitride layer on the charge storage layer, and a first poly layer on the nitride layer, and converting at least a portion of the nitride layer to a top oxide. By converting at least a portion of a nitride layer to a top oxide layer, the quality of the resultant top oxide layer can be improved.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: December 11, 2012
    Assignee: Spansion LLC
    Inventors: Chungho Lee, Kuo-Tung Chang, Hiroyuki Kinoshita, Huaqiang Wu, Fred Cheung
  • Patent number: 8324119
    Abstract: When forming sophisticated gate electrode structures requiring a threshold adjusting semiconductor alloy for one type of transistor, a recess is formed in the corresponding active region, thereby providing superior process uniformity during the deposition of the semiconductor material. Due to the recess, any exposed sidewall surface areas of the active region may be avoided during the selective epitaxial growth process, thereby significantly contributing to enhanced threshold stability of the resulting transistor including the high-k metal gate stack.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: December 4, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Carsten Reichel, Thorsten Kammler, Annekathrin Zeun, Stephan Kronholz
  • Patent number: 8318582
    Abstract: A method of forming a trench isolation, comprising the steps of: applying a silicone resin composition comprising a silicone resin which is represented by the following rational formula (1) and is solid at 120° C.: (H2SiO)n(HSiO1.5)m(SiO2)k??(1) (wherein n, m and k are each a number, with the proviso that when n+m+k=1, n is 0 to 0.8, m is 0 to 1.0, and k is 0 to 0.2) and an organic solvent to a substrate having trenches in such a manner that the trenches of the substrate are filled with the silicone resin composition so as to form a coating film; and carrying out the step of bringing the coating film into contact with at least one selected from the group consisting of water, an alcohol and hydrogen peroxide and the step of subjecting the coating film to at least one treatment selected from the group consisting of a heat treatment and an optical treatment.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: November 27, 2012
    Assignee: JSR Corporation
    Inventors: Seitarou Hattori, Manabu Sekiguchi, Terukazu Kokubo, Kentaro Tamaki, Tsuyoshi Furukawa, Taichi Matsumoto, Chiaki Miyamoto
  • Patent number: 8318584
    Abstract: The formation of a gap-filling silicon oxide layer with reduced volume fraction of voids is described. The deposition involves the formation of an oxygen-rich less-flowable liner layer before an oxygen-poor more-flowable gapfill layer. However, the liner layer is deposited within the same chamber as the gapfill layer. The liner layer and the gapfill layer may both be formed by combining a radical component with an unexcited silicon-containing precursor (i.e. not directly excited by application of plasma power). The liner layer has more oxygen content than the gapfill layer and deposits more conformally. The deposition rate of the gapfill layer may be increased by the presence of the liner layer. The gapfill layer may contain silicon, oxygen and nitrogen and be converted at elevated temperature to contain more oxygen and less nitrogen. The presence of the gapfill liner provides a source of oxygen underneath the gapfill layer to augment the gas phase oxygen introduced during the conversion.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: November 27, 2012
    Assignee: Applied Materials, Inc.
    Inventors: DongQing Li, Jingmei Liang, Nitin K. Ingle
  • Patent number: 8318588
    Abstract: It is an object of the invention is to provide a method suitable for reprocessing a semiconductor substrate having favorable planarity. Another object of the invention is to manufacture a reprocessed semiconductor substrate by using the method suitable for reprocessing a semiconductor substrate having favorable planarity, and to manufacture an SOI substrate by using the reprocessed semiconductor substrate. A projecting portion of a semiconductor substrate is removed using a method capable of selectively removing a semiconductor region which is damaged by ion irradiation or the like. Further, an oxide film is formed on a surface of the semiconductor substrate when the semiconductor substrate is planarized by a polishing treatment typified by a CMP method, whereby the semiconductor substrate is evenly polished at a uniform rate. Moreover, a reprocessed semiconductor substrate is manufactured using the aforementioned method, and an SOI substrate is manufactured using the reprocessed semiconductor substrate.
    Type: Grant
    Filed: August 19, 2010
    Date of Patent: November 27, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ryota Imahayashi, Hideto Ohnuma
  • Patent number: 8309440
    Abstract: Embodiments described herein provide methods for processing a substrate. One embodiment comprises positioning a substrate in a processing region of a processing chamber, exposing a surface of the substrate disposed in the processing chamber to an oxygen containing gas to form a first oxygen containing layer on the surface, removing at least a portion of the first oxygen containing layer to expose at least a portion of the surface of the substrate, and exposing the surface of the substrate to an oxygen containing gas to form a second oxygen containing layer on the surface.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: November 13, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Errol Antonio C. Sanchez, Johanes Swenberg, David K. Carlson, Roisin L. Doherty
  • Patent number: 8304353
    Abstract: Embodiments disclosed herein pertain to silicon dioxide deposition methods using at least ozone and tetraethylorthosilicate (TEOS) as deposition precursors. In one embodiment, a silicon dioxide deposition method using at least ozone and TEOS as deposition precursors includes flowing precursors comprising ozone and TEOS to a substrate under subatmospheric pressure conditions effective to deposit silicon dioxide-comprising material having an outer surface onto the substrate. The outer surface is treated effective to one of add hydroxyl to or remove hydroxyl from the outer surface in comparison to any hydroxyl presence on the outer surface prior to said treating. After the treating, precursors comprising ozone and TEOS are flowed to the substrate under subatmospheric pressure conditions effective to deposit silicon dioxide-comprising material onto the treated outer surface of the substrate. Other embodiments are contemplated.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: November 6, 2012
    Assignee: Micron Technology, Inc.
    Inventors: John Smythe, Gurtej S. Sandhu
  • Patent number: 8293661
    Abstract: One embodiment of the present invention is to achieve high mobility in a device using an oxide semiconductor and provide a highly reliable display device. An oxide semiconductor layer including a crystal region in which c-axis is aligned in a direction substantially perpendicular to a surface is formed and an oxide insulating layer is formed over and in contact with the oxide semiconductor layer. Oxygen is supplied to the oxide semiconductor layer by third heat treatment. A nitride insulating layer containing hydrogen is formed over the oxide insulating layer and fourth heat treatment is performed, so that hydrogen is supplied at least to an interface between the oxide semiconductor layer and the oxide insulating layer.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: October 23, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8283224
    Abstract: A method of manufacturing a memory cell 200. The method comprises forming a memory stack 215. Forming the memory stack includes pre-treating an insulating layer 210 in a substantially ammonia atmosphere for a period of more than 5 minutes to thereby form a pre-treated insulating layer 310. Forming the memory stack also includes depositing a silicon nitride layer on the pre-treated insulating layer.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: October 9, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Bernard John Fischer
  • Patent number: 8283237
    Abstract: A through-silicon via fabrication method comprises forming a substrate by bonding the front surface of a silicon plate to a carrier using an adhesive layer therebetween to expose the back surface of the silicon plate. A silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate. A plurality of through holes are etched in the silicon plate, the through holes comprising sidewalls and bottom walls. A metallic conductor is deposited in the through holes to form a plurality of through-silicon vias.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: October 9, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Nagarajan Rajagopalan, Ji Ae Park, Ryan Yamase, Shamik Patel, Thomas Nowak, Li-Qun Xia, Bok Hoen Kim, Ran Ding, Jim Baldino, Mehul Naik, Sesh Ramaswami
  • Publication number: 20120248445
    Abstract: High performance thin-film, transistors are entirely processed at temperatures not exceeding 150° C., using amorphous multi component dielectrics based on the mixture of high band gap and high dielectric constant (K) materials. The sputtered or ink jet printed mixed dielectric materials such as Ta2O5 with SiO2 or Al2O3 or HfO2 with SiO2 or Al2O3 are used. These multicomponent dielectrics allow producing amorphous dielectrics to be introduced in high stable electronic devices with low leakage currents, while preserving a high dielectric constant. This results in producing thin film transistors with remarkable electrical properties, such as the ones produced based on Ga—In—Zn oxide as channel layers and where the dielectric was the combination of the mixture Ta2O5:SiO2, exhibiting field-effect mobility exceeding 35 cm2 V?1 s?1, close to 0 V turn-on voltage, on/off ratio higher than 106 and subthreshold slope below 0.24 V dec?1.
    Type: Application
    Filed: August 5, 2010
    Publication date: October 4, 2012
    Applicants: Faculdad de Ciencias e Technologia da Universidade Nova de Lisboa, Universidad de Barcelona, Jozef Stefan Institute
    Inventors: Rodrigo Ferrão De Paiva Martins, Elvira Maria Correia fortunato, Pedro Miguel Cândido Barquinha, Luís Miguel Nunes Pereira, Gonçalo Pedro Gonçalves, Danjela Kuscer Hrovatin, Marija Kosec
  • Patent number: 8268411
    Abstract: A method of forming a porous composite material in which substantially all of the pores within the composite material are small having a diameter of about 5 nm or less and with a narrow PSD is provided. The porous composite material includes a first solid phase having a first characteristic dimension and a second phase comprised of pores having a second characteristic dimension, wherein the characteristic dimensions of at least one of said phases is controlled to a value of about 5 nm or less.
    Type: Grant
    Filed: August 8, 2009
    Date of Patent: September 18, 2012
    Assignee: International Business Machines Corporation
    Inventors: Stephen M. Gates, Alfred Grill, Deborah A. Neumayer, Son Nguyen, Vishnubhai V. Patel
  • Patent number: 8268731
    Abstract: Disclosed is a producing method of a semiconductor device, including: loading a substrate into a reaction tube; oxidizing the substrate under an atmospheric pressure by supplying a plurality of kinds of gases which react with each other and an inert gas into the reaction tube; and unloading, from the reaction tube, the substrate after the oxidizing, wherein in the oxidizing, a flow rate of the inert gas is varied in accordance with a variation of the atmospheric pressure to keep constant a partial pressure of an oxidizing gas or partial pressures of oxidizing gases in the reaction tube, and the flow rate of the inert gas is calculated based on a pre-calculated flow rate of a gas or pre-calculated flow rates of gases produced by reaction of the plurality of gases and a pre-calculated flow rate of a gas which is not consumed by the reaction and which remains or pre-calculated flow rates of gases which are not consumed by the reaction and which remain.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: September 18, 2012
    Assignee: Hitatchi Kokusai Electric Inc.
    Inventors: Naoto Nakamura, Iwao Nakamura, Ryota Sasajima
  • Patent number: 8263502
    Abstract: A substrate structure is produced by forming a first material layer on a substrate having a recess, removing the first material layer from the portion of the substrate except for the recess using a second material that reacts with the first material, and forming a deposition film from the first material layer using a third material that reacts with the first material. A method of manufacturing a device may include the method of forming a substrate structure.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: September 11, 2012
    Assignee: Synos Technology, Inc.
    Inventor: Sang In Lee
  • Patent number: 8252704
    Abstract: This disclosure relates to compositions that include (a) at least one substituted or unsubstituted cyclic alkene, and (b) an antioxidant composition including at least one compound of Formula (I): R1 through R4 in Formula (I) are described in the specification.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: August 28, 2012
    Assignee: Fujifilm Electronic Materials U.S.A., Inc.
    Inventors: Daniel J. Teff, John L. Chagolla
  • Publication number: 20120208375
    Abstract: In a semiconductor device formed on a silicon surface which has a substantial (110) crystal plane orientation, the silicon surface is flattened so that an arithmetical mean deviation of surface Ra is not greater than 0.15 nm, preferably, 0.09 nm, which enables to manufacture an n-MOS transistor of a high mobility. Such a flattened silicon surface is obtained by repeating a deposition process of a self-sacrifice oxide film in an oxygen radical atmosphere and a removing process of the self-sacrifice oxide film, by cleaning the silicon surface in deaerated H2O or a low OH density atmosphere, or by strongly terminating the silicon surface by hydrogen or heavy hydrogen. The deposition process of the self-sacrifice oxide film may be carried out by isotropic oxidation.
    Type: Application
    Filed: April 23, 2012
    Publication date: August 16, 2012
    Inventors: Tadahiro Ohmi, Shigetoshi Sugawa, Akinobu Teramoto, Hiroshi Akahori, Keiichi Nii
  • Patent number: 8242031
    Abstract: A method of depositing a silicon and nitrogen containing film on a substrate. The method includes introducing silicon-containing precursor to a deposition chamber that contains the substrate, wherein the silicon-containing precursor comprises at least two silicon atoms. The method further includes generating at least one radical nitrogen precursor with a remote plasma system located outside the deposition chamber. Moreover, the method includes introducing the radical nitrogen precursor to the deposition chamber, wherein the radical nitrogen and silicon-containing precursors react and deposit the silicon and nitrogen containing film on the substrate. Furthermore, the method includes annealing the silicon and nitrogen containing film in a steam environment to form a silicon oxide film, wherein the steam environment includes water and acidic vapor.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: August 14, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Abhijit Basu Mallick, Srinivas D. Nemani, Ellie Yieh
  • Patent number: 8242004
    Abstract: A method of forming a semiconductor device includes the following processes. A groove is formed in a semiconductor substrate. A first spin-on-dielectric layer is formed over a semiconductor substrate. An abnormal oxidation of the first spin-on-dielectric layer is carried out. A surface of the first spin-on-dielectric layer is removed. A second spin-on-dielectric layer is formed over the first spin-on-dielectric layer. A non-abnormal oxidation of the first and second spin-on-dielectric layers is carried out to modify the second spin-on-dielectric layer without modifying the first spin-on-dielectric layer.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: August 14, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Jiro Miyahara
  • Publication number: 20120202358
    Abstract: Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of electronic devices and systems. In an embodiment, a dielectric layer is graded with respect to a doping profile across the dielectric layer. In an embodiment, a dielectric layer is graded with respect to a crystalline structure profile across the dielectric layer. In an embodiment, a dielectric layer is formed by atomic layer deposition incorporating sequencing techniques to generate a doped dielectric material.
    Type: Application
    Filed: February 3, 2012
    Publication date: August 9, 2012
    Inventors: Dan Gealy, Vishwanath Bhat, Cancheepuram V. Srividya, M. Noel Rocklein
  • Publication number: 20120196451
    Abstract: Catalyzed atomic layer deposition from a reduced number of precursors is described. A deposition precursor contains silicon, oxygen and a catalytic ligand. A hydroxyl-terminated substrate is exposed to the deposition precursor to form a silicon bridge bond between two surface-bound oxygens. The surface-bound oxygens were part of two surface-bound hydroxyl groups and the adsorption of the deposition precursor liberates the hydrogens. The silicon atom is also chemically-bound to one or two additional oxygen atoms which were already chemically-bound to the silicon within a same deposition precursor molecule. At least one of the additional oxygen atoms is further chemically-bound to the catalytic ligand either directly or by way of a hydrocarbon chain. Further exposure of the substrate to moisture (H2O) results in displacement of the additional oxygen which are replaced by hydroxyl groups from the moisture. The surface is again hydroxyl-terminated and the process may be repeated.
    Type: Application
    Filed: August 3, 2011
    Publication date: August 2, 2012
    Applicant: Applied Materials, Inc.
    Inventor: Abhijit Basu Mallick
  • Patent number: 8227357
    Abstract: Methods of fabricating a silicon oxide layer using an inorganic silicon precursor and methods of fabricating a semiconductor device using the same are provided. The methods of fabricating a semiconductor device include forming a tunnel insulating layer and a charge storage layer on a substrate; forming a dielectric layer structure on the charge storage layer using an atomic layer deposition (ALD) method, the dielectric layer structure including a first dielectric layer formed of silicon oxide, a second dielectric layer on the first dielectric layer formed of a material different from the material forming the first dielectric layer, and a third dielectric layer formed of the silicon oxide on the second dielectric layer; and forming a control gate on the dielectric layer structure.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: July 24, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-Sun Yi, Ki-Hyun Hwang, Jin-Tae Noh, Jae-Young Ahn, Si-Young Choi
  • Patent number: 8222688
    Abstract: A semiconductor device includes a substrate, a first oxide layer formed on the substrate, an oxygen-rich nitride layer formed on the first oxide layer, a second oxide layer formed on the oxygen-rich nitride layer, and an oxygen-poor nitride layer formed on the second oxide layer.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: July 17, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventors: Fredrick Jenne, Krishnaswamy Ramkumar
  • Patent number: 8222111
    Abstract: A method for semiconductor fabrication. The method includes providing a silicon substrate and forming a tunnel oxide layer over the silicon substrate. Thereafter, a nitride layer is formed over the tunnel oxide layer. The nitride layer and the tunnel oxide layer are etched except where at least one nonvolatile silicon oxide nitride oxide silicon (SONOS) transistor is formed. Additionally, oxide layers are simultaneously formed over the nitride layer corresponding to where at bast one SONOS memory transistor is formed and over the exposed silicon substrate corresponding to where at least one metal oxide semiconductor (MOS) transistor is formed.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: July 17, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventor: Jeong-Mo Hwang